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L 1 "..\..\User\NAVAGATION\QRcode.c"
N#include "QRcode.h"
L 1 "..\..\User\NAVAGATION\QRcode.h" 1
N#ifndef __QRCODE_H
N#define __QRCODE_H
N#include "bsp.h"
L 1 "..\..\User\bsp\bsp.h" 1
N/*
N*********************************************************************************************************
N*
N*	模块名称 : 底层驱动模块
N*	文件名称 : bsp.h
N*	版    本 : V1.0
N*	说    明 : 这是底层驱动模块所有的h文件的汇总文件。
N*	 	       应用程序只需 #include bsp.h 即可,不需要#include 每个模块的 h 文件
N*
N*	修改记录 :
N*		版本号  日期         作者    说明
N*		v1.0    2012-12-17  Eric2013  ST固件库V1.0.2版本。
N*	
N*********************************************************************************************************
N*/
N
N#ifndef _BSP_H_
N#define _BSP_H_
N
N#define STM32_V5
N//#define STM32_X3
N
N
N/* 检查是否定义了开发板型号 */
N#if !defined (STM32_V5) && !defined (STM32_X3)
X#if !1L && !0L
S	#error "Please define the board model : STM32_X3 or STM32_V5"
N#endif
N
N/* 定义 BSP 版本号 */
N#define __STM32F1_BSP_VERSION		"1.1"
N
N/* CPU空闲时执行的函数 */
N//#define CPU_IDLE()		bsp_Idle()
N
N/* 使能在源文件中使用uCOS-III的函数, 这里的源文件主要是指BSP驱动文件 */
N#define uCOS_EN       1
N
N#if uCOS_EN == 1    
X#if 1 == 1    
N	#include "os.h"   
L 1 "..\..\uCOS-III\uCOS-III\Source\os.h" 1
N/*
N************************************************************************************************************************
N*                                                      uC/OS-III
N*                                                 The Real-Time Kernel
N*
N*                                  (c) Copyright 2009-2012; Micrium, Inc.; Weston, FL
N*                           All rights reserved.  Protected by international copyright laws.
N*
N* File    : OS.H
N* By      : JJL
N* Version : V3.03.01
N*
N* LICENSING TERMS:
N* ---------------
N*           uC/OS-III is provided in source form for FREE short-term evaluation, for educational use or 
N*           for peaceful research.  If you plan or intend to use uC/OS-III in a commercial application/
N*           product then, you need to contact Micrium to properly license uC/OS-III for its use in your 
N*           application/product.   We provide ALL the source code for your convenience and to help you 
N*           experience uC/OS-III.  The fact that the source is provided does NOT mean that you can use 
N*           it commercially without paying a licensing fee.
N*
N*           Knowledge of the source code may NOT be used to develop a similar product.
N*
N*           Please help us continue to provide the embedded community with the finest software available.
N*           Your honesty is greatly appreciated.
N*
N*           You can contact us at www.micrium.com, or by phone at +1 (954) 217-2036.
N************************************************************************************************************************
N* Note(s) : (1) Assumes the following versions (or more recent) of software modules are included in the project build:
N*
N*               (a) uC/LIB V1.36.01
N*               (b) uC/CPU V1.29.00
N************************************************************************************************************************
N*/
N
N#ifndef   OS_H
N#define   OS_H
N
N/*
N************************************************************************************************************************
N*                                               uC/OS-III VERSION NUMBER
N************************************************************************************************************************
N*/
N
N#define  OS_VERSION  30301u                       /* Version of uC/OS-III (Vx.yy.zz mult. by 10000)                   */
N
N/*
N************************************************************************************************************************
N*                                                 INCLUDE HEADER FILES
N************************************************************************************************************************
N*/
N
N#ifdef __cplusplus
Sextern "C" {
N#endif
N
N
N
N#include <os_cfg.h>
L 1 "..\..\User\os_cfg.h" 1
N/*
N************************************************************************************************************************
N*                                                      uC/OS-III
N*                                                 The Real-Time Kernel
N*
N*                                  (c) Copyright 2009-2011; Micrium, Inc.; Weston, FL
N*                           All rights reserved.  Protected by international copyright laws.
N*
N*                                                  CONFIGURATION FILE
N*
N* File    : OS_CFG.H
N* By      : JJL
N* Version : V3.02.00
N*
N* LICENSING TERMS:
N* ---------------
N*           uC/OS-III is provided in source form for FREE short-term evaluation, for educational use or 
N*           for peaceful research.  If you plan or intend to use uC/OS-III in a commercial application/
N*           product then, you need to contact Micrium to properly license uC/OS-III for its use in your 
N*           application/product.   We provide ALL the source code for your convenience and to help you 
N*           experience uC/OS-III.  The fact that the source is provided does NOT mean that you can use 
N*           it commercially without paying a licensing fee.
N*
N*           Knowledge of the source code may NOT be used to develop a similar product.
N*
N*           Please help us continue to provide the embedded community with the finest software available.
N*           Your honesty is greatly appreciated.
N*
N*           You can contact us at www.micrium.com, or by phone at +1 (954) 217-2036.
N************************************************************************************************************************
N*/
N
N#ifndef OS_CFG_H
N#define OS_CFG_H
N
N
N                                             /* ---------------------------- MISCELLANEOUS -------------------------- */
N#define OS_CFG_APP_HOOKS_EN             0u   /* Enable (1) or Disable (0) application specific hooks                  */
N#define OS_CFG_ARG_CHK_EN               0u   /* Enable (1) or Disable (0) argument checking                           */
N#define OS_CFG_CALLED_FROM_ISR_CHK_EN   0u   /* Enable (1) or Disable (0) check for called from ISR                   */
N#define OS_CFG_DBG_EN                   0u   /* Enable (1) debug code/variables                                       */
N#define OS_CFG_ISR_POST_DEFERRED_EN     0u   /* Enable (1) or Disable (0) Deferred ISR posts                          */
N#define OS_CFG_OBJ_TYPE_CHK_EN          0u   /* Enable (1) or Disable (0) object type checking                        */
N#define OS_CFG_TS_EN                    0u   /* Enable (1) or Disable (0) time stamping                               */
N
N#define OS_CFG_PEND_MULTI_EN            0u   /* Enable (1) or Disable (0) code generation for multi-pend feature      */
N
N#define OS_CFG_PRIO_MAX                16u   /* Defines the maximum number of task priorities (see OS_PRIO data type) */
N
N#define OS_CFG_SCHED_LOCK_TIME_MEAS_EN  0u   /* Include code to measure scheduler lock time                           */
N#define OS_CFG_SCHED_ROUND_ROBIN_EN     0u   /* Include code for Round-Robin scheduling                               */
N#define OS_CFG_STK_SIZE_MIN            64u   /* Minimum allowable task stack size                                     */
N
N
N                                             /* ----------------------------- EVENT FLAGS --------------------------- */
N#define OS_CFG_FLAG_EN                  0u   /* Enable (1) or Disable (0) code generation for EVENT FLAGS             */
N#define OS_CFG_FLAG_DEL_EN              1u   /*     Include code for OSFlagDel()                                      */
N#define OS_CFG_FLAG_MODE_CLR_EN         1u   /*     Include code for Wait on Clear EVENT FLAGS                        */
N#define OS_CFG_FLAG_PEND_ABORT_EN       1u   /*     Include code for OSFlagPendAbort()                                */
N
N
N                                             /* -------------------------- MEMORY MANAGEMENT ------------------------ */
N#define OS_CFG_MEM_EN                   0u   /* Enable (1) or Disable (0) code generation for MEMORY MANAGER          */
N
N
N                                             /* --------------------- MUTUAL EXCLUSION SEMAPHORES ------------------- */
N#define OS_CFG_MUTEX_EN                 0u   /* Enable (1) or Disable (0) code generation for MUTEX                   */
N#define OS_CFG_MUTEX_DEL_EN             1u   /*     Include code for OSMutexDel()                                     */
N#define OS_CFG_MUTEX_PEND_ABORT_EN      1u   /*     Include code for OSMutexPendAbort()                               */
N
N
N                                             /* --------------------------- MESSAGE QUEUES -------------------------- */
N#define OS_CFG_Q_EN                     0u   /* Enable (1) or Disable (0) code generation for QUEUES                  */
N#define OS_CFG_Q_DEL_EN                 1u   /*     Include code for OSQDel()                                         */
N#define OS_CFG_Q_FLUSH_EN               1u   /*     Include code for OSQFlush()                                       */
N#define OS_CFG_Q_PEND_ABORT_EN          1u   /*     Include code for OSQPendAbort()                                   */
N
N
N                                             /* ----------------------------- SEMAPHORES ---------------------------- */
N#define OS_CFG_SEM_EN                   0u   /* Enable (1) or Disable (0) code generation for SEMAPHORES              */
N#define OS_CFG_SEM_DEL_EN               1u   /*    Include code for OSSemDel()                                        */
N#define OS_CFG_SEM_PEND_ABORT_EN        1u   /*    Include code for OSSemPendAbort()                                  */
N#define OS_CFG_SEM_SET_EN               1u   /*    Include code for OSSemSet()                                        */
N
N
N                                             /* -------------------------- TASK MANAGEMENT -------------------------- */
N#define OS_CFG_STAT_TASK_EN             0u   /* Enable (1) or Disable(0) the statistics task                          */
N#define OS_CFG_STAT_TASK_STK_CHK_EN     1u   /* Check task stacks from statistic task                                 */
N
N#define OS_CFG_TASK_CHANGE_PRIO_EN      0u   /* Include code for OSTaskChangePrio()                                   */
N#define OS_CFG_TASK_DEL_EN              0u   /* Include code for OSTaskDel()                                          */
N#define OS_CFG_TASK_Q_EN                0u   /* Include code for OSTaskQXXXX()                                        */
N#define OS_CFG_TASK_Q_PEND_ABORT_EN     0u   /* Include code for OSTaskQPendAbort()                                   */
N#define OS_CFG_TASK_PROFILE_EN          0u   /* Include variables in OS_TCB for profiling                             */
N#define OS_CFG_TASK_REG_TBL_SIZE        1u   /* Number of task specific registers                                     */
N#define OS_CFG_TASK_SEM_PEND_ABORT_EN   0u   /* Include code for OSTaskSemPendAbort()                                 */
N#define OS_CFG_TASK_SUSPEND_EN          0u   /* Include code for OSTaskSuspend() and OSTaskResume()                   */
N
N
N                                             /* -------------------------- TIME MANAGEMENT -------------------------- */
N#define OS_CFG_TIME_DLY_HMSM_EN         1u   /*     Include code for OSTimeDlyHMSM()                                  */
N#define OS_CFG_TIME_DLY_RESUME_EN       1u   /*     Include code for OSTimeDlyResume()                                */
N
N
N                                             /* ------------------------- TIMER MANAGEMENT -------------------------- */
N#define OS_CFG_TMR_EN                   0u   /* Enable (1) or Disable (0) code generation for TIMERS                  */
N#define OS_CFG_TMR_DEL_EN               0u   /* Enable (1) or Disable (0) code generation for OSTmrDel()              */
N
N#endif
L 60 "..\..\uCOS-III\uCOS-III\Source\os.h" 2
N#include <cpu.h>
L 1 "..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView\cpu.h" 1
N/*
N*********************************************************************************************************
N*                                                uC/CPU
N*                                    CPU CONFIGURATION & PORT LAYER
N*
N*                          (c) Copyright 2004-2011; Micrium, Inc.; Weston, FL
N*
N*               All rights reserved.  Protected by international copyright laws.
N*
N*               uC/CPU is provided in source form to registered licensees ONLY.  It is 
N*               illegal to distribute this source code to any third party unless you receive 
N*               written permission by an authorized Micrium representative.  Knowledge of 
N*               the source code may NOT be used to develop a similar product.
N*
N*               Please help us continue to provide the Embedded community with the finest 
N*               software available.  Your honesty is greatly appreciated.
N*
N*               You can contact us at www.micrium.com.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*
N*                                            CPU PORT FILE
N*
N*                                            ARM-Cortex-M4
N*                                      RealView Development Suite
N*                            RealView Microcontroller Development Kit (MDK)
N*                                       ARM Developer Suite (ADS)
N*                                            Keil uVision
N*
N* Filename      : cpu.h
N* Version       : V1.29.01.00
N* Programmer(s) : JJL
N*                 BAN
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                               MODULE
N*
N* Note(s) : (1) This CPU header file is protected from multiple pre-processor inclusion through use of 
N*               the  CPU module present pre-processor macro definition.
N*********************************************************************************************************
N*/
N
N#ifndef  CPU_MODULE_PRESENT                                     /* See Note #1.                                         */
N#define  CPU_MODULE_PRESENT
N
N
N/*
N*********************************************************************************************************
N*                                          CPU INCLUDE FILES
N*
N* Note(s) : (1) The following CPU files are located in the following directories :
N*
N*               (a) \<Your Product Application>\cpu_cfg.h
N*
N*               (b) (1) \<CPU-Compiler Directory>\cpu_def.h
N*                   (2) \<CPU-Compiler Directory>\<cpu>\<compiler>\cpu*.*
N*
N*                       where
N*                               <Your Product Application>      directory path for Your Product's Application
N*                               <CPU-Compiler Directory>        directory path for common   CPU-compiler software
N*                               <cpu>                           directory name for specific CPU
N*                               <compiler>                      directory name for specific compiler
N*
N*           (2) Compiler MUST be configured to include as additional include path directories :
N*
N*               (a) '\<Your Product Application>\' directory                            See Note #1a
N*
N*               (b) (1) '\<CPU-Compiler Directory>\'                  directory         See Note #1b1
N*                   (2) '\<CPU-Compiler Directory>\<cpu>\<compiler>\' directory         See Note #1b2
N*
N*           (3) Since NO custom library modules are included, 'cpu.h' may ONLY use configurations from
N*               CPU configuration file 'cpu_cfg.h' that do NOT reference any custom library definitions.
N*
N*               In other words, 'cpu.h' may use 'cpu_cfg.h' configurations that are #define'd to numeric
N*               constants or to NULL (i.e. NULL-valued #define's); but may NOT use configurations to
N*               custom library #define's (e.g. DEF_DISABLED or DEF_ENABLED).
N*********************************************************************************************************
N*/
N
N#include  <cpu_def.h>
L 1 "..\..\uCOS-III\uC-CPU\cpu_def.h" 1
N/*
N*********************************************************************************************************
N*                                                uC/CPU
N*                                    CPU CONFIGURATION & PORT LAYER
N*
N*                          (c) Copyright 2004-2011; Micrium, Inc.; Weston, FL
N*
N*               All rights reserved.  Protected by international copyright laws.
N*
N*               uC/CPU is provided in source form to registered licensees ONLY.  It is 
N*               illegal to distribute this source code to any third party unless you receive 
N*               written permission by an authorized Micrium representative.  Knowledge of 
N*               the source code may NOT be used to develop a similar product.
N*
N*               Please help us continue to provide the Embedded community with the finest 
N*               software available.  Your honesty is greatly appreciated.
N*
N*               You can contact us at www.micrium.com.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*
N*                                      CPU CONFIGURATION DEFINES
N*
N* Filename      : cpu_def.h
N* Version       : V1.29.01
N* Programmer(s) : ITJ
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                               MODULE
N*
N* Note(s) : (1) This CPU definition header file is protected from multiple pre-processor inclusion 
N*               through use of the CPU definition module present pre-processor macro definition.
N*********************************************************************************************************
N*/
N
N#ifndef  CPU_DEF_MODULE_PRESENT
N#define  CPU_DEF_MODULE_PRESENT
N
N
N/*
N*********************************************************************************************************
N*                                   CORE CPU MODULE VERSION NUMBER
N*
N* Note(s) : (1) (a) The core CPU module software version is denoted as follows :
N*
N*                       Vx.yy.zz
N*
N*                           where
N*                                   V               denotes 'Version' label
N*                                   x               denotes     major software version revision number
N*                                   yy              denotes     minor software version revision number
N*                                   zz              denotes sub-minor software version revision number
N*
N*               (b) The software version label #define is formatted as follows :
N*
N*                       ver = x.yyzz * 100 * 100
N*
N*                           where
N*                                   ver             denotes software version number scaled as an integer value
N*                                   x.yyzz          denotes software version number, where the unscaled integer 
N*                                                       portion denotes the major version number & the unscaled 
N*                                                       fractional portion denotes the (concatenated) minor 
N*                                                       version numbers
N*********************************************************************************************************
N*/
N
N#define  CPU_CORE_VERSION                              12901u   /* See Note #1.                                         */
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                       CPU WORD CONFIGURATION
N*
N* Note(s) : (1) Configure CPU_CFG_ADDR_SIZE & CPU_CFG_DATA_SIZE in 'cpu.h' with CPU's word sizes :
N*
N*                   CPU_WORD_SIZE_08             8-bit word size
N*                   CPU_WORD_SIZE_16            16-bit word size
N*                   CPU_WORD_SIZE_32            32-bit word size
N*                   CPU_WORD_SIZE_64            64-bit word size
N*
N*           (2) Configure CPU_CFG_ENDIAN_TYPE in 'cpu.h' with CPU's data-word-memory order :
N*
N*               (a) CPU_ENDIAN_TYPE_BIG         Big-   endian word order (CPU words' most  significant
N*                                                                         octet @ lowest memory address)
N*               (b) CPU_ENDIAN_TYPE_LITTLE      Little-endian word order (CPU words' least significant
N*                                                                         octet @ lowest memory address)
N*********************************************************************************************************
N*/
N
N                                                        /* ---------------------- CPU WORD SIZE ----------------------- */
N#define  CPU_WORD_SIZE_08                          1    /*  8-bit word size (in octets).                                */
N#define  CPU_WORD_SIZE_16                          2    /* 16-bit word size (in octets).                                */
N#define  CPU_WORD_SIZE_32                          4    /* 32-bit word size (in octets).                                */
N#define  CPU_WORD_SIZE_64                          8    /* 64-bit word size (in octets).                                */
N
N
N                                                        /* ------------------ CPU WORD-ENDIAN ORDER ------------------- */
N#define  CPU_ENDIAN_TYPE_NONE                      0u
N#define  CPU_ENDIAN_TYPE_BIG                       1u   /* Big-   endian word order (see Note #1a).                     */
N#define  CPU_ENDIAN_TYPE_LITTLE                    2u   /* Little-endian word order (see Note #1b).                     */
N
N
N/*
N*********************************************************************************************************
N*                                       CPU STACK CONFIGURATION
N*
N* Note(s) : (1) Configure CPU_CFG_STK_GROWTH in 'cpu.h' with CPU's stack growth order :
N*
N*               (a) CPU_STK_GROWTH_LO_TO_HI     CPU stack pointer increments to the next higher  stack 
N*                                                   memory address after data is pushed onto the stack
N*               (b) CPU_STK_GROWTH_HI_TO_LO     CPU stack pointer decrements to the next lower   stack 
N*                                                   memory address after data is pushed onto the stack
N*********************************************************************************************************
N*/
N
N                                                        /* ------------------ CPU STACK GROWTH ORDER ------------------ */
N#define  CPU_STK_GROWTH_NONE                       0u
N#define  CPU_STK_GROWTH_LO_TO_HI                   1u   /* CPU stk incs towards higher mem addrs (see Note #1a).        */
N#define  CPU_STK_GROWTH_HI_TO_LO                   2u   /* CPU stk decs towards lower  mem addrs (see Note #1b).        */
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                   CRITICAL SECTION CONFIGURATION
N*
N* Note(s) : (1) Configure CPU_CFG_CRITICAL_METHOD with CPU's/compiler's critical section method :
N*
N*                                                       Enter/Exit critical sections by ...
N*
N*                   CPU_CRITICAL_METHOD_INT_DIS_EN      Disable/Enable interrupts
N*                   CPU_CRITICAL_METHOD_STATUS_STK      Push/Pop       interrupt status onto stack
N*                   CPU_CRITICAL_METHOD_STATUS_LOCAL    Save/Restore   interrupt status to local variable
N*
N*               (a) CPU_CRITICAL_METHOD_INT_DIS_EN  is NOT a preferred method since it does NOT support
N*                   multiple levels of interrupts.  However, with some CPUs/compilers, this is the only
N*                   available method.
N*
N*               (b) CPU_CRITICAL_METHOD_STATUS_STK    is one preferred method since it supports multiple
N*                   levels of interrupts.  However, this method assumes that the compiler provides C-level
N*                   &/or assembly-level functionality for the following :
N*
N*                     ENTER CRITICAL SECTION :
N*                       (1) Push/save   interrupt status onto a local stack
N*                       (2) Disable     interrupts
N*
N*                     EXIT  CRITICAL SECTION :
N*                       (3) Pop/restore interrupt status from a local stack
N*
N*               (c) CPU_CRITICAL_METHOD_STATUS_LOCAL  is one preferred method since it supports multiple
N*                   levels of interrupts.  However, this method assumes that the compiler provides C-level
N*                   &/or assembly-level functionality for the following :
N*
N*                     ENTER CRITICAL SECTION :
N*                       (1) Save    interrupt status into a local variable
N*                       (2) Disable interrupts
N*
N*                     EXIT  CRITICAL SECTION :
N*                       (3) Restore interrupt status from a local variable
N*
N*           (2) Critical section macro's most likely require inline assembly.  If the compiler does NOT
N*               allow inline assembly in C source files, critical section macro's MUST call an assembly
N*               subroutine defined in a 'cpu_a.asm' file located in the following software directory :
N*
N*                   \<CPU-Compiler Directory>\<cpu>\<compiler>\
N*
X
N*                       where
N*                               <CPU-Compiler Directory>    directory path for common   CPU-compiler software
N*                               <cpu>                       directory name for specific CPU
N*                               <compiler>                  directory name for specific compiler
N*
N*           (3) (a) To save/restore interrupt status, a local variable 'cpu_sr' of type 'CPU_SR' MAY need 
N*                   to be declared (e.g. if 'CPU_CRITICAL_METHOD_STATUS_LOCAL' method is configured).
N*
N*                   (1) 'cpu_sr' local variable SHOULD be declared via the CPU_SR_ALLOC() macro which, 
N*                        if used, MUST be declared following ALL other local variables (see any 'cpu.h  
N*                        CRITICAL SECTION CONFIGURATION  Note #3a1').
N*
N*                        Example :
N*
N*                           void  Fnct (void)
N*                           {
N*                               CPU_INT08U  val_08;
N*                               CPU_INT16U  val_16;
N*                               CPU_INT32U  val_32;
N*                               CPU_SR_ALLOC();         MUST be declared after ALL other local variables
N*                                   :
N*                                   :
N*                           }
N*
N*               (b) Configure 'CPU_SR' data type with the appropriate-sized CPU data type large enough to 
N*                   completely store the CPU's/compiler's status word.
N*********************************************************************************************************
N*/
N
N                                                        /* --------------- CPU CRITICAL SECTION METHODS --------------- */
N#define  CPU_CRITICAL_METHOD_NONE                  0u   /*                                                              */
N#define  CPU_CRITICAL_METHOD_INT_DIS_EN            1u   /* DIS/EN       ints                    (see Note #1a).         */
N#define  CPU_CRITICAL_METHOD_STATUS_STK            2u   /* Push/Pop     int status onto stk     (see Note #1b).         */
N#define  CPU_CRITICAL_METHOD_STATUS_LOCAL          3u   /* Save/Restore int status to local var (see Note #1c).         */
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                             MODULE END
N*
N* Note(s) : (1) See 'cpu_def.h  MODULE'.
N*********************************************************************************************************
N*/
N
N#endif                                                  /* End of CPU def module include.                               */
N
L 88 "..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView\cpu.h" 2
N#include  <cpu_cfg.h>                                           /* See Note #3.                                         */
L 1 "..\..\User\cpu_cfg.h" 1
N/*
N*********************************************************************************************************
N*                                                uC/CPU
N*                                    CPU CONFIGURATION & PORT LAYER
N*
N*                          (c) Copyright 2004-2011; Micrium, Inc.; Weston, FL
N*
N*               All rights reserved.  Protected by international copyright laws.
N*
N*               uC/CPU is provided in source form to registered licensees ONLY.  It is 
N*               illegal to distribute this source code to any third party unless you receive 
N*               written permission by an authorized Micrium representative.  Knowledge of 
N*               the source code may NOT be used to develop a similar product.
N*
N*               Please help us continue to provide the Embedded community with the finest 
N*               software available.  Your honesty is greatly appreciated.
N*
N*               You can contact us at www.micrium.com.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*
N*                                       CPU CONFIGURATION FILE
N*
N*                                              TEMPLATE
N*
N* Filename      : cpu_cfg.h
N* Version       : V1.29.01
N* Programmer(s) : SR
N*                 ITJ
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                               MODULE
N*********************************************************************************************************
N*/
N
N#ifndef  CPU_CFG_MODULE_PRESENT
N#define  CPU_CFG_MODULE_PRESENT
N
N
N/*
N*********************************************************************************************************
N*                                       CPU NAME CONFIGURATION
N*
N* Note(s) : (1) Configure CPU_CFG_NAME_EN to enable/disable CPU host name feature :
N*
N*               (a) CPU host name storage
N*               (b) CPU host name API functions
N*
N*           (2) Configure CPU_CFG_NAME_SIZE with the desired ASCII string size of the CPU host name, 
N*               including the terminating NULL character.
N*
N*               See also 'cpu_core.h  GLOBAL VARIABLES  Note #1'.
N*********************************************************************************************************
N*/
N
N                                                                /* Configure CPU host name feature (see Note #1) :      */
N#define  CPU_CFG_NAME_EN                         DEF_ENABLED
N                                                                /*   DEF_DISABLED  CPU host name DISABLED               */
N                                                                /*   DEF_ENABLED   CPU host name ENABLED                */
N
N                                                                /* Configure CPU host name ASCII string size ...        */
N#define  CPU_CFG_NAME_SIZE                                16    /* ... (see Note #2).                                   */
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                     CPU TIMESTAMP CONFIGURATION
N*
N* Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
N*
N*               (a) CPU_CFG_TS_32_EN   enable/disable 32-bit CPU timestamp feature
N*               (b) CPU_CFG_TS_64_EN   enable/disable 64-bit CPU timestamp feature
N*
N*           (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
N*
N*                       CPU_WORD_SIZE_08         8-bit word size
N*                       CPU_WORD_SIZE_16        16-bit word size
N*                       CPU_WORD_SIZE_32        32-bit word size
N*                       CPU_WORD_SIZE_64        64-bit word size
N*
N*               (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets 
N*                   (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word 
N*                   size SHOULD be configured (e.g. to 16-bits).  However, the minimum supported word 
N*                   size for CPU timestamp timers is 8-bits.
N*
N*                   See also 'cpu_core.h  FUNCTION PROTOTYPES  CPU_TS_TmrRd()  Note #2a'.
N*********************************************************************************************************
N*/
N
N                                                                /* Configure CPU timestamp features (see Note #1) :     */
N#define  CPU_CFG_TS_32_EN                       DEF_ENABLED
N#define  CPU_CFG_TS_64_EN                       DEF_DISABLED
N                                                                /*   DEF_DISABLED  CPU timestamps DISABLED              */
N                                                                /*   DEF_ENABLED   CPU timestamps ENABLED               */
N
N                                                                /* Configure CPU timestamp timer word size ...          */
N                                                                /* ... (see Note #2) :                                  */
N#define  CPU_CFG_TS_TMR_SIZE                    CPU_WORD_SIZE_32
N
N
N/*
N*********************************************************************************************************
N*                        CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION
N*
N* Note(s) : (1) (a) Configure CPU_CFG_INT_DIS_MEAS_EN to enable/disable measuring CPU's interrupts 
N*                   disabled time :
N*
N*                   (a)  Enabled,       if CPU_CFG_INT_DIS_MEAS_EN      #define'd in 'cpu_cfg.h'
N*
N*                   (b) Disabled,       if CPU_CFG_INT_DIS_MEAS_EN  NOT #define'd in 'cpu_cfg.h'
N*
N*                   See also 'cpu_core.h  FUNCTION PROTOTYPES  Note #1'.
N*
N*               (b) Configure CPU_CFG_INT_DIS_MEAS_OVRHD_NBR with the number of times to measure & 
N*                   average the interrupts disabled time measurements overhead.
N*
N*                   Recommend a single (1) overhead time measurement, even for instruction-cache-enabled 
N*                   CPUs, since critical sections are NOT typically called within instruction-cached loops.
N*                   Thus a single non-cached/non-averaged time measurement is a more realistic overhead 
N*                   for the majority of non-cached interrupts disabled time measurements.
N*
N*                   See also 'cpu_core.c  CPU_IntDisMeasInit()  Note #3a'.
N*********************************************************************************************************
N*/
N
N#if 0                                                           /* Configure CPU interrupts disabled time ...           */
S#define  CPU_CFG_INT_DIS_MEAS_EN                                /* ... measurements feature (see Note #1a).             */
N#endif
N
N                                                                /* Configure number of interrupts disabled overhead ... */
N#define  CPU_CFG_INT_DIS_MEAS_OVRHD_NBR                    1u   /* ... time measurements (see Note #1b).                */
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                    CPU COUNT ZEROS CONFIGURATION
N*
N* Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT  to define count leading  zeros bits 
N*                   function(s) in :
N*
N*                   (1) 'cpu_a.asm',  if CPU_CFG_LEAD_ZEROS_ASM_PRESENT       #define'd in 'cpu.h'/
N*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
N*
N*                   (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT   NOT #define'd in 'cpu.h'/
N*                                         'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
N*
N*               (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits 
N*                   function(s) in :
N*
N*                   (1) 'cpu_a.asm',  if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT      #define'd in 'cpu.h'/
N*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
N*
N*                   (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT  NOT #define'd in 'cpu.h'/
N*                                         'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
N*********************************************************************************************************
N*/
N
N#if 1                                                           /* Configure CPU count leading  zeros bits ...          */
N#define  CPU_CFG_LEAD_ZEROS_ASM_PRESENT                         /* ... assembly-version (see Note #1a).                 */
N#endif
N
N#if 0                                                           /* Configure CPU count trailing zeros bits ...          */
S#define  CPU_CFG_TRAIL_ZEROS_ASM_PRESENT                        /* ... assembly-version (see Note #1b).                 */
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                             MODULE END
N*********************************************************************************************************
N*/
N
N#endif                                                          /* End of CPU cfg module include.                       */
N
L 89 "..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView\cpu.h" 2
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                    CONFIGURE STANDARD DATA TYPES
N*
N* Note(s) : (1) Configure standard data types according to CPU-/compiler-specifications.
N*
N*           (2) (a) (1) 'CPU_FNCT_VOID' data type defined to replace the commonly-used function pointer
N*                       data type of a pointer to a function which returns void & has no arguments.
N*
N*                   (2) Example function pointer usage :
N*
N*                           CPU_FNCT_VOID  FnctName;
N*
N*                           FnctName();
N*
N*               (b) (1) 'CPU_FNCT_PTR'  data type defined to replace the commonly-used function pointer
N*                       data type of a pointer to a function which returns void & has a single void
N*                       pointer argument.
N*
N*                   (2) Example function pointer usage :
N*
N*                           CPU_FNCT_PTR   FnctName;
N*                           void          *p_obj
N*
N*                           FnctName(p_obj);
N*********************************************************************************************************
N*/
N
Ntypedef            void        CPU_VOID;
Ntypedef            char        CPU_CHAR;                        /*  8-bit character                                     */
Ntypedef  unsigned  char        CPU_BOOLEAN;                     /*  8-bit boolean or logical                            */
Ntypedef  unsigned  char        CPU_INT08U;                      /*  8-bit unsigned integer                              */
Ntypedef    signed  char        CPU_INT08S;                      /*  8-bit   signed integer                              */
Ntypedef  unsigned  short       CPU_INT16U;                      /* 16-bit unsigned integer                              */
Ntypedef    signed  short       CPU_INT16S;                      /* 16-bit   signed integer                              */
Ntypedef  unsigned  int         CPU_INT32U;                      /* 32-bit unsigned integer                              */
Ntypedef    signed  int         CPU_INT32S;                      /* 32-bit   signed integer                              */
Ntypedef  unsigned  long  long  CPU_INT64U;                      /* 64-bit unsigned integer                              */
Ntypedef    signed  long  long  CPU_INT64S;                      /* 64-bit   signed integer                              */
N
Ntypedef            float       CPU_FP32;                        /* 32-bit floating point                                */
Ntypedef            double      CPU_FP64;                        /* 64-bit floating point                                */
N
N
Ntypedef  volatile  CPU_INT08U  CPU_REG08;                       /*  8-bit register                                      */
Ntypedef  volatile  CPU_INT16U  CPU_REG16;                       /* 16-bit register                                      */
Ntypedef  volatile  CPU_INT32U  CPU_REG32;                       /* 32-bit register                                      */
Ntypedef  volatile  CPU_INT64U  CPU_REG64;                       /* 64-bit register                                      */
N
N
Ntypedef            void      (*CPU_FNCT_VOID)(void);            /* See Note #2a.                                        */
Ntypedef            void      (*CPU_FNCT_PTR )(void *p_obj);     /* See Note #2b.                                        */
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                       CPU WORD CONFIGURATION
N*
N* Note(s) : (1) Configure CPU_CFG_ADDR_SIZE, CPU_CFG_DATA_SIZE, & CPU_CFG_DATA_SIZE_MAX with CPU's &/or 
N*               compiler's word sizes :
N*
N*                   CPU_WORD_SIZE_08             8-bit word size
N*                   CPU_WORD_SIZE_16            16-bit word size
N*                   CPU_WORD_SIZE_32            32-bit word size
N*                   CPU_WORD_SIZE_64            64-bit word size
N*
N*           (2) Configure CPU_CFG_ENDIAN_TYPE with CPU's data-word-memory order :
N*
N*               (a) CPU_ENDIAN_TYPE_BIG         Big-   endian word order (CPU words' most  significant
N*                                                                         octet @ lowest memory address)
N*               (b) CPU_ENDIAN_TYPE_LITTLE      Little-endian word order (CPU words' least significant
N*                                                                         octet @ lowest memory address)
N*********************************************************************************************************
N*/
N
N                                                                /* Define  CPU         word sizes (see Note #1) :       */
N#define  CPU_CFG_ADDR_SIZE              CPU_WORD_SIZE_32        /* Defines CPU address word size  (in octets).          */
N#define  CPU_CFG_DATA_SIZE              CPU_WORD_SIZE_32        /* Defines CPU data    word size  (in octets).          */
N#define  CPU_CFG_DATA_SIZE_MAX          CPU_WORD_SIZE_64        /* Defines CPU maximum word size  (in octets).          */
N
N#define  CPU_CFG_ENDIAN_TYPE            CPU_ENDIAN_TYPE_LITTLE  /* Defines CPU data    word-memory order (see Note #2). */
N
N
N/*
N*********************************************************************************************************
N*                                 CONFIGURE CPU ADDRESS & DATA TYPES
N*********************************************************************************************************
N*/
N
N                                                                /* CPU address type based on address bus size.          */
N#if     (CPU_CFG_ADDR_SIZE == CPU_WORD_SIZE_32)
X#if     (4 == 4)
Ntypedef  CPU_INT32U  CPU_ADDR;
N#elif   (CPU_CFG_ADDR_SIZE == CPU_WORD_SIZE_16)
Stypedef  CPU_INT16U  CPU_ADDR;
S#else
Stypedef  CPU_INT08U  CPU_ADDR;
N#endif
N
N                                                                /* CPU data    type based on data    bus size.          */
N#if     (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_32)
X#if     (4 == 4)
Ntypedef  CPU_INT32U  CPU_DATA;
N#elif   (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_16)
Stypedef  CPU_INT16U  CPU_DATA;
S#else
Stypedef  CPU_INT08U  CPU_DATA;
N#endif
N
N
Ntypedef  CPU_DATA    CPU_ALIGN;                                 /* Defines CPU data-word-alignment size.                */
Ntypedef  CPU_ADDR    CPU_SIZE_T;                                /* Defines CPU standard 'size_t'   size.                */
N
N
N/*
N*********************************************************************************************************
N*                                       CPU STACK CONFIGURATION
N*
N* Note(s) : (1) Configure CPU_CFG_STK_GROWTH in 'cpu.h' with CPU's stack growth order :
N*
N*               (a) CPU_STK_GROWTH_LO_TO_HI     CPU stack pointer increments to the next higher  stack
N*                                                   memory address after data is pushed onto the stack
N*               (b) CPU_STK_GROWTH_HI_TO_LO     CPU stack pointer decrements to the next lower   stack
N*                                                   memory address after data is pushed onto the stack
N*********************************************************************************************************
N*/
N
N#define  CPU_CFG_STK_GROWTH     CPU_STK_GROWTH_HI_TO_LO         /* Defines CPU stack growth order (see Note #1).        */
N
Ntypedef  CPU_INT32U             CPU_STK;                        /* Defines CPU stack word size (in octets).             */
Ntypedef  CPU_ADDR               CPU_STK_SIZE;                   /* Defines CPU stack      size (in number of CPU_STKs). */
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                   CRITICAL SECTION CONFIGURATION
N*
N* Note(s) : (1) Configure CPU_CFG_CRITICAL_METHOD with CPU's/compiler's critical section method :
N*
N*                                                       Enter/Exit critical sections by ...
N*
N*                   CPU_CRITICAL_METHOD_INT_DIS_EN      Disable/Enable interrupts
N*                   CPU_CRITICAL_METHOD_STATUS_STK      Push/Pop       interrupt status onto stack
N*                   CPU_CRITICAL_METHOD_STATUS_LOCAL    Save/Restore   interrupt status to local variable
N*
N*               (a) CPU_CRITICAL_METHOD_INT_DIS_EN  is NOT a preferred method since it does NOT support
N*                   multiple levels of interrupts.  However, with some CPUs/compilers, this is the only
N*                   available method.
N*
N*               (b) CPU_CRITICAL_METHOD_STATUS_STK    is one preferred method since it supports multiple
N*                   levels of interrupts.  However, this method assumes that the compiler provides C-level
N*                   &/or assembly-level functionality for the following :
N*
N*                     ENTER CRITICAL SECTION :
N*                       (1) Push/save   interrupt status onto a local stack
N*                       (2) Disable     interrupts
N*
N*                     EXIT  CRITICAL SECTION :
N*                       (3) Pop/restore interrupt status from a local stack
N*
N*               (c) CPU_CRITICAL_METHOD_STATUS_LOCAL  is one preferred method since it supports multiple
N*                   levels of interrupts.  However, this method assumes that the compiler provides C-level
N*                   &/or assembly-level functionality for the following :
N*
N*                     ENTER CRITICAL SECTION :
N*                       (1) Save    interrupt status into a local variable
N*                       (2) Disable interrupts
N*
N*                     EXIT  CRITICAL SECTION :
N*                       (3) Restore interrupt status from a local variable
N*
N*           (2) Critical section macro's most likely require inline assembly.  If the compiler does NOT
N*               allow inline assembly in C source files, critical section macro's MUST call an assembly
N*               subroutine defined in a 'cpu_a.asm' file located in the following software directory :
N*
N*                   \<CPU-Compiler Directory>\<cpu>\<compiler>\
N*
X
N*                       where
N*                               <CPU-Compiler Directory>    directory path for common   CPU-compiler software
N*                               <cpu>                       directory name for specific CPU
N*                               <compiler>                  directory name for specific compiler
N*
N*           (3) (a) To save/restore interrupt status, a local variable 'cpu_sr' of type 'CPU_SR' MAY need
N*                   to be declared (e.g. if 'CPU_CRITICAL_METHOD_STATUS_LOCAL' method is configured).
N*
N*                   (1) 'cpu_sr' local variable SHOULD be declared via the CPU_SR_ALLOC() macro which, if 
N*                        used, MUST be declared following ALL other local variables.
N*
N*                        Example :
N*
N*                           void  Fnct (void)
N*                           {
N*                               CPU_INT08U  val_08;
N*                               CPU_INT16U  val_16;
N*                               CPU_INT32U  val_32;
N*                               CPU_SR_ALLOC();         MUST be declared after ALL other local variables
N*                                   :
N*                                   :
N*                           }
N*
N*               (b) Configure 'CPU_SR' data type with the appropriate-sized CPU data type large enough to
N*                   completely store the CPU's/compiler's status word.
N*********************************************************************************************************
N*/
N/*$PAGE*/
N                                                                /* Configure CPU critical method      (see Note #1) :   */
N#define  CPU_CFG_CRITICAL_METHOD    CPU_CRITICAL_METHOD_STATUS_LOCAL
N
Ntypedef  CPU_INT32U                 CPU_SR;                     /* Defines   CPU status register size (see Note #3b).   */
N
N                                                                /* Allocates CPU status register word (see Note #3a).   */
N#if     (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
X#if     (3u == 3u)
N#define  CPU_SR_ALLOC()             CPU_SR  cpu_sr = (CPU_SR)0
N#else
S#define  CPU_SR_ALLOC()
N#endif
N
N
N
N#define  CPU_INT_DIS()         do { cpu_sr = CPU_SR_Save(); } while (0) /* Save    CPU status word & disable interrupts.*/
N#define  CPU_INT_EN()          do { CPU_SR_Restore(cpu_sr); } while (0) /* Restore CPU status word.                     */
N
N
N#ifdef   CPU_CFG_INT_DIS_MEAS_EN
S                                                                        /* Disable interrupts, ...                      */
S                                                                        /* & start interrupts disabled time measurement.*/
S#define  CPU_CRITICAL_ENTER()  do { CPU_INT_DIS();         \
S                                    CPU_IntDisMeasStart(); }  while (0)
X#define  CPU_CRITICAL_ENTER()  do { CPU_INT_DIS();                                             CPU_IntDisMeasStart(); }  while (0)
S                                                                        /* Stop & measure   interrupts disabled time,   */
S                                                                        /* ...  & re-enable interrupts.                 */
S#define  CPU_CRITICAL_EXIT()   do { CPU_IntDisMeasStop();  \
S                                    CPU_INT_EN();          }  while (0)
X#define  CPU_CRITICAL_EXIT()   do { CPU_IntDisMeasStop();                                      CPU_INT_EN();          }  while (0)
S
N#else
N
N#define  CPU_CRITICAL_ENTER()  do { CPU_INT_DIS(); } while (0)          /* Disable   interrupts.                        */
N#define  CPU_CRITICAL_EXIT()   do { CPU_INT_EN();  } while (0)          /* Re-enable interrupts.                        */
N
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                    CPU COUNT ZEROS CONFIGURATION
N*
N* Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT  to define count leading  zeros bits 
N*                   function(s) in :
N*
N*                   (1) 'cpu_a.asm',  if CPU_CFG_LEAD_ZEROS_ASM_PRESENT       #define'd in 'cpu.h'/
N*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
N*
N*                   (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT   NOT #define'd in 'cpu.h'/
N*                                         'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
N*
N*               (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits 
N*                   function(s) in :
N*
N*                   (1) 'cpu_a.asm',  if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT      #define'd in 'cpu.h'/
N*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
N*
N*                   (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT  NOT #define'd in 'cpu.h'/
N*                                         'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
N*********************************************************************************************************
N*/
N
N                                                                /* Configure CPU count leading  zeros bits ...          */
N#define  CPU_CFG_LEAD_ZEROS_ASM_PRESENT                         /* ... assembly-version (see Note #1a).                 */
N
N                                                                /* Configure CPU count trailing zeros bits ...          */
N#define  CPU_CFG_TRAIL_ZEROS_ASM_PRESENT                        /* ... assembly-version (see Note #1b).                 */
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                         FUNCTION PROTOTYPES
N*********************************************************************************************************
N*/
N
Nvoid        CPU_IntDis       (void);
Nvoid        CPU_IntEn        (void);
N
Nvoid        CPU_IntSrcDis    (CPU_INT08U  pos);
Nvoid        CPU_IntSrcEn     (CPU_INT08U  pos);
Nvoid        CPU_IntSrcPendClr(CPU_INT08U  pos);
NCPU_INT16S  CPU_IntSrcPrioGet(CPU_INT08U  pos);
Nvoid        CPU_IntSrcPrioSet(CPU_INT08U  pos,
N                              CPU_INT08U  prio);
N
N
NCPU_SR      CPU_SR_Save      (void);
Nvoid        CPU_SR_Restore   (CPU_SR      cpu_sr);
N
N
Nvoid        CPU_WaitForInt   (void);
Nvoid        CPU_WaitForExcept(void);
N
N
NCPU_DATA    CPU_RevBits      (CPU_DATA    val);
N
Nvoid        CPU_BitBandClr   (CPU_ADDR    addr,
N                              CPU_INT08U  bit_nbr);
Nvoid        CPU_BitBandSet   (CPU_ADDR    addr,
N                              CPU_INT08U  bit_nbr);
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          INTERRUPT SOURCES
N*********************************************************************************************************
N*/
N
N#define  CPU_INT_STK_PTR                                   0u
N#define  CPU_INT_RESET                                     1u
N#define  CPU_INT_NMI                                       2u
N#define  CPU_INT_HFAULT                                    3u
N#define  CPU_INT_MEM                                       4u
N#define  CPU_INT_BUSFAULT                                  5u
N#define  CPU_INT_USAGEFAULT                                6u
N#define  CPU_INT_RSVD_07                                   7u
N#define  CPU_INT_RSVD_08                                   8u
N#define  CPU_INT_RSVD_09                                   9u
N#define  CPU_INT_RSVD_10                                  10u
N#define  CPU_INT_SVCALL                                   11u
N#define  CPU_INT_DBGMON                                   12u
N#define  CPU_INT_RSVD_13                                  13u
N#define  CPU_INT_PENDSV                                   14u
N#define  CPU_INT_SYSTICK                                  15u
N#define  CPU_INT_EXT0                                     16u
N
N/*
N*********************************************************************************************************
N*                                            CPU REGISTERS
N*********************************************************************************************************
N*/
N
N#define  CPU_REG_NVIC_NVIC           (*((CPU_REG32 *)(0xE000E004)))             /* Int Ctrl'er Type Reg.                */
N#define  CPU_REG_NVIC_ST_CTRL        (*((CPU_REG32 *)(0xE000E010)))             /* SysTick Ctrl & Status Reg.           */
N#define  CPU_REG_NVIC_ST_RELOAD      (*((CPU_REG32 *)(0xE000E014)))             /* SysTick Reload      Value Reg.       */
N#define  CPU_REG_NVIC_ST_CURRENT     (*((CPU_REG32 *)(0xE000E018)))             /* SysTick Current     Value Reg.       */
N#define  CPU_REG_NVIC_ST_CAL         (*((CPU_REG32 *)(0xE000E01C)))             /* SysTick Calibration Value Reg.       */
N
N#define  CPU_REG_NVIC_SETEN(n)       (*((CPU_REG32 *)(0xE000E100 + (n) * 4u)))  /* IRQ Set En Reg.                      */
N#define  CPU_REG_NVIC_CLREN(n)       (*((CPU_REG32 *)(0xE000E180 + (n) * 4u)))  /* IRQ Clr En Reg.                      */
N#define  CPU_REG_NVIC_SETPEND(n)     (*((CPU_REG32 *)(0xE000E200 + (n) * 4u)))  /* IRQ Set Pending Reg.                 */
N#define  CPU_REG_NVIC_CLRPEND(n)     (*((CPU_REG32 *)(0xE000E280 + (n) * 4u)))  /* IRQ Clr Pending Reg.                 */
N#define  CPU_REG_NVIC_ACTIVE(n)      (*((CPU_REG32 *)(0xE000E300 + (n) * 4u)))  /* IRQ Active Reg.                      */
N#define  CPU_REG_NVIC_PRIO(n)        (*((CPU_REG32 *)(0xE000E400 + (n) * 4u)))  /* IRQ Prio Reg.                        */
N
N#define  CPU_REG_NVIC_CPUID          (*((CPU_REG32 *)(0xE000ED00)))             /* CPUID Base Reg.                      */
N#define  CPU_REG_NVIC_ICSR           (*((CPU_REG32 *)(0xE000ED04)))             /* Int Ctrl State  Reg.                 */
N#define  CPU_REG_NVIC_VTOR           (*((CPU_REG32 *)(0xE000ED08)))             /* Vect Tbl Offset Reg.                 */
N#define  CPU_REG_NVIC_AIRCR          (*((CPU_REG32 *)(0xE000ED0C)))             /* App Int/Reset Ctrl Reg.              */
N#define  CPU_REG_NVIC_SCR            (*((CPU_REG32 *)(0xE000ED10)))             /* System Ctrl Reg.                     */
N#define  CPU_REG_NVIC_CCR            (*((CPU_REG32 *)(0xE000ED14)))             /* Cfg    Ctrl Reg.                     */
N#define  CPU_REG_NVIC_SHPRI1         (*((CPU_REG32 *)(0xE000ED18)))             /* System Handlers  4 to  7 Prio.       */
N#define  CPU_REG_NVIC_SHPRI2         (*((CPU_REG32 *)(0xE000ED1C)))             /* System Handlers  8 to 11 Prio.       */
N#define  CPU_REG_NVIC_SHPRI3         (*((CPU_REG32 *)(0xE000ED20)))             /* System Handlers 12 to 15 Prio.       */
N#define  CPU_REG_NVIC_SHCSR          (*((CPU_REG32 *)(0xE000ED24)))             /* System Handler Ctrl & State Reg.     */
N#define  CPU_REG_NVIC_CFSR           (*((CPU_REG32 *)(0xE000ED28)))             /* Configurable Fault Status Reg.       */
N#define  CPU_REG_NVIC_HFSR           (*((CPU_REG32 *)(0xE000ED2C)))             /* Hard  Fault Status Reg.              */
N#define  CPU_REG_NVIC_DFSR           (*((CPU_REG32 *)(0xE000ED30)))             /* Debug Fault Status Reg.              */
N#define  CPU_REG_NVIC_MMFAR          (*((CPU_REG32 *)(0xE000ED34)))             /* Mem Manage Addr Reg.                 */
N#define  CPU_REG_NVIC_BFAR           (*((CPU_REG32 *)(0xE000ED38)))             /* Bus Fault  Addr Reg.                 */
N#define  CPU_REG_NVIC_AFSR           (*((CPU_REG32 *)(0xE000ED3C)))             /* Aux Fault Status Reg.                */
N
N#define  CPU_REG_NVIC_PFR0           (*((CPU_REG32 *)(0xE000ED40)))             /* Processor Feature Reg 0.             */
N#define  CPU_REG_NVIC_PFR1           (*((CPU_REG32 *)(0xE000ED44)))             /* Processor Feature Reg 1.             */
N#define  CPU_REG_NVIC_DFR0           (*((CPU_REG32 *)(0xE000ED48)))             /* Debug     Feature Reg 0.             */
N#define  CPU_REG_NVIC_AFR0           (*((CPU_REG32 *)(0xE000ED4C)))             /* Aux       Feature Reg 0.             */
N#define  CPU_REG_NVIC_MMFR0          (*((CPU_REG32 *)(0xE000ED50)))             /* Memory Model Feature Reg 0.          */
N#define  CPU_REG_NVIC_MMFR1          (*((CPU_REG32 *)(0xE000ED54)))             /* Memory Model Feature Reg 1.          */
N#define  CPU_REG_NVIC_MMFR2          (*((CPU_REG32 *)(0xE000ED58)))             /* Memory Model Feature Reg 2.          */
N#define  CPU_REG_NVIC_MMFR3          (*((CPU_REG32 *)(0xE000ED5C)))             /* Memory Model Feature Reg 3.          */
N#define  CPU_REG_NVIC_ISAFR0         (*((CPU_REG32 *)(0xE000ED60)))             /* ISA Feature Reg 0.                   */
N#define  CPU_REG_NVIC_ISAFR1         (*((CPU_REG32 *)(0xE000ED64)))             /* ISA Feature Reg 1.                   */
N#define  CPU_REG_NVIC_ISAFR2         (*((CPU_REG32 *)(0xE000ED68)))             /* ISA Feature Reg 2.                   */
N#define  CPU_REG_NVIC_ISAFR3         (*((CPU_REG32 *)(0xE000ED6C)))             /* ISA Feature Reg 3.                   */
N#define  CPU_REG_NVIC_ISAFR4         (*((CPU_REG32 *)(0xE000ED70)))             /* ISA Feature Reg 4.                   */
N#define  CPU_REG_NVIC_SW_TRIG        (*((CPU_REG32 *)(0xE000EF00)))             /* Software Trigger Int Reg.            */
N
N#define  CPU_REG_MPU_TYPE            (*((CPU_REG32 *)(0xE000ED90)))             /* MPU Type Reg.                        */
N#define  CPU_REG_MPU_CTRL            (*((CPU_REG32 *)(0xE000ED94)))             /* MPU Ctrl Reg.                        */
N#define  CPU_REG_MPU_REG_NBR         (*((CPU_REG32 *)(0xE000ED98)))             /* MPU Region Nbr Reg.                  */
N#define  CPU_REG_MPU_REG_BASE        (*((CPU_REG32 *)(0xE000ED9C)))             /* MPU Region Base Addr Reg.            */
N#define  CPU_REG_MPU_REG_ATTR        (*((CPU_REG32 *)(0xE000EDA0)))             /* MPU Region Attrib & Size Reg.        */
N
N#define  CPU_REG_DBG_CTRL            (*((CPU_REG32 *)(0xE000EDF0)))             /* Debug Halting Ctrl & Status Reg.     */
N#define  CPU_REG_DBG_SELECT          (*((CPU_REG32 *)(0xE000EDF4)))             /* Debug Core Reg Selector Reg.         */
N#define  CPU_REG_DBG_DATA            (*((CPU_REG32 *)(0xE000EDF8)))             /* Debug Core Reg Data     Reg.         */
N#define  CPU_REG_DBG_INT             (*((CPU_REG32 *)(0xE000EDFC)))             /* Debug Except & Monitor Ctrl Reg.     */
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          CPU REGISTER BITS
N*********************************************************************************************************
N*/
N
N                                                                /* ---------- SYSTICK CTRL & STATUS REG BITS ---------- */
N#define  CPU_REG_NVIC_ST_CTRL_COUNTFLAG           0x00010000
N#define  CPU_REG_NVIC_ST_CTRL_CLKSOURCE           0x00000004
N#define  CPU_REG_NVIC_ST_CTRL_TICKINT             0x00000002
N#define  CPU_REG_NVIC_ST_CTRL_ENABLE              0x00000001
N
N
N                                                                /* -------- SYSTICK CALIBRATION VALUE REG BITS -------- */
N#define  CPU_REG_NVIC_ST_CAL_NOREF                0x80000000
N#define  CPU_REG_NVIC_ST_CAL_SKEW                 0x40000000
N
N                                                                /* -------------- INT CTRL STATE REG BITS ------------- */
N#define  CPU_REG_NVIC_ICSR_NMIPENDSET             0x80000000
N#define  CPU_REG_NVIC_ICSR_PENDSVSET              0x10000000
N#define  CPU_REG_NVIC_ICSR_PENDSVCLR              0x08000000
N#define  CPU_REG_NVIC_ICSR_PENDSTSET              0x04000000
N#define  CPU_REG_NVIC_ICSR_PENDSTCLR              0x02000000
N#define  CPU_REG_NVIC_ICSR_ISRPREEMPT             0x00800000
N#define  CPU_REG_NVIC_ICSR_ISRPENDING             0x00400000
N#define  CPU_REG_NVIC_ICSR_RETTOBASE              0x00000800
N
N                                                                /* ------------- VECT TBL OFFSET REG BITS ------------- */
N#define  CPU_REG_NVIC_VTOR_TBLBASE                0x20000000
N
N                                                                /* ------------ APP INT/RESET CTRL REG BITS ----------- */
N#define  CPU_REG_NVIC_AIRCR_ENDIANNESS            0x00008000
N#define  CPU_REG_NVIC_AIRCR_SYSRESETREQ           0x00000004
N#define  CPU_REG_NVIC_AIRCR_VECTCLRACTIVE         0x00000002
N#define  CPU_REG_NVIC_AIRCR_VECTRESET             0x00000001
N
N                                                                /* --------------- SYSTEM CTRL REG BITS --------------- */
N#define  CPU_REG_NVIC_SCR_SEVONPEND               0x00000010
N#define  CPU_REG_NVIC_SCR_SLEEPDEEP               0x00000004
N#define  CPU_REG_NVIC_SCR_SLEEPONEXIT             0x00000002
N
N                                                                /* ----------------- CFG CTRL REG BITS ---------------- */
N#define  CPU_REG_NVIC_CCR_STKALIGN                0x00000200
N#define  CPU_REG_NVIC_CCR_BFHFNMIGN               0x00000100
N#define  CPU_REG_NVIC_CCR_DIV_0_TRP               0x00000010
N#define  CPU_REG_NVIC_CCR_UNALIGN_TRP             0x00000008
N#define  CPU_REG_NVIC_CCR_USERSETMPEND            0x00000002
N#define  CPU_REG_NVIC_CCR_NONBASETHRDENA          0x00000001
N
N                                                                /* ------- SYSTEM HANDLER CTRL & STATE REG BITS ------- */
N#define  CPU_REG_NVIC_SHCSR_USGFAULTENA           0x00040000
N#define  CPU_REG_NVIC_SHCSR_BUSFAULTENA           0x00020000
N#define  CPU_REG_NVIC_SHCSR_MEMFAULTENA           0x00010000
N#define  CPU_REG_NVIC_SHCSR_SVCALLPENDED          0x00008000
N#define  CPU_REG_NVIC_SHCSR_BUSFAULTPENDED        0x00004000
N#define  CPU_REG_NVIC_SHCSR_MEMFAULTPENDED        0x00002000
N#define  CPU_REG_NVIC_SHCSR_USGFAULTPENDED        0x00001000
N#define  CPU_REG_NVIC_SHCSR_SYSTICKACT            0x00000800
N#define  CPU_REG_NVIC_SHCSR_PENDSVACT             0x00000400
N#define  CPU_REG_NVIC_SHCSR_MONITORACT            0x00000100
N#define  CPU_REG_NVIC_SHCSR_SVCALLACT             0x00000080
N#define  CPU_REG_NVIC_SHCSR_USGFAULTACT           0x00000008
N#define  CPU_REG_NVIC_SHCSR_BUSFAULTACT           0x00000002
N#define  CPU_REG_NVIC_SHCSR_MEMFAULTACT           0x00000001
N
N                                                                /* -------- CONFIGURABLE FAULT STATUS REG BITS -------- */
N#define  CPU_REG_NVIC_CFSR_DIVBYZERO              0x02000000
N#define  CPU_REG_NVIC_CFSR_UNALIGNED              0x01000000
N#define  CPU_REG_NVIC_CFSR_NOCP                   0x00080000
N#define  CPU_REG_NVIC_CFSR_INVPC                  0x00040000
N#define  CPU_REG_NVIC_CFSR_INVSTATE               0x00020000
N#define  CPU_REG_NVIC_CFSR_UNDEFINSTR             0x00010000
N#define  CPU_REG_NVIC_CFSR_BFARVALID              0x00008000
N#define  CPU_REG_NVIC_CFSR_STKERR                 0x00001000
N#define  CPU_REG_NVIC_CFSR_UNSTKERR               0x00000800
N#define  CPU_REG_NVIC_CFSR_IMPRECISERR            0x00000400
N#define  CPU_REG_NVIC_CFSR_PRECISERR              0x00000200
N#define  CPU_REG_NVIC_CFSR_IBUSERR                0x00000100
N#define  CPU_REG_NVIC_CFSR_MMARVALID              0x00000080
N#define  CPU_REG_NVIC_CFSR_MSTKERR                0x00000010
N#define  CPU_REG_NVIC_CFSR_MUNSTKERR              0x00000008
N#define  CPU_REG_NVIC_CFSR_DACCVIOL               0x00000002
N#define  CPU_REG_NVIC_CFSR_IACCVIOL               0x00000001
N
N                                                                /* ------------ HARD FAULT STATUS REG BITS ------------ */
N#define  CPU_REG_NVIC_HFSR_DEBUGEVT               0x80000000
N#define  CPU_REG_NVIC_HFSR_FORCED                 0x40000000
N#define  CPU_REG_NVIC_HFSR_VECTTBL                0x00000002
N
N                                                                /* ------------ DEBUG FAULT STATUS REG BITS ----------- */
N#define  CPU_REG_NVIC_DFSR_EXTERNAL               0x00000010
N#define  CPU_REG_NVIC_DFSR_VCATCH                 0x00000008
N#define  CPU_REG_NVIC_DFSR_DWTTRAP                0x00000004
N#define  CPU_REG_NVIC_DFSR_BKPT                   0x00000002
N#define  CPU_REG_NVIC_DFSR_HALTED                 0x00000001
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          CPU REGISTER MASK
N*********************************************************************************************************
N*/
N
N#define  CPU_MSK_NVIC_ICSR_VECT_ACTIVE            0x000001FF
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                        CONFIGURATION ERRORS
N*********************************************************************************************************
N*/
N
N#ifndef  CPU_CFG_ADDR_SIZE
S#error  "CPU_CFG_ADDR_SIZE              not #define'd in 'cpu.h'               "
S#error  "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_64  64-bit alignment]"
S
S#elif  ((CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_08) && \
S        (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_16) && \
S        (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_32) && \
S        (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_64))
X#elif  ((4 != 1) &&         (4 != 2) &&         (4 != 4) &&         (4 != 8))
S#error  "CPU_CFG_ADDR_SIZE        illegally #define'd in 'cpu.h'               "
S#error  "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_64  64-bit alignment]"
N#endif
N
N
N#ifndef  CPU_CFG_DATA_SIZE
S#error  "CPU_CFG_DATA_SIZE              not #define'd in 'cpu.h'               "
S#error  "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_64  64-bit alignment]"
S
S#elif  ((CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_08) && \
S        (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_16) && \
S        (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_32) && \
S        (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_64))
X#elif  ((4 != 1) &&         (4 != 2) &&         (4 != 4) &&         (4 != 8))
S#error  "CPU_CFG_DATA_SIZE        illegally #define'd in 'cpu.h'               "
S#error  "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_64  64-bit alignment]"
N#endif
N
N
N#ifndef  CPU_CFG_DATA_SIZE_MAX
S#error  "CPU_CFG_DATA_SIZE_MAX          not #define'd in 'cpu.h'               "
S#error  "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_64  64-bit alignment]"
S
S#elif  ((CPU_CFG_DATA_SIZE_MAX != CPU_WORD_SIZE_08) && \
S        (CPU_CFG_DATA_SIZE_MAX != CPU_WORD_SIZE_16) && \
S        (CPU_CFG_DATA_SIZE_MAX != CPU_WORD_SIZE_32) && \
S        (CPU_CFG_DATA_SIZE_MAX != CPU_WORD_SIZE_64))
X#elif  ((8 != 1) &&         (8 != 2) &&         (8 != 4) &&         (8 != 8))
S#error  "CPU_CFG_DATA_SIZE_MAX    illegally #define'd in 'cpu.h'               "
S#error  "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"
S#error  "                         [     ||  CPU_WORD_SIZE_64  64-bit alignment]"
N#endif
N
N
N
N#if     (CPU_CFG_DATA_SIZE_MAX < CPU_CFG_DATA_SIZE)
X#if     (8 < 4)
S#error  "CPU_CFG_DATA_SIZE_MAX    illegally #define'd in 'cpu.h' "
S#error  "                         [MUST be  >= CPU_CFG_DATA_SIZE]"
N#endif
N
N
N
N
N/*$PAGE*/
N#ifndef  CPU_CFG_ENDIAN_TYPE
S#error  "CPU_CFG_ENDIAN_TYPE            not #define'd in 'cpu.h'   "
S#error  "                         [MUST be  CPU_ENDIAN_TYPE_BIG   ]"
S#error  "                         [     ||  CPU_ENDIAN_TYPE_LITTLE]"
S
S#elif  ((CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_BIG   ) && \
S        (CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_LITTLE))
X#elif  ((2u != 1u   ) &&         (2u != 2u))
S#error  "CPU_CFG_ENDIAN_TYPE      illegally #define'd in 'cpu.h'   "
S#error  "                         [MUST be  CPU_ENDIAN_TYPE_BIG   ]"
S#error  "                         [     ||  CPU_ENDIAN_TYPE_LITTLE]"
N#endif
N
N
N
N
N#ifndef  CPU_CFG_STK_GROWTH
S#error  "CPU_CFG_STK_GROWTH             not #define'd in 'cpu.h'    "
S#error  "                         [MUST be  CPU_STK_GROWTH_LO_TO_HI]"
S#error  "                         [     ||  CPU_STK_GROWTH_HI_TO_LO]"
S
S#elif  ((CPU_CFG_STK_GROWTH != CPU_STK_GROWTH_LO_TO_HI) && \
S        (CPU_CFG_STK_GROWTH != CPU_STK_GROWTH_HI_TO_LO))
X#elif  ((2u != 1u) &&         (2u != 2u))
S#error  "CPU_CFG_STK_GROWTH       illegally #define'd in 'cpu.h'    "
S#error  "                         [MUST be  CPU_STK_GROWTH_LO_TO_HI]"
S#error  "                         [     ||  CPU_STK_GROWTH_HI_TO_LO]"
N#endif
N
N
N
N
N#ifndef  CPU_CFG_CRITICAL_METHOD
S#error  "CPU_CFG_CRITICAL_METHOD        not #define'd in 'cpu.h'             "
S#error  "                         [MUST be  CPU_CRITICAL_METHOD_INT_DIS_EN  ]"
S#error  "                         [     ||  CPU_CRITICAL_METHOD_STATUS_STK  ]"
S#error  "                         [     ||  CPU_CRITICAL_METHOD_STATUS_LOCAL]"
S
S#elif  ((CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_INT_DIS_EN  ) && \
S        (CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_STK  ) && \
S        (CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_LOCAL))
X#elif  ((3u != 1u  ) &&         (3u != 2u  ) &&         (3u != 3u))
S#error  "CPU_CFG_CRITICAL_METHOD  illegally #define'd in 'cpu.h'             "
S#error  "                         [MUST be  CPU_CRITICAL_METHOD_INT_DIS_EN  ]"
S#error  "                         [     ||  CPU_CRITICAL_METHOD_STATUS_STK  ]"
S#error  "                         [     ||  CPU_CRITICAL_METHOD_STATUS_LOCAL]"
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                             MODULE END
N*
N* Note(s) : (1) See 'cpu.h  MODULE'.
N*********************************************************************************************************
N*/
N
N#endif                                                          /* End of CPU module include.                           */
N
L 61 "..\..\uCOS-III\uCOS-III\Source\os.h" 2
N#include <cpu_core.h>
L 1 "..\..\uCOS-III\uC-CPU\cpu_core.h" 1
N/*
N*********************************************************************************************************
N*                                                uC/CPU
N*                                    CPU CONFIGURATION & PORT LAYER
N*
N*                          (c) Copyright 2004-2011; Micrium, Inc.; Weston, FL
N*
N*               All rights reserved.  Protected by international copyright laws.
N*
N*               uC/CPU is provided in source form to registered licensees ONLY.  It is 
N*               illegal to distribute this source code to any third party unless you receive 
N*               written permission by an authorized Micrium representative.  Knowledge of 
N*               the source code may NOT be used to develop a similar product.
N*
N*               Please help us continue to provide the Embedded community with the finest 
N*               software available.  Your honesty is greatly appreciated.
N*
N*               You can contact us at www.micrium.com.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*
N*                                           CORE CPU MODULE
N*
N* Filename      : cpu_core.h
N* Version       : V1.29.01
N* Programmer(s) : SR
N*                 ITJ
N*********************************************************************************************************
N* Note(s)       : (1) Assumes the following versions (or more recent) of software modules are included in 
N*                     the project build :
N*
N*                     (a) uC/LIB V1.35.00
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                               MODULE
N*
N* Note(s) : (1) This core CPU header file is protected from multiple pre-processor inclusion through use of 
N*               the  core CPU module present pre-processor macro definition.
N*********************************************************************************************************
N*/
N
N#ifndef  CPU_CORE_MODULE_PRESENT                                /* See Note #1.                                         */
N#define  CPU_CORE_MODULE_PRESENT
N
N
N/*
N*********************************************************************************************************
N*                                               EXTERNS
N*********************************************************************************************************
N*/
N
N#ifdef   CPU_CORE_MODULE
S#define  CPU_CORE_EXT
N#else
N#define  CPU_CORE_EXT  extern
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                            INCLUDE FILES
N*
N* Note(s) : (1) CPU-configuration software files are located in the following directories :
N*
N*               (a) \<Your Product Application>\cpu_cfg.h
N*
N*               (b) (1) \<CPU-Compiler Directory>\cpu_*.*
N*                   (2) \<CPU-Compiler Directory>\<cpu>\<compiler>\cpu*.*
N*
N*                       where
N*                               <Your Product Application>      directory path for Your Product's Application
N*                               <CPU-Compiler Directory>        directory path for common CPU-compiler software
N*                               <cpu>                           directory name for specific processor (CPU)
N*                               <compiler>                      directory name for specific compiler
N*
N*           (2) NO compiler-supplied standard library functions SHOULD be used.
N*
N*               (a) Standard library functions are implemented in the custom library module(s) :
N*
N*                       \<Custom Library Directory>\lib_*.*
N*
N*                           where
N*                                   <Custom Library Directory>      directory path for custom library software
N*
N*           (3) Compiler MUST be configured to include as additional include path directories :
N*
N*               (a) '\<Your Product Application>\' directory                            See Note #1a
N*
N*               (b) (1) '\<CPU-Compiler Directory>\'                  directory         See Note #1b1
N*                   (2) '\<CPU-Compiler Directory>\<cpu>\<compiler>\' directory         See Note #1b2
N*
N*               (c) '\<Custom Library Directory>\' directory                            See Note #2a
N*********************************************************************************************************
N*/
N
N#include  <cpu.h>
N#include  <lib_def.h>
L 1 "..\..\uCOS-III\uC-LIB\lib_def.h" 1
N/*
N*********************************************************************************************************
N*                                                uC/LIB
N*                                        CUSTOM LIBRARY MODULES
N*
N*                          (c) Copyright 2004-2012; Micrium, Inc.; Weston, FL
N*
N*               All rights reserved.  Protected by international copyright laws.
N*
N*               uC/LIB is provided in source form to registered licensees ONLY.  It is 
N*               illegal to distribute this source code to any third party unless you receive 
N*               written permission by an authorized Micrium representative.  Knowledge of 
N*               the source code may NOT be used to develop a similar product.
N*
N*               Please help us continue to provide the Embedded community with the finest 
N*               software available.  Your honesty is greatly appreciated.
N*
N*               You can contact us at www.micrium.com.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*
N*                                     CORE CUSTOM LIBRARY MODULE
N*
N* Filename      : lib_def.h
N* Version       : V1.37.01
N* Programmer(s) : ITJ
N*                 FBJ
N*********************************************************************************************************
N* Note(s)       : (1) Assumes the following versions (or more recent) of software modules are included in 
N*                     the project build :
N*
N*                     (a) uC/CPU V1.29.00
N*
N*
N*                 (2) NO compiler-supplied standard library functions are used in library or product software.
N*
N*                     (a) ALL standard library functions are implemented in the custom library modules :
N*
N*                         (1) \<Custom Library Directory>\lib_*.*
N*
N*                         (2) \<Custom Library Directory>\Ports\<cpu>\<compiler>\lib*_a.*
N*
N*                               where
N*                                       <Custom Library Directory>      directory path for custom library software
N*                                       <cpu>                           directory name for specific processor (CPU)
N*                                       <compiler>                      directory name for specific compiler
N*
N*                     (b) Product-specific library functions are implemented in individual products.
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                               MODULE
N*
N* Note(s) : (1) This library definition header file is protected from multiple pre-processor inclusion 
N*               through use of the library definition module present pre-processor macro definition.
N*********************************************************************************************************
N*/
N
N#ifndef  LIB_DEF_MODULE_PRESENT
N#define  LIB_DEF_MODULE_PRESENT
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                CUSTOM LIBRARY MODULE VERSION NUMBER
N*
N* Note(s) : (1) (a) The custom library module software version is denoted as follows :
N*
N*                       Vx.yy.zz
N*
N*                           where
N*                                   V               denotes 'Version' label
N*                                   x               denotes     major software version revision number
N*                                   yy              denotes     minor software version revision number
N*                                   zz              denotes sub-minor software version revision number
N*
N*               (b) The software version label #define is formatted as follows :
N*
N*                       ver = x.yyzz * 100 * 100
N*
N*                           where
N*                                   ver             denotes software version number scaled as an integer value
N*                                   x.yyzz          denotes software version number, where the unscaled integer 
N*                                                       portion denotes the major version number & the unscaled 
N*                                                       fractional portion denotes the (concatenated) minor 
N*                                                       version numbers
N*********************************************************************************************************
N*/
N
N#define  LIB_VERSION                                   13700u   /* See Note #1.                                         */
N
N
N/*
N*********************************************************************************************************
N*                                            INCLUDE FILES
N*
N* Note(s) : (1) The custom library software files are located in the following directories :
N*
N*               (a) \<Custom Library Directory>\lib_*.*
N*
N*                       where
N*                               <Custom Library Directory>      directory path for custom library software
N*
N*           (2) CPU-configuration  software files are located in the following directories :
N*
N*               (a) \<CPU-Compiler Directory>\cpu_*.*
N*               (b) \<CPU-Compiler Directory>\<cpu>\<compiler>\cpu*.*
N*
N*                       where
N*                               <CPU-Compiler Directory>        directory path for common CPU-compiler software
N*                               <cpu>                           directory name for specific processor (CPU)
N*                               <compiler>                      directory name for specific compiler
N*
N*           (3) Compiler MUST be configured to include as additional include path directories :
N*
N*               (a) '\<Custom Library Directory>\' directory                            See Note #1a
N*
N*               (b) (1) '\<CPU-Compiler Directory>\'                  directory         See Note #2a
N*                   (2) '\<CPU-Compiler Directory>\<cpu>\<compiler>\' directory         See Note #2b
N*********************************************************************************************************
N*/
N
N#include  <cpu_def.h>
N#include  <cpu.h>
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          STANDARD DEFINES
N*********************************************************************************************************
N*/
N
N#define  DEF_NULL                                 ((void *)0)
N
N
N                                                                /* ----------------- BOOLEAN DEFINES ------------------ */
N#define  DEF_FALSE                                         0u
N#define  DEF_TRUE                                          1u
N
N#define  DEF_NO                                            0u
N#define  DEF_YES                                           1u
N
N#define  DEF_DISABLED                                      0u
N#define  DEF_ENABLED                                       1u
N
N#define  DEF_INACTIVE                                      0u
N#define  DEF_ACTIVE                                        1u
N
N#define  DEF_INVALID                                       0u
N#define  DEF_VALID                                         1u
N
N#define  DEF_OFF                                           0u
N#define  DEF_ON                                            1u
N
N#define  DEF_CLR                                           0u
N#define  DEF_SET                                           1u
N
N#define  DEF_FAIL                                          0u
N#define  DEF_OK                                            1u
N
N
N                                                                /* ------------------- BIT DEFINES -------------------- */
N#define  DEF_BIT_NONE                                   0x00u
N
N#define  DEF_BIT_00                                     0x01u
N#define  DEF_BIT_01                                     0x02u
N#define  DEF_BIT_02                                     0x04u
N#define  DEF_BIT_03                                     0x08u
N#define  DEF_BIT_04                                     0x10u
N#define  DEF_BIT_05                                     0x20u
N#define  DEF_BIT_06                                     0x40u
N#define  DEF_BIT_07                                     0x80u
N
N#define  DEF_BIT_08                                   0x0100u
N#define  DEF_BIT_09                                   0x0200u
N#define  DEF_BIT_10                                   0x0400u
N#define  DEF_BIT_11                                   0x0800u
N#define  DEF_BIT_12                                   0x1000u
N#define  DEF_BIT_13                                   0x2000u
N#define  DEF_BIT_14                                   0x4000u
N#define  DEF_BIT_15                                   0x8000u
N
N#define  DEF_BIT_16                               0x00010000u
N#define  DEF_BIT_17                               0x00020000u
N#define  DEF_BIT_18                               0x00040000u
N#define  DEF_BIT_19                               0x00080000u
N#define  DEF_BIT_20                               0x00100000u
N#define  DEF_BIT_21                               0x00200000u
N#define  DEF_BIT_22                               0x00400000u
N#define  DEF_BIT_23                               0x00800000u
N
N#define  DEF_BIT_24                               0x01000000u
N#define  DEF_BIT_25                               0x02000000u
N#define  DEF_BIT_26                               0x04000000u
N#define  DEF_BIT_27                               0x08000000u
N#define  DEF_BIT_28                               0x10000000u
N#define  DEF_BIT_29                               0x20000000u
N#define  DEF_BIT_30                               0x40000000u
N#define  DEF_BIT_31                               0x80000000u
N/*$PAGE*/
N#define  DEF_BIT_32                       0x0000000100000000u
N#define  DEF_BIT_33                       0x0000000200000000u
N#define  DEF_BIT_34                       0x0000000400000000u
N#define  DEF_BIT_35                       0x0000000800000000u
N#define  DEF_BIT_36                       0x0000001000000000u
N#define  DEF_BIT_37                       0x0000002000000000u
N#define  DEF_BIT_38                       0x0000004000000000u
N#define  DEF_BIT_39                       0x0000008000000000u
N
N#define  DEF_BIT_40                       0x0000010000000000u
N#define  DEF_BIT_41                       0x0000020000000000u
N#define  DEF_BIT_42                       0x0000040000000000u
N#define  DEF_BIT_43                       0x0000080000000000u
N#define  DEF_BIT_44                       0x0000100000000000u
N#define  DEF_BIT_45                       0x0000200000000000u
N#define  DEF_BIT_46                       0x0000400000000000u
N#define  DEF_BIT_47                       0x0000800000000000u
N
N#define  DEF_BIT_48                       0x0001000000000000u
N#define  DEF_BIT_49                       0x0002000000000000u
N#define  DEF_BIT_50                       0x0004000000000000u
N#define  DEF_BIT_51                       0x0008000000000000u
N#define  DEF_BIT_52                       0x0010000000000000u
N#define  DEF_BIT_53                       0x0020000000000000u
N#define  DEF_BIT_54                       0x0040000000000000u
N#define  DEF_BIT_55                       0x0080000000000000u
N
N#define  DEF_BIT_56                       0x0100000000000000u
N#define  DEF_BIT_57                       0x0200000000000000u
N#define  DEF_BIT_58                       0x0400000000000000u
N#define  DEF_BIT_59                       0x0800000000000000u
N#define  DEF_BIT_60                       0x1000000000000000u
N#define  DEF_BIT_61                       0x2000000000000000u
N#define  DEF_BIT_62                       0x4000000000000000u
N#define  DEF_BIT_63                       0x8000000000000000u
N
N
N                                                                /* ------------------ ALIGN DEFINES ------------------- */
N#define  DEF_ALIGN_MAX_NBR_OCTETS                       4096u
N
N
N                                                                /* ------------------ OCTET DEFINES ------------------- */
N#define  DEF_OCTET_NBR_BITS                                8u
N#define  DEF_OCTET_MASK                                 0xFFu
N
N#define  DEF_OCTET_TO_BIT_NBR_BITS                         3u
N#define  DEF_OCTET_TO_BIT_SHIFT                          DEF_OCTET_TO_BIT_NBR_BITS
N#define  DEF_OCTET_TO_BIT_MASK                          0x07u
N
N
N#define  DEF_NIBBLE_NBR_BITS                               4u
N#define  DEF_NIBBLE_MASK                                0x0Fu
N
N
N                                                                /* --------------- NUMBER BASE DEFINES ---------------- */
N#define  DEF_NBR_BASE_BIN                                  2u
N#define  DEF_NBR_BASE_OCT                                  8u
N#define  DEF_NBR_BASE_DEC                                 10u
N#define  DEF_NBR_BASE_HEX                                 16u
N
N
N/*$PAGE*/
N                                                                /* ----------------- INTEGER DEFINES ------------------ */
N#define  DEF_INT_08_NBR_BITS                               8u
N#define  DEF_INT_08_MASK                                0xFFu
N
N#define  DEF_INT_08U_MIN_VAL                               0u
N#define  DEF_INT_08U_MAX_VAL                             255u
N
N#define  DEF_INT_08S_MIN_VAL_ONES_CPL                  (-127)
N#define  DEF_INT_08S_MAX_VAL_ONES_CPL                    127
N
N#define  DEF_INT_08S_MIN_VAL                            (DEF_INT_08S_MIN_VAL_ONES_CPL - 1)
N#define  DEF_INT_08S_MAX_VAL                             DEF_INT_08S_MAX_VAL_ONES_CPL
N
N#define  DEF_INT_08U_NBR_DIG_MIN                           1u
N#define  DEF_INT_08U_NBR_DIG_MAX                           3u
N
N#define  DEF_INT_08S_NBR_DIG_MIN                           3u
N#define  DEF_INT_08S_NBR_DIG_MAX                           3u
N
N
N
N#define  DEF_INT_16_NBR_BITS                              16u
N#define  DEF_INT_16_MASK                              0xFFFFu
N
N#define  DEF_INT_16U_MIN_VAL                               0u
N#define  DEF_INT_16U_MAX_VAL                           65535u
N
N#define  DEF_INT_16S_MIN_VAL_ONES_CPL                (-32767)
N#define  DEF_INT_16S_MAX_VAL_ONES_CPL                  32767
N
N#define  DEF_INT_16S_MIN_VAL                            (DEF_INT_16S_MIN_VAL_ONES_CPL - 1)
N#define  DEF_INT_16S_MAX_VAL                             DEF_INT_16S_MAX_VAL_ONES_CPL
N
N#define  DEF_INT_16U_NBR_DIG_MIN                           1u
N#define  DEF_INT_16U_NBR_DIG_MAX                           5u
N
N#define  DEF_INT_16S_NBR_DIG_MIN                           5u
N#define  DEF_INT_16S_NBR_DIG_MAX                           5u
N
N
N
N#define  DEF_INT_32_NBR_BITS                              32u
N#define  DEF_INT_32_MASK                          0xFFFFFFFFu
N
N#define  DEF_INT_32U_MIN_VAL                               0u
N#define  DEF_INT_32U_MAX_VAL                      4294967295u
N
N#define  DEF_INT_32S_MIN_VAL_ONES_CPL           (-2147483647)
N#define  DEF_INT_32S_MAX_VAL_ONES_CPL             2147483647
N
N#define  DEF_INT_32S_MIN_VAL                            (DEF_INT_32S_MIN_VAL_ONES_CPL - 1)
N#define  DEF_INT_32S_MAX_VAL                             DEF_INT_32S_MAX_VAL_ONES_CPL
N
N#define  DEF_INT_32U_NBR_DIG_MIN                           1u
N#define  DEF_INT_32U_NBR_DIG_MAX                          10u
N
N#define  DEF_INT_32S_NBR_DIG_MIN                          10u
N#define  DEF_INT_32S_NBR_DIG_MAX                          10u
N
N
N
N#define  DEF_INT_64_NBR_BITS                              64u
N#define  DEF_INT_64_MASK                  0xFFFFFFFFFFFFFFFFu
N
N#define  DEF_INT_64U_MIN_VAL                               0u
N#define  DEF_INT_64U_MAX_VAL            18446744073709551615u
N
N#define  DEF_INT_64S_MIN_VAL_ONES_CPL  (-9223372036854775807)
N#define  DEF_INT_64S_MAX_VAL_ONES_CPL    9223372036854775807
N
N#define  DEF_INT_64S_MIN_VAL                            (DEF_INT_64S_MIN_VAL_ONES_CPL - 1)
N#define  DEF_INT_64S_MAX_VAL                             DEF_INT_64S_MAX_VAL_ONES_CPL
N
N#define  DEF_INT_64U_NBR_DIG_MIN                           1u
N#define  DEF_INT_64U_NBR_DIG_MAX                          20u
N
N#define  DEF_INT_64S_NBR_DIG_MIN                          19u
N#define  DEF_INT_64S_NBR_DIG_MAX                          19u
N
N
N
N/*$PAGE*/
N                                                                /* --------------- CPU INTEGER DEFINES ---------------- */
N#define  DEF_INT_CPU_NBR_BITS                           (CPU_CFG_DATA_SIZE     * DEF_OCTET_NBR_BITS)
N#define  DEF_INT_CPU_NBR_BITS_MAX                       (CPU_CFG_DATA_SIZE_MAX * DEF_OCTET_NBR_BITS)
N
N
N
N#if     (DEF_INT_CPU_NBR_BITS == DEF_INT_08_NBR_BITS)
X#if     ((4 * 8u) == 8u)
S
S
S#define  DEF_INT_CPU_MASK                                DEF_INT_08_MASK
S
S#define  DEF_INT_CPU_U_MIN_VAL                           DEF_INT_08U_MIN_VAL
S#define  DEF_INT_CPU_U_MAX_VAL                           DEF_INT_08U_MAX_VAL
S
S#define  DEF_INT_CPU_S_MIN_VAL                           DEF_INT_08S_MIN_VAL
S#define  DEF_INT_CPU_S_MAX_VAL                           DEF_INT_08S_MAX_VAL
S
S#define  DEF_INT_CPU_S_MIN_VAL_ONES_CPL                  DEF_INT_08S_MIN_VAL_ONES_CPL
S#define  DEF_INT_CPU_S_MAX_VAL_ONES_CPL                  DEF_INT_08S_MAX_VAL_ONES_CPL
S
S
S
S#elif   (DEF_INT_CPU_NBR_BITS == DEF_INT_16_NBR_BITS)
X#elif   ((4 * 8u) == 16u)
S
S
S#define  DEF_INT_CPU_MASK                                DEF_INT_16_MASK
S
S#define  DEF_INT_CPU_U_MIN_VAL                           DEF_INT_16U_MIN_VAL
S#define  DEF_INT_CPU_U_MAX_VAL                           DEF_INT_16U_MAX_VAL
S
S#define  DEF_INT_CPU_S_MIN_VAL                           DEF_INT_16S_MIN_VAL
S#define  DEF_INT_CPU_S_MAX_VAL                           DEF_INT_16S_MAX_VAL
S
S#define  DEF_INT_CPU_S_MIN_VAL_ONES_CPL                  DEF_INT_16S_MIN_VAL_ONES_CPL
S#define  DEF_INT_CPU_S_MAX_VAL_ONES_CPL                  DEF_INT_16S_MAX_VAL_ONES_CPL
S
S
S
N#elif   (DEF_INT_CPU_NBR_BITS == DEF_INT_32_NBR_BITS)
X#elif   ((4 * 8u) == 32u)
N
N
N#define  DEF_INT_CPU_MASK                                DEF_INT_32_MASK
N
N#define  DEF_INT_CPU_U_MIN_VAL                           DEF_INT_32U_MIN_VAL
N#define  DEF_INT_CPU_U_MAX_VAL                           DEF_INT_32U_MAX_VAL
N
N#define  DEF_INT_CPU_S_MIN_VAL                           DEF_INT_32S_MIN_VAL
N#define  DEF_INT_CPU_S_MAX_VAL                           DEF_INT_32S_MAX_VAL
N
N#define  DEF_INT_CPU_S_MIN_VAL_ONES_CPL                  DEF_INT_32S_MIN_VAL_ONES_CPL
N#define  DEF_INT_CPU_S_MAX_VAL_ONES_CPL                  DEF_INT_32S_MAX_VAL_ONES_CPL
N
N
N
N#elif   (DEF_INT_CPU_NBR_BITS == DEF_INT_64_NBR_BITS)
S
S
S#define  DEF_INT_CPU_MASK                                DEF_INT_64_MASK
S
S#define  DEF_INT_CPU_U_MIN_VAL                           DEF_INT_64U_MIN_VAL
S#define  DEF_INT_CPU_U_MAX_VAL                           DEF_INT_64U_MAX_VAL
S
S#define  DEF_INT_CPU_S_MIN_VAL                           DEF_INT_64S_MIN_VAL
S#define  DEF_INT_CPU_S_MAX_VAL                           DEF_INT_64S_MAX_VAL
S
S#define  DEF_INT_CPU_S_MIN_VAL_ONES_CPL                  DEF_INT_64S_MIN_VAL_ONES_CPL
S#define  DEF_INT_CPU_S_MAX_VAL_ONES_CPL                  DEF_INT_64S_MAX_VAL_ONES_CPL
S
S
S
S#else
S
S#error  "CPU_CFG_DATA_SIZE  illegally #defined in 'cpu.h'      "
S#error  "                   [See 'cpu.h  CONFIGURATION ERRORS']"
S
N#endif
N
N
N
N/*$PAGE*/
N                                                                /* ------------------- TIME DEFINES ------------------- */
N#define  DEF_TIME_NBR_DAY_PER_WK                           7u
N#define  DEF_TIME_NBR_DAY_PER_YR                         365u
N#define  DEF_TIME_NBR_DAY_PER_YR_LEAP                    366u
N
N#define  DEF_TIME_NBR_HR_PER_DAY                          24u
N#define  DEF_TIME_NBR_HR_PER_WK                         (DEF_TIME_NBR_HR_PER_DAY  * DEF_TIME_NBR_DAY_PER_WK     )
N#define  DEF_TIME_NBR_HR_PER_YR                         (DEF_TIME_NBR_HR_PER_DAY  * DEF_TIME_NBR_DAY_PER_YR     )
N#define  DEF_TIME_NBR_HR_PER_YR_LEAP                    (DEF_TIME_NBR_HR_PER_DAY  * DEF_TIME_NBR_DAY_PER_YR_LEAP)
N
N#define  DEF_TIME_NBR_MIN_PER_HR                          60u
N#define  DEF_TIME_NBR_MIN_PER_DAY                       (DEF_TIME_NBR_MIN_PER_HR  * DEF_TIME_NBR_HR_PER_DAY     )
N#define  DEF_TIME_NBR_MIN_PER_WK                        (DEF_TIME_NBR_MIN_PER_DAY * DEF_TIME_NBR_DAY_PER_WK     )
N#define  DEF_TIME_NBR_MIN_PER_YR                        (DEF_TIME_NBR_MIN_PER_DAY * DEF_TIME_NBR_DAY_PER_YR     )
N#define  DEF_TIME_NBR_MIN_PER_YR_LEAP                   (DEF_TIME_NBR_MIN_PER_DAY * DEF_TIME_NBR_DAY_PER_YR_LEAP)
N
N#define  DEF_TIME_NBR_SEC_PER_MIN                         60u
N#define  DEF_TIME_NBR_SEC_PER_HR                        (DEF_TIME_NBR_SEC_PER_MIN * DEF_TIME_NBR_MIN_PER_HR     )
N#define  DEF_TIME_NBR_SEC_PER_DAY                       (DEF_TIME_NBR_SEC_PER_HR  * DEF_TIME_NBR_HR_PER_DAY     )
N#define  DEF_TIME_NBR_SEC_PER_WK                        (DEF_TIME_NBR_SEC_PER_DAY * DEF_TIME_NBR_DAY_PER_WK     )
N#define  DEF_TIME_NBR_SEC_PER_YR                        (DEF_TIME_NBR_SEC_PER_DAY * DEF_TIME_NBR_DAY_PER_YR     )
N#define  DEF_TIME_NBR_SEC_PER_YR_LEAP                   (DEF_TIME_NBR_SEC_PER_DAY * DEF_TIME_NBR_DAY_PER_YR_LEAP)
N
N#define  DEF_TIME_NBR_mS_PER_SEC                        1000u
N#define  DEF_TIME_NBR_uS_PER_SEC                     1000000u
N#define  DEF_TIME_NBR_nS_PER_SEC                  1000000000u
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                             ERROR CODES
N*
N* Note(s) : (1) All library error codes are #define'd in 'lib_def.h';
N*********************************************************************************************************
N*/
N
Ntypedef enum lib_err {
N
N    LIB_ERR_NONE                            =         0u,
N
N    LIB_MEM_ERR_NONE                        =     10000u,
N    LIB_MEM_ERR_NULL_PTR                    =     10001u,       /* Ptr arg(s) passed NULL ptr(s).                       */
N
N    LIB_MEM_ERR_INVALID_MEM_SIZE            =     10100u,       /* Invalid mem     size.                                */
N    LIB_MEM_ERR_INVALID_MEM_ALIGN           =     10101u,       /* Invalid mem     align.                               */
N    LIB_MEM_ERR_INVALID_SEG_SIZE            =     10110u,       /* Invalid mem seg size.                                */
N    LIB_MEM_ERR_INVALID_SEG_OVERLAP         =     10111u,       /* Invalid mem seg overlaps other mem seg(s).           */
N    LIB_MEM_ERR_INVALID_POOL                =     10120u,       /* Invalid mem pool.                                    */
N    LIB_MEM_ERR_INVALID_BLK_NBR             =     10130u,       /* Invalid mem pool blk nbr.                            */
N    LIB_MEM_ERR_INVALID_BLK_SIZE            =     10131u,       /* Invalid mem pool blk size.                           */
N    LIB_MEM_ERR_INVALID_BLK_ALIGN           =     10132u,       /* Invalid mem pool blk align.                          */
N    LIB_MEM_ERR_INVALID_BLK_IX              =     10133u,       /* Invalid mem pool ix.                                 */
N    LIB_MEM_ERR_INVALID_BLK_ADDR            =     10135u,       /* Invalid mem pool blk addr.                           */
N    LIB_MEM_ERR_INVALID_BLK_ADDR_IN_POOL    =     10136u,       /* Mem pool blk addr already in mem pool.               */
N
N    LIB_MEM_ERR_SEG_EMPTY                   =     10200u,       /* Mem seg  empty; i.e. NO avail mem in seg.            */
N    LIB_MEM_ERR_SEG_OVF                     =     10201u,       /* Mem seg  ovf;   i.e. req'd mem ovfs rem mem in seg.  */
N    LIB_MEM_ERR_POOL_FULL                   =     10205u,       /* Mem pool full;  i.e. all mem blks avail in mem pool. */
N    LIB_MEM_ERR_POOL_EMPTY                  =     10206u,       /* Mem pool empty; i.e. NO  mem blks avail in mem pool. */
N
N    LIB_MEM_ERR_HEAP_EMPTY                  =     10210u,       /* Heap seg empty; i.e. NO avail mem in heap.           */
N    LIB_MEM_ERR_HEAP_OVF                    =     10211u,       /* Heap seg ovf;   i.e. req'd mem ovfs rem mem in heap. */
N    LIB_MEM_ERR_HEAP_NOT_FOUND              =     10215u        /* Heap seg NOT found.                                  */
N
N} LIB_ERR;
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                             DATA TYPES
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                          GLOBAL VARIABLES
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                               TRACING
N*********************************************************************************************************
N*/
N
N                                                                /* Trace level, default to TRACE_LEVEL_OFF.             */
N#ifndef  TRACE_LEVEL_OFF
N#define  TRACE_LEVEL_OFF                                   0u
N#endif
N
N#ifndef  TRACE_LEVEL_INFO
N#define  TRACE_LEVEL_INFO                                  1u
N#endif
N
N#ifndef  TRACE_LEVEL_DBG
N#define  TRACE_LEVEL_DBG                                   2u
N#endif
N
N#ifndef  TRACE_LEVEL_LOG
N#define  TRACE_LEVEL_LOG                                   3u
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                             BIT MACRO'S
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                              DEF_BIT()
N*
N* Description : Create bit mask with single, specified bit set.
N*
N* Argument(s) : bit         Bit number of bit to set.
N*
N* Return(s)   : Bit mask with single, specified bit set.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) 'bit' SHOULD be a non-negative integer.
N*
N*               (2) (a) 'bit' values that overflow the target CPU &/or compiler environment (e.g. negative 
N*                       or greater-than-CPU-data-size values) MAY generate compiler warnings &/or errors.
N*********************************************************************************************************
N*/
N
N#define  DEF_BIT(bit)                                                   (1u << (bit))
N
N
N/*
N*********************************************************************************************************
N*                                             DEF_BITxx()
N*
N* Description : Create bit mask of specified bit size with single, specified bit set.
N*
N* Argument(s) : bit         Bit number of bit to set.
N*
N* Return(s)   : Bit mask with single, specified bit set.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) 'bit' SHOULD be a non-negative integer.
N*
N*               (2) (a) 'bit' values that overflow the target CPU &/or compiler environment (e.g. negative 
N*                       or greater-than-CPU-data-size values) MAY generate compiler warnings &/or errors.
N*
N*                   (b) To avoid overflowing any target CPU &/or compiler's integer data type, unsigned 
N*                       bit constant '1' is cast to specified integer data type size.
N*
N*               (3) Ideally, DEF_BITxx() macro's should be named DEF_BIT_xx(); however, these names already 
N*                   previously-released for bit constant #define's (see 'STANDARD DEFINES  BIT DEFINES').
N*********************************************************************************************************
N*/
N
N#define  DEF_BIT08(bit)                        ((CPU_INT08U)((CPU_INT08U)1u  << (bit)))
N
N#define  DEF_BIT16(bit)                        ((CPU_INT16U)((CPU_INT16U)1u  << (bit)))
N
N#define  DEF_BIT32(bit)                        ((CPU_INT32U)((CPU_INT32U)1u  << (bit)))
N
N#define  DEF_BIT64(bit)                        ((CPU_INT64U)((CPU_INT64U)1u  << (bit)))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                           DEF_BIT_MASK()
N*
N* Description : Shift a bit mask.
N*
N* Argument(s) : bit_mask    Bit mask to shift.
N*
N*               bit_shift   Number of bit positions to left-shift bit mask.
N*
N* Return(s)   : Shifted bit mask.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) (a) 'bit_mask'  SHOULD be an unsigned    integer.
N*
N*                   (b) 'bit_shift' SHOULD be a non-negative integer.
N*
N*               (2) 'bit_shift' values that overflow the target CPU &/or compiler environment (e.g. negative
N*                   or greater-than-CPU-data-size values) MAY generate compiler warnings &/or errors.
N*********************************************************************************************************
N*/
N
N#define  DEF_BIT_MASK(bit_mask, bit_shift)                                     ((bit_mask) << (bit_shift))
N
N
N/*
N*********************************************************************************************************
N*                                          DEF_BIT_MASK_xx()
N*
N* Description : Shift a bit mask of specified bit size.
N*
N* Argument(s) : bit_mask    Bit mask to shift.
N*
N*               bit_shift   Number of bit positions to left-shift bit mask.
N*
N* Return(s)   : Shifted bit mask.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) (a) 'bit_mask'  SHOULD be an unsigned    integer.
N*
N*                   (b) 'bit_shift' SHOULD be a non-negative integer.
N*
N*               (2) 'bit_shift' values that overflow the target CPU &/or compiler environment (e.g. negative
N*                   or greater-than-CPU-data-size values) MAY generate compiler warnings &/or errors.
N*********************************************************************************************************
N*/
N
N#define  DEF_BIT_MASK_08(bit_mask, bit_shift)         ((CPU_INT08U)((CPU_INT08U)(bit_mask) << (bit_shift)))
N
N#define  DEF_BIT_MASK_16(bit_mask, bit_shift)         ((CPU_INT16U)((CPU_INT16U)(bit_mask) << (bit_shift)))
N
N#define  DEF_BIT_MASK_32(bit_mask, bit_shift)         ((CPU_INT32U)((CPU_INT32U)(bit_mask) << (bit_shift)))
N
N#define  DEF_BIT_MASK_64(bit_mask, bit_shift)         ((CPU_INT64U)((CPU_INT64U)(bit_mask) << (bit_shift)))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                           DEF_BIT_FIELD()
N*
N* Description : Create & shift a contiguous bit field.
N*
N* Argument(s) : bit_field   Number of contiguous bits to set in the bit field.
N*
N*               bit_shift   Number of bit positions   to left-shift bit field.
N*
N* Return(s)   : Shifted bit field.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) 'bit_field' & 'bit_shift' SHOULD be non-negative integers.
N*
N*               (2) (a) 'bit_field'/'bit_shift' values that overflow the target CPU &/or compiler 
N*                       environment (e.g. negative or greater-than-CPU-data-size values) MAY generate 
N*                       compiler warnings &/or errors.
N*
N*                   (b) To avoid overflowing any target CPU &/or compiler's integer data type, unsigned 
N*                       bit constant '1' is suffixed with 'L'ong integer modifier.
N*
N*                       This may still be insufficient for CPUs &/or compilers that support 'long long' 
N*                       integer data types, in which case 'LL' integer modifier should be suffixed.  
N*                       However, since almost all 16- & 32-bit CPUs & compilers support 'long' integer 
N*                       data types but many may NOT support 'long long' integer data types, only 'long' 
N*                       integer data types & modifiers are supported.
N*
N*                       See also 'DEF_BIT_FIELD_xx()  Note #1b'.
N*********************************************************************************************************
N*/
N
N#define  DEF_BIT_FIELD(bit_field, bit_shift)                                 ((((bit_field) >= DEF_INT_CPU_NBR_BITS) ? (DEF_INT_CPU_U_MAX_VAL)     \
N                                                                                                                     : (DEF_BIT(bit_field) - 1uL)) \
N                                                                                                                            << (bit_shift))
X#define  DEF_BIT_FIELD(bit_field, bit_shift)                                 ((((bit_field) >= DEF_INT_CPU_NBR_BITS) ? (DEF_INT_CPU_U_MAX_VAL)                                                                                                                          : (DEF_BIT(bit_field) - 1uL))                                                                                                                             << (bit_shift))
N
N/*
N*********************************************************************************************************
N*                                         DEF_BIT_FIELD_xx()
N*
N* Description : Create & shift a contiguous bit field of specified bit size.
N*
N* Argument(s) : bit_field   Number of contiguous bits to set in the bit field.
N*
N*               bit_shift   Number of bit positions   to left-shift bit field.
N*
N* Return(s)   : Shifted bit field.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) 'bit_field' & 'bit_shift' SHOULD be non-negative integers.
N*
N*               (2) (a) 'bit_field'/'bit_shift' values that overflow the target CPU &/or compiler 
N*                       environment (e.g. negative or greater-than-CPU-data-size values) MAY generate 
N*                       compiler warnings &/or errors.
N*
N*                   (b) To avoid overflowing any target CPU &/or compiler's integer data type, unsigned 
N*                       bit constant '1' is cast to specified integer data type size.
N*********************************************************************************************************
N*/
N
N#define  DEF_BIT_FIELD_08(bit_field, bit_shift)     ((CPU_INT08U)((((CPU_INT08U)(bit_field) >= (CPU_INT08U)DEF_INT_08_NBR_BITS) ? (CPU_INT08U)(DEF_INT_08U_MAX_VAL)                    \
N                                                                                                                                : (CPU_INT08U)(DEF_BIT08(bit_field) - (CPU_INT08U)1u)) \
N                                                                                                                                                     << (bit_shift)))
X#define  DEF_BIT_FIELD_08(bit_field, bit_shift)     ((CPU_INT08U)((((CPU_INT08U)(bit_field) >= (CPU_INT08U)DEF_INT_08_NBR_BITS) ? (CPU_INT08U)(DEF_INT_08U_MAX_VAL)                                                                                                                                                    : (CPU_INT08U)(DEF_BIT08(bit_field) - (CPU_INT08U)1u))                                                                                                                                                      << (bit_shift)))
N
N#define  DEF_BIT_FIELD_16(bit_field, bit_shift)     ((CPU_INT16U)((((CPU_INT16U)(bit_field) >= (CPU_INT16U)DEF_INT_16_NBR_BITS) ? (CPU_INT16U)(DEF_INT_16U_MAX_VAL)                    \
N                                                                                                                                : (CPU_INT16U)(DEF_BIT16(bit_field) - (CPU_INT16U)1u)) \
N                                                                                                                                                     << (bit_shift)))
X#define  DEF_BIT_FIELD_16(bit_field, bit_shift)     ((CPU_INT16U)((((CPU_INT16U)(bit_field) >= (CPU_INT16U)DEF_INT_16_NBR_BITS) ? (CPU_INT16U)(DEF_INT_16U_MAX_VAL)                                                                                                                                                    : (CPU_INT16U)(DEF_BIT16(bit_field) - (CPU_INT16U)1u))                                                                                                                                                      << (bit_shift)))
N
N#define  DEF_BIT_FIELD_32(bit_field, bit_shift)     ((CPU_INT32U)((((CPU_INT32U)(bit_field) >= (CPU_INT32U)DEF_INT_32_NBR_BITS) ? (CPU_INT32U)(DEF_INT_32U_MAX_VAL)                    \
N                                                                                                                                : (CPU_INT32U)(DEF_BIT32(bit_field) - (CPU_INT32U)1u)) \
N                                                                                                                                                     << (bit_shift)))
X#define  DEF_BIT_FIELD_32(bit_field, bit_shift)     ((CPU_INT32U)((((CPU_INT32U)(bit_field) >= (CPU_INT32U)DEF_INT_32_NBR_BITS) ? (CPU_INT32U)(DEF_INT_32U_MAX_VAL)                                                                                                                                                    : (CPU_INT32U)(DEF_BIT32(bit_field) - (CPU_INT32U)1u))                                                                                                                                                      << (bit_shift)))
N
N#define  DEF_BIT_FIELD_64(bit_field, bit_shift)     ((CPU_INT64U)((((CPU_INT64U)(bit_field) >= (CPU_INT64U)DEF_INT_64_NBR_BITS) ? (CPU_INT64U)(DEF_INT_64U_MAX_VAL)                    \
N                                                                                                                                : (CPU_INT64U)(DEF_BIT64(bit_field) - (CPU_INT64U)1u)) \
N                                                                                                                                                     << (bit_shift)))
X#define  DEF_BIT_FIELD_64(bit_field, bit_shift)     ((CPU_INT64U)((((CPU_INT64U)(bit_field) >= (CPU_INT64U)DEF_INT_64_NBR_BITS) ? (CPU_INT64U)(DEF_INT_64U_MAX_VAL)                                                                                                                                                    : (CPU_INT64U)(DEF_BIT64(bit_field) - (CPU_INT64U)1u))                                                                                                                                                      << (bit_shift)))
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          DEF_BIT_SET_xx()
N*
N* Description : Set specified bit(s) in a value of specified bit size.
N*
N* Argument(s) : val         Value to modify by setting specified bit(s).
N*
N*               mask        Mask of bits to set.
N*
N* Return(s)   : Modified value with specified bit(s) set.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) 'val' & 'mask' SHOULD be unsigned integers.
N*********************************************************************************************************
N*/
N
N#define  DEF_BIT_SET_08(val, mask)                     ((val) = (CPU_INT08U)(((CPU_INT08U)(val)) | ((CPU_INT08U) (mask))))
N
N#define  DEF_BIT_SET_16(val, mask)                     ((val) = (CPU_INT16U)(((CPU_INT16U)(val)) | ((CPU_INT16U) (mask))))
N
N#define  DEF_BIT_SET_32(val, mask)                     ((val) = (CPU_INT32U)(((CPU_INT32U)(val)) | ((CPU_INT32U) (mask))))
N
N#define  DEF_BIT_SET_64(val, mask)                     ((val) = (CPU_INT64U)(((CPU_INT64U)(val)) | ((CPU_INT64U) (mask))))
N
N
N/*
N*********************************************************************************************************
N*                                            DEF_BIT_SET()
N*
N* Description : Set specified bit(s) in a value.
N*
N* Argument(s) : val         Value to modify by setting specified bit(s).
N*
N*               mask        Mask of bits to set.
N*
N* Return(s)   : Modified value with specified bit(s) set.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) 'val' & 'mask' SHOULD be unsigned integers.
N*********************************************************************************************************
N*/
N
N#if     (CPU_CFG_DATA_SIZE_MAX == CPU_WORD_SIZE_08)
X#if     (8 == 1)
S
S#define  DEF_BIT_SET(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_SET_08(val, mask) : 0)
S
S
S#elif   (CPU_CFG_DATA_SIZE_MAX == CPU_WORD_SIZE_16)
X#elif   (8 == 2)
S
S#define  DEF_BIT_SET(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_SET_08(val, mask) :   \
S                                                ((sizeof(val) == CPU_WORD_SIZE_16) ? DEF_BIT_SET_16(val, mask) : 0))
X#define  DEF_BIT_SET(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_SET_08(val, mask) :                                                   ((sizeof(val) == CPU_WORD_SIZE_16) ? DEF_BIT_SET_16(val, mask) : 0))
S
S
S#elif   (CPU_CFG_DATA_SIZE_MAX == CPU_WORD_SIZE_32)
X#elif   (8 == 4)
S
S#define  DEF_BIT_SET(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_SET_08(val, mask) :    \
S                                                ((sizeof(val) == CPU_WORD_SIZE_16) ? DEF_BIT_SET_16(val, mask) :    \
S                                                ((sizeof(val) == CPU_WORD_SIZE_32) ? DEF_BIT_SET_32(val, mask) : 0)))
X#define  DEF_BIT_SET(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_SET_08(val, mask) :                                                    ((sizeof(val) == CPU_WORD_SIZE_16) ? DEF_BIT_SET_16(val, mask) :                                                    ((sizeof(val) == CPU_WORD_SIZE_32) ? DEF_BIT_SET_32(val, mask) : 0)))
S
S
N#elif   (CPU_CFG_DATA_SIZE_MAX == CPU_WORD_SIZE_64)
X#elif   (8 == 8)
N
N#define  DEF_BIT_SET(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_SET_08(val, mask) :     \
N                                                ((sizeof(val) == CPU_WORD_SIZE_16) ? DEF_BIT_SET_16(val, mask) :     \
N                                                ((sizeof(val) == CPU_WORD_SIZE_32) ? DEF_BIT_SET_32(val, mask) :     \
N                                                ((sizeof(val) == CPU_WORD_SIZE_64) ? DEF_BIT_SET_64(val, mask) : 0))))
X#define  DEF_BIT_SET(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_SET_08(val, mask) :                                                     ((sizeof(val) == CPU_WORD_SIZE_16) ? DEF_BIT_SET_16(val, mask) :                                                     ((sizeof(val) == CPU_WORD_SIZE_32) ? DEF_BIT_SET_32(val, mask) :                                                     ((sizeof(val) == CPU_WORD_SIZE_64) ? DEF_BIT_SET_64(val, mask) : 0))))
N
N#else
S
S#error  "CPU_CFG_DATA_SIZE_MAX  illegally #defined in 'cpu.h'      "
S#error  "                       [See 'cpu.h  CONFIGURATION ERRORS']"
S
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          DEF_BIT_CLR_xx()
N*
N* Description : Clear specified bit(s) in a value of specified bit size.
N*
N* Argument(s) : val         Value to modify by clearing specified bit(s).
N*
N*               mask        Mask of bits to clear.
N*
N* Return(s)   : Modified value with specified bit(s) clear.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) 'val' & 'mask' SHOULD be unsigned integers.
N*********************************************************************************************************
N*/
N
N#define  DEF_BIT_CLR_08(val, mask)                     ((val) = (CPU_INT08U)(((CPU_INT08U)(val)) & ((CPU_INT08U)~(mask))))
N
N#define  DEF_BIT_CLR_16(val, mask)                     ((val) = (CPU_INT16U)(((CPU_INT16U)(val)) & ((CPU_INT16U)~(mask))))
N
N#define  DEF_BIT_CLR_32(val, mask)                     ((val) = (CPU_INT32U)(((CPU_INT32U)(val)) & ((CPU_INT32U)~(mask))))
N
N#define  DEF_BIT_CLR_64(val, mask)                     ((val) = (CPU_INT64U)(((CPU_INT64U)(val)) & ((CPU_INT64U)~(mask))))
N
N
N/*
N*********************************************************************************************************
N*                                            DEF_BIT_CLR()
N*
N* Description : Clear specified bit(s) in a value.
N*
N* Argument(s) : val         Value to modify by clearing specified bit(s).
N*
N*               mask        Mask of bits to clear.
N*
N* Return(s)   : Modified value with specified bit(s) clear.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) 'val' & 'mask' SHOULD be unsigned integers.
N*********************************************************************************************************
N*/
N
N#if     (CPU_CFG_DATA_SIZE_MAX == CPU_WORD_SIZE_08)
X#if     (8 == 1)
S
S#define  DEF_BIT_CLR(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_CLR_08(val, mask) : 0)
S
S
S#elif   (CPU_CFG_DATA_SIZE_MAX == CPU_WORD_SIZE_16)
X#elif   (8 == 2)
S
S#define  DEF_BIT_CLR(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_CLR_08(val, mask) :   \
S                                                ((sizeof(val) == CPU_WORD_SIZE_16) ? DEF_BIT_CLR_16(val, mask) : 0))
X#define  DEF_BIT_CLR(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_CLR_08(val, mask) :                                                   ((sizeof(val) == CPU_WORD_SIZE_16) ? DEF_BIT_CLR_16(val, mask) : 0))
S
S
S#elif   (CPU_CFG_DATA_SIZE_MAX == CPU_WORD_SIZE_32)
X#elif   (8 == 4)
S
S#define  DEF_BIT_CLR(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_CLR_08(val, mask) :    \
S                                                ((sizeof(val) == CPU_WORD_SIZE_16) ? DEF_BIT_CLR_16(val, mask) :    \
S                                                ((sizeof(val) == CPU_WORD_SIZE_32) ? DEF_BIT_CLR_32(val, mask) : 0)))
X#define  DEF_BIT_CLR(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_CLR_08(val, mask) :                                                    ((sizeof(val) == CPU_WORD_SIZE_16) ? DEF_BIT_CLR_16(val, mask) :                                                    ((sizeof(val) == CPU_WORD_SIZE_32) ? DEF_BIT_CLR_32(val, mask) : 0)))
S
S
N#elif   (CPU_CFG_DATA_SIZE_MAX == CPU_WORD_SIZE_64)
X#elif   (8 == 8)
N
N#define  DEF_BIT_CLR(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_CLR_08(val, mask) :     \
N                                                ((sizeof(val) == CPU_WORD_SIZE_16) ? DEF_BIT_CLR_16(val, mask) :     \
N                                                ((sizeof(val) == CPU_WORD_SIZE_32) ? DEF_BIT_CLR_32(val, mask) :     \
N                                                ((sizeof(val) == CPU_WORD_SIZE_64) ? DEF_BIT_CLR_64(val, mask) : 0))))
X#define  DEF_BIT_CLR(val, mask)                 ((sizeof(val) == CPU_WORD_SIZE_08) ? DEF_BIT_CLR_08(val, mask) :                                                     ((sizeof(val) == CPU_WORD_SIZE_16) ? DEF_BIT_CLR_16(val, mask) :                                                     ((sizeof(val) == CPU_WORD_SIZE_32) ? DEF_BIT_CLR_32(val, mask) :                                                     ((sizeof(val) == CPU_WORD_SIZE_64) ? DEF_BIT_CLR_64(val, mask) : 0))))
N
N#else
S
S#error  "CPU_CFG_DATA_SIZE_MAX  illegally #defined in 'cpu.h'      "
S#error  "                       [See 'cpu.h  CONFIGURATION ERRORS']"
S
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          DEF_BIT_IS_SET()
N*
N* Description : Determine if specified bit(s) in a value are set.
N*
N* Argument(s) : val         Value to check for specified bit(s) set.
N*
N*               mask        Mask of bits to check if set (see Note #2).
N*
N* Return(s)   : DEF_YES, if ALL specified bit(s) are     set in value.
N*
N*               DEF_NO,  if ALL specified bit(s) are NOT set in value.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) 'val' & 'mask' SHOULD be unsigned integers.
N*
N*               (2) NULL 'mask' allowed; returns 'DEF_NO' since NO mask bits specified.
N*********************************************************************************************************
N*/
N
N#define  DEF_BIT_IS_SET(val, mask)                           ((((mask)  !=  0u)  && \
N                                                      (((val) & (mask)) == (mask))) ? (DEF_YES) : (DEF_NO ))
X#define  DEF_BIT_IS_SET(val, mask)                           ((((mask)  !=  0u)  &&                                                       (((val) & (mask)) == (mask))) ? (DEF_YES) : (DEF_NO ))
N
N
N/*
N*********************************************************************************************************
N*                                          DEF_BIT_IS_CLR()
N*
N* Description : Determine if specified bit(s) in a value are clear.
N*
N* Argument(s) : val         Value to check for specified bit(s) clear.
N*
N*               mask        Mask of bits to check if clear (see Note #2).
N*
N* Return(s)   : DEF_YES, if ALL specified bit(s) are     clear in value.
N*
N*               DEF_NO,  if ALL specified bit(s) are NOT clear in value.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) 'val' & 'mask' SHOULD be unsigned integers.
N*
N*               (2) NULL 'mask' allowed; returns 'DEF_NO' since NO mask bits specified.
N*********************************************************************************************************
N*/
N
N#define  DEF_BIT_IS_CLR(val, mask)                           ((((mask)  !=  0u)  && \
N                                                      (((val) & (mask)) ==  0u))    ? (DEF_YES) : (DEF_NO ))
X#define  DEF_BIT_IS_CLR(val, mask)                           ((((mask)  !=  0u)  &&                                                       (((val) & (mask)) ==  0u))    ? (DEF_YES) : (DEF_NO ))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                        DEF_BIT_IS_SET_ANY()
N*
N* Description : Determine if any specified bit(s) in a value are set.
N*
N* Argument(s) : val         Value to check for specified bit(s) set.
N*
N*               mask        Mask of bits to check if set (see Note #2).
N*
N* Return(s)   : DEF_YES, if ANY specified bit(s) are     set in value.
N*
N*               DEF_NO,  if ALL specified bit(s) are NOT set in value.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) 'val' & 'mask' SHOULD be unsigned integers.
N*
N*               (2) NULL 'mask' allowed; returns 'DEF_NO' since NO mask bits specified.
N*********************************************************************************************************
N*/
N
N#define  DEF_BIT_IS_SET_ANY(val, mask)               ((((val) & (mask)) ==  0u)     ? (DEF_NO ) : (DEF_YES))
N
N
N/*
N*********************************************************************************************************
N*                                        DEF_BIT_IS_CLR_ANY()
N*
N* Description : Determine if any specified bit(s) in a value are clear.
N*
N* Argument(s) : val         Value to check for specified bit(s) clear.
N*
N*               mask        Mask of bits to check if clear (see Note #2).
N*
N* Return(s)   : DEF_YES, if ANY specified bit(s) are     clear in value.
N*
N*               DEF_NO,  if ALL specified bit(s) are NOT clear in value.
N*
N* Note(s)     : (1) 'val' & 'mask' SHOULD be unsigned integers.
N*
N*               (2) NULL 'mask' allowed; returns 'DEF_NO' since NO mask bits specified.
N*********************************************************************************************************
N*/
N
N#define  DEF_BIT_IS_CLR_ANY(val, mask)               ((((val) & (mask)) == (mask))  ? (DEF_NO ) : (DEF_YES))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                            VALUE MACRO'S
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                          DEF_CHK_VAL_MIN()
N*
N* Description : Validate a value as greater than or equal to a specified minimum value.
N*
N* Argument(s) : val        Value to validate.
N*
N*               val_min    Minimum value to test.
N*
N* Return(s)   : DEF_OK,    Value is greater than or equal to minimum value.
N*
N*               DEF_FAIL,  otherwise.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) DEF_CHK_VAL_MIN() avoids directly comparing any two values if only one of the values 
N*                   is negative since the negative value might be incorrectly promoted to an arbitrary 
N*                   unsigned value if the other value to compare is unsigned.
N*
N*               (2) Validation of values is limited to the range supported by the compiler &/or target 
N*                   environment.  All other values that underflow/overflow the supported range will 
N*                   modulo/wrap into the supported range as arbitrary signed or unsigned values.
N*
N*                   Therefore, any values that underflow the most negative signed value or overflow 
N*                   the most positive unsigned value supported by the compiler &/or target environment 
N*                   cannot be validated :
N*
N*                           (    N-1       N     ]
N*                           ( -(2   )  ,  2  - 1 ]
N*                           (                    ]
N*
N*                               where
N*                                       N       Number of data word bits supported by the compiler 
N*                                                   &/or target environment
N*
N*                   (a) Note that the most negative value, -2^(N-1), is NOT included in the supported 
N*                       range since many compilers do NOT always correctly handle this value.
N*
N*               (3) 'val' and 'val_min' are compared to 1 instead of 0 to avoid warning generated for
N*                   unsigned numbers.
N*********************************************************************************************************
N*/
N
N#define  DEF_CHK_VAL_MIN(val, val_min)            (((!(((val)     >= 1) && ((val_min) < 1))) && \
N                                                     ((((val_min) >= 1) && ((val)     < 1))  || \
N                                                       ((val) < (val_min)))) ? DEF_FAIL : DEF_OK)
X#define  DEF_CHK_VAL_MIN(val, val_min)            (((!(((val)     >= 1) && ((val_min) < 1))) &&                                                      ((((val_min) >= 1) && ((val)     < 1))  ||                                                        ((val) < (val_min)))) ? DEF_FAIL : DEF_OK)
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          DEF_CHK_VAL_MAX()
N*
N* Description : Validate a value as less than or equal to a specified maximum value.
N*
N* Argument(s) : val        Value to validate.
N*
N*               val_max    Maximum value to test.
N*
N* Return(s)   : DEF_OK,    Value is less than or equal to maximum value.
N*
N*               DEF_FAIL,  otherwise.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) DEF_CHK_VAL_MAX() avoids directly comparing any two values if only one of the values 
N*                   is negative since the negative value might be incorrectly promoted to an arbitrary 
N*                   unsigned value if the other value to compare is unsigned.
N*
N*               (2) Validation of values is limited to the range supported by the compiler &/or target 
N*                   environment.  All other values that underflow/overflow the supported range will 
N*                   modulo/wrap into the supported range as arbitrary signed or unsigned values.
N*
N*                   Therefore, any values that underflow the most negative signed value or overflow 
N*                   the most positive unsigned value supported by the compiler &/or target environment 
N*                   cannot be validated :
N*
N*                           (    N-1       N     ]
N*                           ( -(2   )  ,  2  - 1 ]
N*                           (                    ]
N*
N*                               where
N*                                       N       Number of data word bits supported by the compiler 
N*                                                   &/or target environment
N*
N*                   (a) Note that the most negative value, -2^(N-1), is NOT included in the supported 
N*                       range since many compilers do NOT always correctly handle this value.
N*
N*               (3) 'val' and 'val_max' are compared to 1 instead of 0 to avoid warning generated for
N*                   unsigned numbers.
N*********************************************************************************************************
N*/
N
N#define  DEF_CHK_VAL_MAX(val, val_max)            (((!(((val_max) >= 1) && ((val)     < 1))) && \
N                                                     ((((val)     >= 1) && ((val_max) < 1))  || \
N                                                       ((val) > (val_max)))) ? DEF_FAIL : DEF_OK)
X#define  DEF_CHK_VAL_MAX(val, val_max)            (((!(((val_max) >= 1) && ((val)     < 1))) &&                                                      ((((val)     >= 1) && ((val_max) < 1))  ||                                                        ((val) > (val_max)))) ? DEF_FAIL : DEF_OK)
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                            DEF_CHK_VAL()
N*
N* Description : Validate a value as greater than or equal to a specified minimum value & less than or 
N*                   equal to a specified maximum value.
N*
N* Argument(s) : val        Value to validate.
N*
N*               val_min    Minimum value to test.
N*
N*               val_max    Maximum value to test.
N*
N* Return(s)   : DEF_OK,    Value is greater than or equal to minimum value AND 
N*                                   less    than or equal to maximum value.
N*
N*               DEF_FAIL,  otherwise.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) DEF_CHK_VAL() avoids directly comparing any two values if only one of the values 
N*                   is negative since the negative value might be incorrectly promoted to an arbitrary 
N*                   unsigned value if the other value to compare is unsigned.
N*
N*               (2) Validation of values is limited to the range supported by the compiler &/or target 
N*                   environment.  All other values that underflow/overflow the supported range will 
N*                   modulo/wrap into the supported range as arbitrary signed or unsigned values.
N*
N*                   Therefore, any values that underflow the most negative signed value or overflow 
N*                   the most positive unsigned value supported by the compiler &/or target environment 
N*                   cannot be validated :
N*
N*                           (    N-1       N     ]
N*                           ( -(2   )  ,  2  - 1 ]
N*                           (                    ]
N*
N*                               where
N*                                       N       Number of data word bits supported by the compiler 
N*                                                   &/or target environment
N*
N*                   (a) Note that the most negative value, -2^(N-1), is NOT included in the supported 
N*                       range since many compilers do NOT always correctly handle this value.
N*
N*               (3) DEF_CHK_VAL() does NOT validate that the maximum value ('val_max') is greater than 
N*                   or equal to the minimum value ('val_min').
N*********************************************************************************************************
N*/
N
N#define  DEF_CHK_VAL(val, val_min, val_max)          (((DEF_CHK_VAL_MIN(val, val_min) == DEF_FAIL) ||                  \
N                                                       (DEF_CHK_VAL_MAX(val, val_max) == DEF_FAIL)) ? DEF_FAIL : DEF_OK)
X#define  DEF_CHK_VAL(val, val_min, val_max)          (((DEF_CHK_VAL_MIN(val, val_min) == DEF_FAIL) ||                                                                         (DEF_CHK_VAL_MAX(val, val_max) == DEF_FAIL)) ? DEF_FAIL : DEF_OK)
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                         DEF_GET_U_MAX_VAL()
N*
N* Description : Get the maximum unsigned value that can be represented in an unsigned integer variable 
N*                   of the same data type size as an object.
N*
N* Argument(s) : obj         Object or data type to return maximum unsigned value (see Note #1).
N*
N* Return(s)   : Maximum unsigned integer value that can be represented by the object, if NO error(s).
N*
N*               0,                                                                    otherwise.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) 'obj' SHOULD be an integer object or data type but COULD also be a character or 
N*                   pointer object or data type.
N*********************************************************************************************************
N*/
N
N#if     (CPU_CFG_DATA_SIZE_MAX == CPU_WORD_SIZE_08)
X#if     (8 == 1)
S
S#define  DEF_GET_U_MAX_VAL(obj)                 ((sizeof(obj) == CPU_WORD_SIZE_08) ? DEF_INT_08U_MAX_VAL : 0)
S
S
S#elif   (CPU_CFG_DATA_SIZE_MAX == CPU_WORD_SIZE_16)
X#elif   (8 == 2)
S
S#define  DEF_GET_U_MAX_VAL(obj)                 ((sizeof(obj) == CPU_WORD_SIZE_08) ? DEF_INT_08U_MAX_VAL :   \
S                                                ((sizeof(obj) == CPU_WORD_SIZE_16) ? DEF_INT_16U_MAX_VAL : 0))
X#define  DEF_GET_U_MAX_VAL(obj)                 ((sizeof(obj) == CPU_WORD_SIZE_08) ? DEF_INT_08U_MAX_VAL :                                                   ((sizeof(obj) == CPU_WORD_SIZE_16) ? DEF_INT_16U_MAX_VAL : 0))
S
S
S#elif   (CPU_CFG_DATA_SIZE_MAX == CPU_WORD_SIZE_32)
X#elif   (8 == 4)
S
S#define  DEF_GET_U_MAX_VAL(obj)                 ((sizeof(obj) == CPU_WORD_SIZE_08) ? DEF_INT_08U_MAX_VAL :    \
S                                                ((sizeof(obj) == CPU_WORD_SIZE_16) ? DEF_INT_16U_MAX_VAL :    \
S                                                ((sizeof(obj) == CPU_WORD_SIZE_32) ? DEF_INT_32U_MAX_VAL : 0)))
X#define  DEF_GET_U_MAX_VAL(obj)                 ((sizeof(obj) == CPU_WORD_SIZE_08) ? DEF_INT_08U_MAX_VAL :                                                    ((sizeof(obj) == CPU_WORD_SIZE_16) ? DEF_INT_16U_MAX_VAL :                                                    ((sizeof(obj) == CPU_WORD_SIZE_32) ? DEF_INT_32U_MAX_VAL : 0)))
S
S
N#elif   (CPU_CFG_DATA_SIZE_MAX == CPU_WORD_SIZE_64)
X#elif   (8 == 8)
N
N#define  DEF_GET_U_MAX_VAL(obj)                 ((sizeof(obj) == CPU_WORD_SIZE_08) ? DEF_INT_08U_MAX_VAL :     \
N                                                ((sizeof(obj) == CPU_WORD_SIZE_16) ? DEF_INT_16U_MAX_VAL :     \
N                                                ((sizeof(obj) == CPU_WORD_SIZE_32) ? DEF_INT_32U_MAX_VAL :     \
N                                                ((sizeof(obj) == CPU_WORD_SIZE_64) ? DEF_INT_64U_MAX_VAL : 0))))
X#define  DEF_GET_U_MAX_VAL(obj)                 ((sizeof(obj) == CPU_WORD_SIZE_08) ? DEF_INT_08U_MAX_VAL :                                                     ((sizeof(obj) == CPU_WORD_SIZE_16) ? DEF_INT_16U_MAX_VAL :                                                     ((sizeof(obj) == CPU_WORD_SIZE_32) ? DEF_INT_32U_MAX_VAL :                                                     ((sizeof(obj) == CPU_WORD_SIZE_64) ? DEF_INT_64U_MAX_VAL : 0))))
N
N#else
S
S#error  "CPU_CFG_DATA_SIZE_MAX  illegally #defined in 'cpu.h'      "
S#error  "                       [See 'cpu.h  CONFIGURATION ERRORS']"
S
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                            MATH MACRO'S
N*
N* Note(s) : (1) Ideally, ALL mathematical macro's & functions SHOULD be defined in the custom mathematics 
N*               library ('lib_math.*').  #### However, to maintain backwards compatibility with previously-
N*               released modules, mathematical macro & function definitions should only be moved to the 
N*               custom mathematics library once all previously-released modules are updated to include the 
N*               custom mathematics library.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                              DEF_MIN()
N*
N* Description : Determine the minimum of two values.
N*
N* Argument(s) : a           First  value.
N*
N*               b           Second value.
N*
N* Return(s)   : Minimum of the two values.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : none.
N*********************************************************************************************************
N*/
N
N#define  DEF_MIN(a, b)                                  (((a) < (b)) ? (a) : (b))
N
N
N/*
N*********************************************************************************************************
N*                                              DEF_MAX()
N*
N* Description : Determine the maximum of two values.
N*
N* Argument(s) : a           First  value.
N*
N*               b           Second value.
N*
N* Return(s)   : Maximum of the two values.
N*
N* Note(s)     : none.
N*********************************************************************************************************
N*/
N
N#define  DEF_MAX(a, b)                                  (((a) > (b)) ? (a) : (b))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                              DEF_ABS()
N*
N* Description : Determine the absolute value of a value.
N*
N* Argument(s) : a           Value to calculate absolute value.
N*
N* Return(s)   : Absolute value of the value.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : none.
N*********************************************************************************************************
N*/
N
N#define  DEF_ABS(a)                                     (((a) < 0) ? (-(a)) : (a))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                         FUNCTION PROTOTYPES
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                        CONFIGURATION ERRORS
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                    LIBRARY CONFIGURATION ERRORS
N*********************************************************************************************************
N*/
N
N                                                                /* See 'lib_def.h  Note #1a'.                           */
N#if     (CPU_CORE_VERSION < 12900u)
X#if     (12901u < 12900u)
S#error  "CPU_CORE_VERSION  [SHOULD be >= V1.29.00]"
N#endif
N
N
N/*
N*********************************************************************************************************
N*                                             MODULE END
N*
N* Note(s) : (1) See 'lib_def.h  MODULE'.
N*********************************************************************************************************
N*/
N
N#endif                                                          /* End of lib def module include.                       */
N
L 106 "..\..\uCOS-III\uC-CPU\cpu_core.h" 2
N#include  <cpu_cfg.h>
N
N#if (CPU_CFG_NAME_EN == DEF_ENABLED)
X#if (1u == 1u)
N#include  <lib_mem.h>
L 1 "..\..\uCOS-III\uC-LIB\lib_mem.h" 1
N/*
N*********************************************************************************************************
N*                                                uC/LIB
N*                                        CUSTOM LIBRARY MODULES
N*
N*                          (c) Copyright 2004-2012; Micrium, Inc.; Weston, FL
N*
N*               All rights reserved.  Protected by international copyright laws.
N*
N*               uC/LIB is provided in source form to registered licensees ONLY.  It is
N*               illegal to distribute this source code to any third party unless you receive
N*               written permission by an authorized Micrium representative.  Knowledge of
N*               the source code may NOT be used to develop a similar product.
N*
N*               Please help us continue to provide the Embedded community with the finest
N*               software available.  Your honesty is greatly appreciated.
N*
N*               You can contact us at www.micrium.com.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*
N*                                     STANDARD MEMORY OPERATIONS
N*
N* Filename      : lib_mem.h
N* Version       : V1.37.01
N* Programmer(s) : ITJ
N*                 FBJ
N*********************************************************************************************************
N* Note(s)       : (1) NO compiler-supplied standard library functions are used in library or product software.
N*
N*                     (a) ALL standard library functions are implemented in the custom library modules :
N*
N*                         (1) \<Custom Library Directory>\lib_*.*
N*
N*                         (2) \<Custom Library Directory>\Ports\<cpu>\<compiler>\lib*_a.*
N*
N*                               where
N*                                       <Custom Library Directory>      directory path for custom library software
N*                                       <cpu>                           directory name for specific processor (CPU)
N*                                       <compiler>                      directory name for specific compiler
N*
N*                     (b) Product-specific library functions are implemented in individual products.
N*
N*                 (2) Assumes the following versions (or more recent) of software modules are included in
N*                     the project build :
N*
N*                     (a) uC/CPU V1.27
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                               MODULE
N*
N* Note(s) : (1) This memory library header file is protected from multiple pre-processor inclusion through
N*               use of the memory library module present pre-processor macro definition.
N*********************************************************************************************************
N*/
N
N#ifndef  LIB_MEM_MODULE_PRESENT                                 /* See Note #1.                                         */
N#define  LIB_MEM_MODULE_PRESENT
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                            INCLUDE FILES
N*
N* Note(s) : (1) The custom library software files are located in the following directories :
N*
N*               (a) \<Your Product Application>\lib_cfg.h
N*
N*               (b) \<Custom Library Directory>\lib_*.*
N*
N*                       where
N*                               <Your Product Application>      directory path for Your Product's Application
N*                               <Custom Library Directory>      directory path for custom library software
N*
N*           (2) CPU-configuration  software files are located in the following directories :
N*
N*               (a) \<CPU-Compiler Directory>\cpu_*.*
N*               (b) \<CPU-Compiler Directory>\<cpu>\<compiler>\cpu*.*
N*
N*                       where
N*                               <CPU-Compiler Directory>        directory path for common CPU-compiler software
N*                               <cpu>                           directory name for specific processor (CPU)
N*                               <compiler>                      directory name for specific compiler
N*
N*           (3) Compiler MUST be configured to include as additional include path directories :
N*
N*               (a) '\<Your Product Application>\' directory                            See Note #1a
N*
N*               (b) '\<Custom Library Directory>\' directory                            See Note #1b
N*
N*               (c) (1) '\<CPU-Compiler Directory>\'                  directory         See Note #2a
N*                   (2) '\<CPU-Compiler Directory>\<cpu>\<compiler>\' directory         See Note #2b
N*
N*           (4) NO compiler-supplied standard library functions SHOULD be used.
N*********************************************************************************************************
N*/
N
N#include  <cpu.h>
N#include  <cpu_core.h>
L 1 "..\..\uCOS-III\uC-CPU\cpu_core.h" 1
N/*
N*********************************************************************************************************
N*                                                uC/CPU
N*                                    CPU CONFIGURATION & PORT LAYER
N*
N*                          (c) Copyright 2004-2011; Micrium, Inc.; Weston, FL
N*
N*               All rights reserved.  Protected by international copyright laws.
N*
N*               uC/CPU is provided in source form to registered licensees ONLY.  It is 
N*               illegal to distribute this source code to any third party unless you receive 
N*               written permission by an authorized Micrium representative.  Knowledge of 
N*               the source code may NOT be used to develop a similar product.
N*
N*               Please help us continue to provide the Embedded community with the finest 
N*               software available.  Your honesty is greatly appreciated.
N*
N*               You can contact us at www.micrium.com.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*
N*                                           CORE CPU MODULE
N*
N* Filename      : cpu_core.h
N* Version       : V1.29.01
N* Programmer(s) : SR
N*                 ITJ
N*********************************************************************************************************
N* Note(s)       : (1) Assumes the following versions (or more recent) of software modules are included in 
N*                     the project build :
N*
N*                     (a) uC/LIB V1.35.00
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                               MODULE
N*
N* Note(s) : (1) This core CPU header file is protected from multiple pre-processor inclusion through use of 
N*               the  core CPU module present pre-processor macro definition.
N*********************************************************************************************************
N*/
N
N#ifndef  CPU_CORE_MODULE_PRESENT                                /* See Note #1.                                         */
S#define  CPU_CORE_MODULE_PRESENT
S
S
S/*
S*********************************************************************************************************
S*                                               EXTERNS
S*********************************************************************************************************
S*/
S
S#ifdef   CPU_CORE_MODULE
S#define  CPU_CORE_EXT
S#else
S#define  CPU_CORE_EXT  extern
S#endif
S
S
S/*$PAGE*/
S/*
S*********************************************************************************************************
S*                                            INCLUDE FILES
S*
S* Note(s) : (1) CPU-configuration software files are located in the following directories :
S*
S*               (a) \<Your Product Application>\cpu_cfg.h
S*
S*               (b) (1) \<CPU-Compiler Directory>\cpu_*.*
S*                   (2) \<CPU-Compiler Directory>\<cpu>\<compiler>\cpu*.*
S*
S*                       where
S*                               <Your Product Application>      directory path for Your Product's Application
S*                               <CPU-Compiler Directory>        directory path for common CPU-compiler software
S*                               <cpu>                           directory name for specific processor (CPU)
S*                               <compiler>                      directory name for specific compiler
S*
S*           (2) NO compiler-supplied standard library functions SHOULD be used.
S*
S*               (a) Standard library functions are implemented in the custom library module(s) :
S*
S*                       \<Custom Library Directory>\lib_*.*
S*
S*                           where
S*                                   <Custom Library Directory>      directory path for custom library software
S*
S*           (3) Compiler MUST be configured to include as additional include path directories :
S*
S*               (a) '\<Your Product Application>\' directory                            See Note #1a
S*
S*               (b) (1) '\<CPU-Compiler Directory>\'                  directory         See Note #1b1
S*                   (2) '\<CPU-Compiler Directory>\<cpu>\<compiler>\' directory         See Note #1b2
S*
S*               (c) '\<Custom Library Directory>\' directory                            See Note #2a
S*********************************************************************************************************
S*/
S
S#include  <cpu.h>
S#include  <lib_def.h>
S#include  <cpu_cfg.h>
S
S#if (CPU_CFG_NAME_EN == DEF_ENABLED)
S#include  <lib_mem.h>
S#include  <lib_str.h>
S#endif
S
S
S/*$PAGE*/
S/*
S*********************************************************************************************************
S*                                          CPU CONFIGURATION
S*
S* Note(s) : (1) The following pre-processor directives correctly configure CPU parameters.  DO NOT MODIFY.
S*
S*           (2) CPU timestamp timer feature is required for :
S*
S*               (a) CPU timestamps
S*               (b) CPU interrupts disabled time measurement
S*
S*               See also 'cpu_cfg.h  CPU TIMESTAMP CONFIGURATION  Note #1'
S*                      & 'cpu_cfg.h  CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION  Note #1'.
S*********************************************************************************************************
S*/
S
S#ifdef   CPU_CFG_TS_EN
S#undef   CPU_CFG_TS_EN
S#endif
S
S
S#if    ((CPU_CFG_TS_32_EN == DEF_ENABLED) || \
S        (CPU_CFG_TS_64_EN == DEF_ENABLED))
X#if    ((CPU_CFG_TS_32_EN == DEF_ENABLED) ||         (CPU_CFG_TS_64_EN == DEF_ENABLED))
S#define  CPU_CFG_TS_EN                          DEF_ENABLED
S#else
S#define  CPU_CFG_TS_EN                          DEF_DISABLED
S#endif
S
S#if    ((CPU_CFG_TS_EN == DEF_ENABLED) || \
S(defined(CPU_CFG_INT_DIS_MEAS_EN)))
X#if    ((CPU_CFG_TS_EN == DEF_ENABLED) || (defined(CPU_CFG_INT_DIS_MEAS_EN)))
S#define  CPU_CFG_TS_TMR_EN                      DEF_ENABLED
S#else
S#define  CPU_CFG_TS_TMR_EN                      DEF_DISABLED
S#endif
S
S
S/*
S*********************************************************************************************************
S*                                               DEFINES
S*********************************************************************************************************
S*/
S
S#define  CPU_TIME_MEAS_NBR_MIN                             1u
S#define  CPU_TIME_MEAS_NBR_MAX                           128u
S
S
S/*$PAGE*/
S/*
S*********************************************************************************************************
S*                                             DATA TYPES
S*********************************************************************************************************
S*/
S
S
S/*
S*********************************************************************************************************
S*                                           CPU ERROR CODES
S*********************************************************************************************************
S*/
S
Stypedef enum cpu_err {
S
S    CPU_ERR_NONE                            =         0u,
S    CPU_ERR_NULL_PTR                        =        10u,
S
S    CPU_ERR_NAME_SIZE                       =      1000u,
S
S    CPU_ERR_TS_FREQ_INVALID                 =      2000u
S
S} CPU_ERR;
S
S
S/*
S*********************************************************************************************************
S*                                      CPU TIMESTAMP DATA TYPES
S*
S* Note(s) : (1) CPU timestamp timer data type defined to the binary-multiple of 8-bit octets as configured 
S*               by 'CPU_CFG_TS_TMR_SIZE' (see 'cpu_cfg.h  CPU TIMESTAMP CONFIGURATION  Note #2').
S*********************************************************************************************************
S*/
S
Stypedef  CPU_INT32U  CPU_TS32;
Stypedef  CPU_INT64U  CPU_TS64;
S
Stypedef  CPU_TS32    CPU_TS;                                    /* Req'd for backwards-compatibility.                   */
S
S
S#if     (CPU_CFG_TS_TMR_EN   == DEF_ENABLED)                    /* CPU ts tmr defined to cfg'd word size (see Note #1). */
S#if     (CPU_CFG_TS_TMR_SIZE == CPU_WORD_SIZE_08)
Stypedef  CPU_INT08U  CPU_TS_TMR;
S#elif   (CPU_CFG_TS_TMR_SIZE == CPU_WORD_SIZE_16)
Stypedef  CPU_INT16U  CPU_TS_TMR;
S#elif   (CPU_CFG_TS_TMR_SIZE == CPU_WORD_SIZE_64)
Stypedef  CPU_INT64U  CPU_TS_TMR;
S#else                                                           /* CPU ts tmr dflt size = 32-bits.                      */
Stypedef  CPU_INT32U  CPU_TS_TMR;
S#endif
S#endif
S
S
S/*
S*********************************************************************************************************
S*                               CPU TIMESTAMP TIMER FREQUENCY DATA TYPE
S*********************************************************************************************************
S*/
S
Stypedef  CPU_INT32U  CPU_TS_TMR_FREQ;
S
S
S/*
S*********************************************************************************************************
S*                                          GLOBAL VARIABLES
S*********************************************************************************************************
S*/
S
S#if    (CPU_CFG_NAME_EN   == DEF_ENABLED)
SCPU_CORE_EXT  CPU_CHAR         CPU_Name[CPU_CFG_NAME_SIZE];     /* CPU host name.                                       */
S#endif
S
S
S#if ((CPU_CFG_TS_32_EN    == DEF_ENABLED)  && \
S     (CPU_CFG_TS_TMR_SIZE <  CPU_WORD_SIZE_32))
X#if ((CPU_CFG_TS_32_EN    == DEF_ENABLED)  &&      (CPU_CFG_TS_TMR_SIZE <  CPU_WORD_SIZE_32))
SCPU_CORE_EXT  CPU_TS32         CPU_TS_32_Accum;                 /* 32-bit accum'd ts  (in ts tmr cnts).                 */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_TS_32_TmrPrev;               /* 32-bit ts prev tmr (in ts tmr cnts).                 */
S#endif
S
S#if ((CPU_CFG_TS_64_EN    == DEF_ENABLED)  && \
S     (CPU_CFG_TS_TMR_SIZE <  CPU_WORD_SIZE_64))
X#if ((CPU_CFG_TS_64_EN    == DEF_ENABLED)  &&      (CPU_CFG_TS_TMR_SIZE <  CPU_WORD_SIZE_64))
SCPU_CORE_EXT  CPU_TS64         CPU_TS_64_Accum;                 /* 64-bit accum'd ts  (in ts tmr cnts).                 */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_TS_64_TmrPrev;               /* 64-bit ts prev tmr (in ts tmr cnts).                 */
S#endif
S
S#if  (CPU_CFG_TS_TMR_EN   == DEF_ENABLED)
SCPU_CORE_EXT  CPU_TS_TMR_FREQ  CPU_TS_TmrFreq_Hz;               /* CPU ts tmr freq (in Hz).                             */
S#endif
S
S
S#ifdef  CPU_CFG_INT_DIS_MEAS_EN
SCPU_CORE_EXT  CPU_INT16U       CPU_IntDisMeasCtr;               /* Nbr tot    ints dis'd ctr.                           */
SCPU_CORE_EXT  CPU_INT16U       CPU_IntDisNestCtr;               /* Nbr nested ints dis'd ctr.                           */
S                                                                /* Ints dis'd time (in ts tmr cnts) : ...               */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_IntDisMeasStart_cnts;        /* ...  start time.                                     */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_IntDisMeasStop_cnts;         /* ...  stop  time.                                     */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_IntDisMeasOvrhd_cnts;        /* ...        time meas ovrhd.                          */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_IntDisMeasMaxCur_cnts;       /* ...     resetable max time dis'd.                    */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_IntDisMeasMax_cnts;          /* ... non-resetable max time dis'd.                    */
S#endif
S
S
S/*$PAGE*/
S/*
S*********************************************************************************************************
S*                                               MACRO'S
S*********************************************************************************************************
S*/
S
S/*
S*********************************************************************************************************
S*                                         CPU_SW_EXCEPTION()
S*
S* Description : Trap unrecoverable software exception.
S*
S* Argument(s) : err_rtn_val     Error type &/or value of the calling function to return (see Note #2b).
S*
S* Return(s)   : none.
S*
S* Caller(s)   : various.
S*
S* Note(s)     : (1) CPU_SW_EXCEPTION() deadlocks the current code execution -- whether multi-tasked/
S*                   -processed/-threaded or single-threaded -- when the current code execution cannot 
S*                   gracefully recover or report a fault or exception condition.
S*
S*                   Example CPU_SW_EXCEPTION() call :
S*
S*                       void  Fnct (CPU_ERR  *p_err)
S*                       {
S*                           :
S*
S*                           if (p_err == (CPU_ERR *)0) {        If 'p_err' NULL, cannot return error ...
S*                               CPU_SW_EXCEPTION(;);            ... so trap invalid argument exception.
S*                           }
S*
S*                           :
S*                       }
S*
S*                   See also 'cpu_core.c  CPU_SW_Exception()  Note #1'.
S*
S*               (2) (a) CPU_SW_EXCEPTION()  MAY be developer-implemented to output &/or handle any error or 
S*                       exception conditions; but since CPU_SW_EXCEPTION() is intended to trap unrecoverable 
S*                       software  conditions, it is recommended that developer-implemented versions prevent 
S*                       execution of any code following calls to CPU_SW_EXCEPTION() by deadlocking the code 
S*                       (see Note #1).
S*
S*                           Example CPU_SW_EXCEPTION() :
S*
S*                               #define  CPU_SW_EXCEPTION(err_rtn_val)      do {                         \
S*                                                                               Log(__FILE__, __LINE__); \
S*                                                                               CPU_SW_Exception();      \
S*                                                                           } while (0)
X
S*
S*                   (b) (1) However, if execution of code following calls to CPU_SW_EXCEPTION() is required 
S*                           (e.g. for automated testing); it is recommended that the last statement in 
S*                           developer-implemented versions be to return from the current function to prevent 
S*                           possible software exception(s) in the current function from triggering CPU &/or 
S*                           hardware exception(s).
S*
S*                           Example CPU_SW_EXCEPTION() :
S*
S*                               #define  CPU_SW_EXCEPTION(err_rtn_val)      do {                         \
S*                                                                               Log(__FILE__, __LINE__); \
S*                                                                               return  err_rtn_val;     \
S*                                                                           } while (0)
X
S*
S*                           (A) Note that 'err_rtn_val' in the return statement MUST NOT be enclosed in 
S*                               parentheses.  This allows CPU_SW_EXCEPTION() to return from functions that 
S*                               return 'void', i.e. NO return type or value (see also Note #2b2A).
S*$PAGE*
S*                       (2) In order for CPU_SW_EXCEPTION() to return from functions with various return 
S*                           types/values, each caller function MUST pass an appropriate error return type 
S*                           & value to CPU_SW_EXCEPTION().
S*
S*                           (A) Note that CPU_SW_EXCEPTION()  MUST NOT be passed any return type or value 
S*                               for functions that return 'void', i.e. NO return type or value; but SHOULD 
S*                               instead be passed a single semicolon.  This prevents possible compiler 
S*                               warnings that CPU_SW_EXCEPTION() is passed too few arguments.  However, 
S*                               the compiler may warn that CPU_SW_EXCEPTION() does NOT prevent creating 
S*                               null statements on lines with NO other code statements.
S*
S*                           Example CPU_SW_EXCEPTION() calls :
S*
S*                               void  Fnct (CPU_ERR  *p_err)
S*                               {
S*                                   :
S*
S*                                   if (p_err == (CPU_ERR *)0) {
S*                                       CPU_SW_EXCEPTION(;);            Exception macro returns NO value
S*                                   }                                       (see Note #2b2A)
S*
S*                                   :
S*                               }
S*
S*                               CPU_BOOLEAN  Fnct (CPU_ERR  *p_err)
S*                               {
S*                                   :
S*
S*                                   if (p_err == (CPU_ERR *)0) {
S*                                       CPU_SW_EXCEPTION(DEF_FAIL);     Exception macro returns 'DEF_FAIL'
S*                                   }
S*
S*                                   :
S*                               }
S*
S*                               OBJ  *Fnct (CPU_ERR  *p_err)
S*                               {
S*                                   :
S*
S*                                   if (p_err == (CPU_ERR *)0) {
S*                                       CPU_SW_EXCEPTION((OBJ *)0);     Exception macro returns NULL 'OBJ *'
S*                                   }
S*
S*                                   :
S*                               }
S*
S*********************************************************************************************************
S*/
S
S#ifndef  CPU_SW_EXCEPTION                                                       /* See Note #2.                         */
S#define  CPU_SW_EXCEPTION(err_rtn_val)              do {                    \
S                                                        CPU_SW_Exception(); \
S                                                    } while (0)
X#define  CPU_SW_EXCEPTION(err_rtn_val)              do {                                                                            CPU_SW_Exception();                                                     } while (0)
S#endif
S
S
S/*$PAGE*/
S/*
S*********************************************************************************************************
S*                                           CPU_VAL_UNUSED()
S*
S* Description : 
S*
S* Argument(s) : none.
S*
S* Return(s)   : none.
S*
S* Caller(s)   : #### various.
S*
S* Note(s)     : none.
S*********************************************************************************************************
S*/
S
S
S#define  CPU_VAL_UNUSED(val)        ((void)&(val));
S
S
S#define  CPU_VAL_IGNORED(val)       CPU_VAL_UNUSED(val)
S
S
S/*$PAGE*/
S/*
S*********************************************************************************************************
S*                                          CPU_TYPE_CREATE()
S*
S* Description : Creates a generic type value.
S*
S* Argument(s) : char_1      1st ASCII character to create generic type value.
S*
S*               char_2      2nd ASCII character to create generic type value.
S*
S*               char_3      3rd ASCII character to create generic type value.
S*
S*               char_4      4th ASCII character to create generic type value.
S*
S* Return(s)   : 32-bit generic type value.
S*
S* Caller(s)   : various.
S*
S* Note(s)     : (1) (a) Generic type values should be #define'd with large, non-trivial values to trap 
S*                       & discard invalid/corrupted objects based on type value.
S*
S*                       In other words, by assigning large, non-trivial values to valid objects' type 
S*                       fields; the likelihood that an object with an unassigned &/or corrupted type 
S*                       field will contain a value is highly improbable & therefore the object itself 
S*                       will be trapped as invalid.
S*
S*                   (b) (1) CPU_TYPE_CREATE()  creates a 32-bit type value from four values.
S*
S*                       (2) Ideally, generic type values SHOULD be created from 'CPU_CHAR' characters to 
S*                           represent ASCII string abbreviations of the specific object types.  Memory 
S*                           displays of object type values will display the specific object types with 
S*                           their chosen ASCII names.
S*
S*                           Examples :
S*
S*                               #define  FILE_TYPE  CPU_TYPE_CREATE('F', 'I', 'L', 'E')
S*                               #define  BUF_TYPE   CPU_TYPE_CREATE('B', 'U', 'F', ' ')
S*********************************************************************************************************
S*/
S
S#if     (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
S#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (3u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_2)) << (2u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_3)) << (1u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_4)) << (0u * DEF_OCTET_NBR_BITS)))
X#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (3u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_2)) << (2u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_3)) << (1u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_4)) << (0u * DEF_OCTET_NBR_BITS)))
S
S#else
S
S#if    ((CPU_CFG_DATA_SIZE   == CPU_WORD_SIZE_64) || \
S        (CPU_CFG_DATA_SIZE   == CPU_WORD_SIZE_32))
X#if    ((CPU_CFG_DATA_SIZE   == CPU_WORD_SIZE_64) ||         (CPU_CFG_DATA_SIZE   == CPU_WORD_SIZE_32))
S#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (0u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_2)) << (1u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_3)) << (2u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_4)) << (3u * DEF_OCTET_NBR_BITS)))
X#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (0u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_2)) << (1u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_3)) << (2u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_4)) << (3u * DEF_OCTET_NBR_BITS)))
S
S
S#elif   (CPU_CFG_DATA_SIZE   == CPU_WORD_SIZE_16)
S#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (2u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_2)) << (3u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_3)) << (0u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_4)) << (1u * DEF_OCTET_NBR_BITS)))
X#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (2u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_2)) << (3u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_3)) << (0u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_4)) << (1u * DEF_OCTET_NBR_BITS)))
S
S#else                                                           /* Dflt CPU_WORD_SIZE_08.                               */
S#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (3u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_2)) << (2u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_3)) << (1u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_4)) << (0u * DEF_OCTET_NBR_BITS)))
X#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (3u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_2)) << (2u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_3)) << (1u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_4)) << (0u * DEF_OCTET_NBR_BITS)))
S#endif
S#endif
S
S
S/*$PAGE*/
S/*
S*********************************************************************************************************
S*                                         FUNCTION PROTOTYPES
S*
S* Note(s) : (1) CPU interrupts disabled time measurement functions prototyped/defined only if 
S*               CPU_CFG_INT_DIS_MEAS_EN  #define'd in 'cpu_cfg.h'.
S*
S*           (2) (a) CPU_CntLeadZeros()  defined in :
S*
S*                   (1) 'cpu_a.asm',  if CPU_CFG_LEAD_ZEROS_ASM_PRESENT       #define'd in 'cpu.h'/
S*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
S*
S*                   (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT   NOT #define'd in 'cpu.h'/
S*                                         'cpu_cfg.h' to enable C-source-optimized function(s)
S*
S*               (b) CPU_CntTrailZeros() defined in :
S*
S*                   (1) 'cpu_a.asm',  if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT      #define'd in 'cpu.h'/
S*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
S*
S*                   (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT  NOT #define'd in 'cpu.h'/
S*                                         'cpu_cfg.h' to enable C-source-optimized function(s)
S*********************************************************************************************************
S*/
S
Svoid             CPU_Init                 (void);
S
Svoid             CPU_SW_Exception         (void);
S
S
S
S#if (CPU_CFG_NAME_EN == DEF_ENABLED)                                    /* -------------- CPU NAME FNCTS -------------- */
Svoid             CPU_NameClr              (void);
S
Svoid             CPU_NameGet              (       CPU_CHAR  *p_name,
S                                                  CPU_ERR   *p_err);
S
Svoid             CPU_NameSet              (const  CPU_CHAR  *p_name,
S                                                  CPU_ERR   *p_err);
S#endif
S
S
S
S                                                                        /* --------------- CPU TS FNCTS --------------- */
S#if (CPU_CFG_TS_32_EN == DEF_ENABLED)
SCPU_TS32         CPU_TS_Get32             (void);
S#endif
S
S#if (CPU_CFG_TS_64_EN == DEF_ENABLED)
SCPU_TS64         CPU_TS_Get64             (void);
S#endif
S
S#if (CPU_CFG_TS_EN    == DEF_ENABLED)
Svoid             CPU_TS_Update            (void);
S#endif
S
S
S#if (CPU_CFG_TS_TMR_EN == DEF_ENABLED)                                  /* ------------- CPU TS TMR FNCTS ------------- */
SCPU_TS_TMR_FREQ  CPU_TS_TmrFreqGet        (CPU_ERR          *p_err);
S
Svoid             CPU_TS_TmrFreqSet        (CPU_TS_TMR_FREQ   freq_hz);
S#endif
S
S
S
S#ifdef  CPU_CFG_INT_DIS_MEAS_EN                                         /* -------- CPU INT DIS TIME MEAS FNCTS ------- */
S                                                                        /* See Note #1.                                 */
SCPU_TS_TMR       CPU_IntDisMeasMaxCurReset(void);
S
SCPU_TS_TMR       CPU_IntDisMeasMaxCurGet  (void);
S
SCPU_TS_TMR       CPU_IntDisMeasMaxGet     (void);
S
S
Svoid             CPU_IntDisMeasStart      (void);
S
Svoid             CPU_IntDisMeasStop       (void);
S#endif
S
S
S
S                                                                        /* ----------- CPU CNT ZEROS FNCTS ------------ */
SCPU_DATA         CPU_CntLeadZeros         (CPU_DATA    val);
S
S#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_08)
SCPU_DATA         CPU_CntLeadZeros08       (CPU_INT08U  val);
S#endif
S#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_16)
SCPU_DATA         CPU_CntLeadZeros16       (CPU_INT16U  val);
S#endif
S#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_32)
SCPU_DATA         CPU_CntLeadZeros32       (CPU_INT32U  val);
S#endif
S#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_64)
SCPU_DATA         CPU_CntLeadZeros64       (CPU_INT64U  val);
S#endif
S
S
SCPU_DATA         CPU_CntTrailZeros        (CPU_DATA    val);
S
S#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_08)
SCPU_DATA         CPU_CntTrailZeros08      (CPU_INT08U  val);
S#endif
S#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_16)
SCPU_DATA         CPU_CntTrailZeros16      (CPU_INT16U  val);
S#endif
S#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_32)
SCPU_DATA         CPU_CntTrailZeros32      (CPU_INT32U  val);
S#endif
S#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_64)
SCPU_DATA         CPU_CntTrailZeros64      (CPU_INT64U  val);
S#endif
S
S
S/*$PAGE*/
S/*
S*********************************************************************************************************
S*                                         FUNCTION PROTOTYPES
S*                                      DEFINED IN PRODUCT'S BSP
S*********************************************************************************************************
S*/
S
S/*
S*********************************************************************************************************
S*                                          CPU_TS_TmrInit()
S*
S* Description : Initialize & start CPU timestamp timer.
S*
S* Argument(s) : none.
S*
S* Return(s)   : none.
S*
S* Caller(s)   : CPU_TS_Init().
S*
S*               This function is an INTERNAL CPU module function & MUST be implemented by application/
S*               BSP function(s) [see Note #1] but MUST NOT be called by application function(s).
S*
S* Note(s)     : (1) CPU_TS_TmrInit() is an application/BSP function that MUST be defined by the developer 
S*                   if either of the following CPU features is enabled :
S*
S*                   (a) CPU timestamps
S*                   (b) CPU interrupts disabled time measurements
S*
S*                   See 'cpu_cfg.h  CPU TIMESTAMP CONFIGURATION  Note #1'
S*                     & 'cpu_cfg.h  CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION  Note #1a'.
S*
S*               (2) (a) Timer count values MUST be returned via word-size-configurable 'CPU_TS_TMR' 
S*                       data type.
S*
S*                       (1) If timer has more bits, truncate timer values' higher-order bits greater 
S*                           than the configured 'CPU_TS_TMR' timestamp timer data type word size.
S*
S*                       (2) Since the timer MUST NOT have less bits than the configured 'CPU_TS_TMR' 
S*                           timestamp timer data type word size; 'CPU_CFG_TS_TMR_SIZE' MUST be 
S*                           configured so that ALL bits in 'CPU_TS_TMR' data type are significant.
S*
S*                           In other words, if timer size is not a binary-multiple of 8-bit octets 
S*                           (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple 
S*                           octet word size SHOULD be configured (e.g. to 16-bits).  However, the 
S*                           minimum supported word size for CPU timestamp timers is 8-bits.
S*
S*                       See also 'cpu_cfg.h   CPU TIMESTAMP CONFIGURATION  Note #2'
S*                              & 'cpu_core.h  CPU TIMESTAMP DATA TYPES     Note #1'.
S*
S*                   (b) Timer SHOULD be an 'up'  counter whose values increase with each time count.
S*
S*                   (c) When applicable, timer period SHOULD be less than the typical measured time 
S*                       but MUST be less than the maximum measured time; otherwise, timer resolution 
S*                       inadequate to measure desired times.
S*
S*                   See also 'CPU_TS_TmrRd()  Note #2'.
S*********************************************************************************************************
S*/
S
S#if (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
Svoid  CPU_TS_TmrInit(void);
S#endif
S
S
S/*$PAGE*/
S/*
S*********************************************************************************************************
S*                                           CPU_TS_TmrRd()
S*
S* Description : Get current CPU timestamp timer count value.
S*
S* Argument(s) : none.
S*
S* Return(s)   : Timestamp timer count (see Notes #2a & #2b).
S*
S* Caller(s)   : CPU_TS_Init(),
S*               CPU_TS_Get32(),
S*               CPU_TS_Get64(),
S*               CPU_IntDisMeasStart(),
S*               CPU_IntDisMeasStop().
S*
S*               This function is an INTERNAL CPU module function & MUST be implemented by application/
S*               BSP function(s) [see Note #1] but SHOULD NOT be called by application function(s).
S*
S* Note(s)     : (1) CPU_TS_TmrRd() is an application/BSP function that MUST be defined by the developer 
S*                   if either of the following CPU features is enabled :
S*
S*                   (a) CPU timestamps
S*                   (b) CPU interrupts disabled time measurements
S*
S*                   See 'cpu_cfg.h  CPU TIMESTAMP CONFIGURATION  Note #1'
S*                     & 'cpu_cfg.h  CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION  Note #1a'.
S*
S*               (2) (a) Timer count values MUST be returned via word-size-configurable 'CPU_TS_TMR' 
S*                       data type.
S*
S*                       (1) If timer has more bits, truncate timer values' higher-order bits greater 
S*                           than the configured 'CPU_TS_TMR' timestamp timer data type word size.
S*
S*                       (2) Since the timer MUST NOT have less bits than the configured 'CPU_TS_TMR' 
S*                           timestamp timer data type word size; 'CPU_CFG_TS_TMR_SIZE' MUST be 
S*                           configured so that ALL bits in 'CPU_TS_TMR' data type are significant.
S*
S*                           In other words, if timer size is not a binary-multiple of 8-bit octets 
S*                           (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple 
S*                           octet word size SHOULD be configured (e.g. to 16-bits).  However, the 
S*                           minimum supported word size for CPU timestamp timers is 8-bits.
S*
S*                       See also 'cpu_cfg.h   CPU TIMESTAMP CONFIGURATION  Note #2'
S*                              & 'cpu_core.h  CPU TIMESTAMP DATA TYPES     Note #1'.
S*
S*                   (b) Timer SHOULD be an 'up'  counter whose values increase with each time count.
S*
S*                       (1) If timer is a 'down' counter whose values decrease with each time count,
S*                           then the returned timer value MUST be ones-complemented.
S*
S*                   (c) (1) When applicable, the amount of time measured by CPU timestamps is 
S*                           calculated by either of the following equations :
S*
S*                           (A) Time measured  =  Number timer counts  *  Timer period
S*
S*                                   where
S*
S*                                       Number timer counts     Number of timer counts measured 
S*                                       Timer period            Timer's period in some units of 
S*                                                                   (fractional) seconds
S*                                       Time measured           Amount of time measured, in same 
S*                                                                   units of (fractional) seconds 
S*                                                                   as the Timer period
S*
S*                                                  Number timer counts
S*                           (B) Time measured  =  ---------------------
S*                                                    Timer frequency
S*
S*                                   where
S*
S*                                       Number timer counts     Number of timer counts measured
S*                                       Timer frequency         Timer's frequency in some units 
S*                                                                   of counts per second
S*                                       Time measured           Amount of time measured, in seconds
S*
S*                       (2) Timer period SHOULD be less than the typical measured time but MUST be less 
S*                           than the maximum measured time; otherwise, timer resolution inadequate to 
S*                           measure desired times.
S*********************************************************************************************************
S*/
S
S#if (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
SCPU_TS_TMR  CPU_TS_TmrRd(void);
S#endif
S
S
S/*$PAGE*/
S/*
S*********************************************************************************************************
S*                                         CPU_TSxx_to_uSec()
S*
S* Description : Convert a 32-/64-bit CPU timestamp from timer counts to microseconds.
S*
S* Argument(s) : ts_cnts   CPU timestamp (in timestamp timer counts [see Note #2aA]).
S*
S* Return(s)   : Converted CPU timestamp (in microseconds           [see Note #2aD]).
S*
S* Caller(s)   : Application.
S*
S*               This function is an (optional) CPU module application programming interface (API) 
S*               function which MAY be implemented by application/BSP function(s) [see Note #1] & 
S*               MAY be called by application function(s).
S*
S* Note(s)     : (1) CPU_TS32_to_uSec()/CPU_TS64_to_uSec() are application/BSP functions that MAY be 
S*                   optionally defined by the developer when either of the following CPU features is 
S*                   enabled :
S*
S*                   (a) CPU timestamps
S*                   (b) CPU interrupts disabled time measurements
S*
S*                   See 'cpu_cfg.h  CPU TIMESTAMP CONFIGURATION  Note #1'
S*                     & 'cpu_cfg.h  CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION  Note #1a'.
S*
S*               (2) (a) The amount of time measured by CPU timestamps is calculated by either of 
S*                       the following equations :
S*
S*                                                                        10^6 microseconds
S*                       (1) Time measured  =   Number timer counts   *  -------------------  *  Timer period
S*                                                                            1 second
S*
S*                                              Number timer counts       10^6 microseconds
S*                       (2) Time measured  =  ---------------------  *  -------------------
S*                                                Timer frequency             1 second
S*
S*                               where
S*
S*                                   (A) Number timer counts     Number of timer counts measured
S*                                   (B) Timer frequency         Timer's frequency in some units 
S*                                                                   of counts per second
S*                                   (C) Timer period            Timer's period in some units of 
S*                                                                   (fractional)  seconds
S*                                   (D) Time measured           Amount of time measured, 
S*                                                                   in microseconds
S*
S*                   (b) Timer period SHOULD be less than the typical measured time but MUST be less 
S*                       than the maximum measured time; otherwise, timer resolution inadequate to 
S*                       measure desired times.
S*
S*                   (c) Specific implementations may convert any number of CPU_TS32 or CPU_TS64 bits 
S*                       -- up to 32 or 64, respectively -- into microseconds.
S*********************************************************************************************************
S*/
S
S#if (CPU_CFG_TS_32_EN == DEF_ENABLED)
SCPU_INT64U  CPU_TS32_to_uSec(CPU_TS32  ts_cnts);
S#endif
S
S#if (CPU_CFG_TS_64_EN == DEF_ENABLED)
SCPU_INT64U  CPU_TS64_to_uSec(CPU_TS64  ts_cnts);
S#endif
S
S
S/*$PAGE*/
S/*
S*********************************************************************************************************
S*                                        CONFIGURATION ERRORS
S*********************************************************************************************************
S*/
S
S#ifndef  CPU_CFG_NAME_EN
S#error  "CPU_CFG_NAME_EN                       not #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  DEF_ENABLED ]           "
S#error  "                                [     ||  DEF_DISABLED]           "
S
S#elif  ((CPU_CFG_NAME_EN != DEF_ENABLED ) && \
S        (CPU_CFG_NAME_EN != DEF_DISABLED))
X#elif  ((CPU_CFG_NAME_EN != DEF_ENABLED ) &&         (CPU_CFG_NAME_EN != DEF_DISABLED))
S#error  "CPU_CFG_NAME_EN                 illegally #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  DEF_ENABLED ]           "
S#error  "                                [     ||  DEF_DISABLED]           "
S
S
S#elif   (CPU_CFG_NAME_EN == DEF_ENABLED)
S
S#ifndef  CPU_CFG_NAME_SIZE
S#error  "CPU_CFG_NAME_SIZE                     not #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  >=   1]                 "
S#error  "                                [     &&  <= 255]                 "
S
S#elif   (DEF_CHK_VAL(CPU_CFG_NAME_SIZE,            \
S                     1,                            \
S                     DEF_INT_08U_MAX_VAL) != DEF_OK)
X#elif   (DEF_CHK_VAL(CPU_CFG_NAME_SIZE,                                 1,                                                 DEF_INT_08U_MAX_VAL) != DEF_OK)
S#error  "CPU_CFG_NAME_SIZE               illegally #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  >=   1]                 "
S#error  "                                [     &&  <= 255]                 "
S#endif
S
S#endif
S
S
S
S
S#ifndef  CPU_CFG_TS_32_EN
S#error  "CPU_CFG_TS_32_EN                      not #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  DEF_DISABLED]           "
S#error  "                                [     ||  DEF_ENABLED ]           "
S
S#elif  ((CPU_CFG_TS_32_EN != DEF_DISABLED) && \
S        (CPU_CFG_TS_32_EN != DEF_ENABLED ))
X#elif  ((CPU_CFG_TS_32_EN != DEF_DISABLED) &&         (CPU_CFG_TS_32_EN != DEF_ENABLED ))
S#error  "CPU_CFG_TS_32_EN                illegally #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  DEF_DISABLED]           "
S#error  "                                [     ||  DEF_ENABLED ]           "
S
S#endif
S
S
S#ifndef  CPU_CFG_TS_64_EN
S#error  "CPU_CFG_TS_64_EN                      not #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  DEF_DISABLED]           "
S#error  "                                [     ||  DEF_ENABLED ]           "
S
S#elif  ((CPU_CFG_TS_64_EN != DEF_DISABLED) && \
S        (CPU_CFG_TS_64_EN != DEF_ENABLED ))
X#elif  ((CPU_CFG_TS_64_EN != DEF_DISABLED) &&         (CPU_CFG_TS_64_EN != DEF_ENABLED ))
S#error  "CPU_CFG_TS_64_EN                illegally #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  DEF_DISABLED]           "
S#error  "                                [     ||  DEF_ENABLED ]           "
S
S#endif
S
S                                                                /* Correctly configured in 'cpu_core.h'; DO NOT MODIFY. */
S#ifndef  CPU_CFG_TS_EN
S#error  "CPU_CFG_TS_EN                         not #define'd in 'cpu_core.h'"
S#error  "                                [MUST be  DEF_DISABLED]            "
S#error  "                                [     ||  DEF_ENABLED ]            "
S
S#elif  ((CPU_CFG_TS_EN != DEF_DISABLED) && \
S        (CPU_CFG_TS_EN != DEF_ENABLED ))
X#elif  ((CPU_CFG_TS_EN != DEF_DISABLED) &&         (CPU_CFG_TS_EN != DEF_ENABLED ))
S#error  "CPU_CFG_TS_EN                   illegally #define'd in 'cpu_core.h'"
S#error  "                                [MUST be  DEF_DISABLED]            "
S#error  "                                [     ||  DEF_ENABLED ]            "
S
S#endif
S
S
S/*$PAGE*/
S                                                                /* Correctly configured in 'cpu_core.h'; DO NOT MODIFY. */
S#ifndef  CPU_CFG_TS_TMR_EN
S#error  "CPU_CFG_TS_TMR_EN                     not #define'd in 'cpu_core.h'"
S#error  "                                [MUST be  DEF_DISABLED]            "
S#error  "                                [     ||  DEF_ENABLED ]            "
S
S#elif  ((CPU_CFG_TS_TMR_EN != DEF_DISABLED) && \
S        (CPU_CFG_TS_TMR_EN != DEF_ENABLED ))
X#elif  ((CPU_CFG_TS_TMR_EN != DEF_DISABLED) &&         (CPU_CFG_TS_TMR_EN != DEF_ENABLED ))
S#error  "CPU_CFG_TS_TMR_EN               illegally #define'd in 'cpu_core.h'"
S#error  "                                [MUST be  DEF_DISABLED]            "
S#error  "                                [     ||  DEF_ENABLED ]            "
S
S
S#elif   (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
S
S#ifndef  CPU_CFG_TS_TMR_SIZE
S#error  "CPU_CFG_TS_TMR_SIZE                   not #define'd in 'cpu_cfg.h'       "
S#error  "                                [MUST be  CPU_WORD_SIZE_08   8-bit timer]"
S#error  "                                [     ||  CPU_WORD_SIZE_16  16-bit timer]"
S#error  "                                [     ||  CPU_WORD_SIZE_32  32-bit timer]"
S#error  "                                [     ||  CPU_WORD_SIZE_64  64-bit timer]"
S
S#elif  ((CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_08) && \
S        (CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_16) && \
S        (CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_32) && \
S        (CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_64))
X#elif  ((CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_08) &&         (CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_16) &&         (CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_32) &&         (CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_64))
S#error  "CPU_CFG_TS_TMR_SIZE             illegally #define'd in 'cpu_cfg.h'       "
S#error  "                                [MUST be  CPU_WORD_SIZE_08   8-bit timer]"
S#error  "                                [     ||  CPU_WORD_SIZE_16  16-bit timer]"
S#error  "                                [     ||  CPU_WORD_SIZE_32  32-bit timer]"
S#error  "                                [     ||  CPU_WORD_SIZE_64  64-bit timer]"
S#endif
S
S#endif
S
S
S
S#ifndef  CPU_CFG_INT_DIS_MEAS_EN
S#if 0                                                           /* Optionally configured in 'cpu_cfg.h'; DO NOT MODIFY. */
S#error  "CPU_CFG_INT_DIS_MEAS_EN               not #define'd in 'cpu_cfg.h'"
S#endif
S
S#else
S
S#ifndef  CPU_CFG_INT_DIS_MEAS_OVRHD_NBR
S#error  "CPU_CFG_INT_DIS_MEAS_OVRHD_NBR        not #define'd in 'cpu_cfg.h' "
S#error  "                                [MUST be  >= CPU_TIME_MEAS_NBR_MIN]"
S#error  "                                [     ||  <= CPU_TIME_MEAS_NBR_MAX]"
S
S#elif   (DEF_CHK_VAL(CPU_CFG_INT_DIS_MEAS_OVRHD_NBR, \
S                     CPU_TIME_MEAS_NBR_MIN,          \
S                     CPU_TIME_MEAS_NBR_MAX) != DEF_OK)
X#elif   (DEF_CHK_VAL(CPU_CFG_INT_DIS_MEAS_OVRHD_NBR,                      CPU_TIME_MEAS_NBR_MIN,                               CPU_TIME_MEAS_NBR_MAX) != DEF_OK)
S#error  "CPU_CFG_INT_DIS_MEAS_OVRHD_NBR  illegally #define'd in 'cpu_cfg.h' "
S#error  "                                [MUST be  >= CPU_TIME_MEAS_NBR_MIN]"
S#error  "                                [     ||  <= CPU_TIME_MEAS_NBR_MAX]"
S
S#endif
S
S#endif
S
S
S
S
S#ifndef  CPU_CFG_LEAD_ZEROS_ASM_PRESENT
S#if 0                                                           /* Optionally configured in 'cpu_cfg.h'; DO NOT MODIFY. */
S#error  "CPU_CFG_LEAD_ZEROS_ASM_PRESENT        not #define'd in 'cpu.h'/'cpu_cfg.h'"
S#endif
S#endif
S
S
S#ifndef  CPU_CFG_TRAIL_ZEROS_ASM_PRESENT
S#if 0                                                           /* Optionally configured in 'cpu_cfg.h'; DO NOT MODIFY. */
S#error  "CPU_CFG_TRAIL_ZEROS_ASM_PRESENT       not #define'd in 'cpu.h'/'cpu_cfg.h'"
S#endif
S#endif
S
S
S/*$PAGE*/
S/*
S*********************************************************************************************************
S*                                    CPU PORT CONFIGURATION ERRORS
S*********************************************************************************************************
S*/
S
S#ifndef  CPU_CFG_ADDR_SIZE
S#error  "CPU_CFG_ADDR_SIZE      not #define'd in 'cpu.h'"
S#endif
S
S#ifndef  CPU_CFG_DATA_SIZE
S#error  "CPU_CFG_DATA_SIZE      not #define'd in 'cpu.h'"
S#endif
S
S#ifndef  CPU_CFG_DATA_SIZE_MAX
S#error  "CPU_CFG_DATA_SIZE_MAX  not #define'd in 'cpu.h'"
S#endif
S
S
S/*
S*********************************************************************************************************
S*                                    LIBRARY CONFIGURATION ERRORS
S*********************************************************************************************************
S*/
S
S                                                                /* See 'cpu_core.h  Note #1a'.                          */
S#if     (LIB_VERSION < 13500u)
S#error  "LIB_VERSION  [SHOULD be >= V1.35.00]"
S#endif
S
S
S/*
S*********************************************************************************************************
S*                                             MODULE END
S*
S* Note(s) : (1) See 'cpu_core.h  MODULE'.
S*********************************************************************************************************
S*/
S
N#endif                                                          /* End of CPU core module include.                      */
N
L 108 "..\..\uCOS-III\uC-LIB\lib_mem.h" 2
N
N#include  <lib_def.h>
N#include  <lib_cfg.h>
L 1 "..\..\User\lib_cfg.h" 1
N/*
N*********************************************************************************************************
N*                                                uC/LIB
N*                                        CUSTOM LIBRARY MODULES
N*
N*                          (c) Copyright 2004-2013; Micrium, Inc.; Weston, FL
N*
N*               All rights reserved.  Protected by international copyright laws.
N*
N*               uC/LIB is provided in source form to registered licensees ONLY.  It is 
N*               illegal to distribute this source code to any third party unless you receive 
N*               written permission by an authorized Micrium representative.  Knowledge of 
N*               the source code may NOT be used to develop a similar product.
N*
N*               Please help us continue to provide the Embedded community with the finest 
N*               software available.  Your honesty is greatly appreciated.
N*
N*               You can contact us at www.micrium.com.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*
N*                                  CUSTOM LIBRARY CONFIGURATION FILE
N*
N*                                     ST Microelectronics STM32
N*                                              on the
N*
N*                                           STM3240G-EVAL
N*                                         Evaluation Board
N*
N* Filename      : lib_cfg.h
N* Version       : V1.35.00
N* Programmer(s) : DC
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                               MODULE
N*********************************************************************************************************
N*/
N
N#ifndef  LIB_CFG_MODULE_PRESENT
N#define  LIB_CFG_MODULE_PRESENT
N
N
N/*
N*********************************************************************************************************
N*                                          uC/LIB CONFIGURATION
N*********************************************************************************************************
N*/
N
N#define  LIB_MEM_CFG_ARG_CHK_EXT_EN     DEF_ENABLED
N                                                        /*   DEF_DISABLED     Argument check DISABLED                   */
N                                                        /*   DEF_ENABLED      Argument check ENABLED                    */
N
N#define  LIB_MEM_CFG_OPTIMIZE_ASM_EN    DEF_ENABLED
N                                                        /*   DEF_DISABLED     Assembly-optimized function(s) DISABLED   */
N                                                        /*   DEF_ENABLED      Assembly-optimized function(s) ENABLED    */
N
N#define  LIB_MEM_CFG_ALLOC_EN           DEF_ENABLED
N                                                        /*   DEF_DISABLED     Memory allocation DISABLED                */
N                                                        /*   DEF_ENABLED      Memory allocation ENABLED                 */
N
N
N#define  LIB_MEM_CFG_HEAP_SIZE          23u * 1024u     /* Configure Heap Memory Size                                   */
N
N
N/*
N*********************************************************************************************************
N*                                             MODULE END
N*********************************************************************************************************
N*/
N
N#endif                                                  /* End of lib cfg module include.                               */
N
L 111 "..\..\uCOS-III\uC-LIB\lib_mem.h" 2
N
N
N/*
N*********************************************************************************************************
N*                                               EXTERNS
N*********************************************************************************************************
N*/
N
N#ifdef   LIB_MEM_MODULE
S#define  LIB_MEM_EXT
N#else
N#define  LIB_MEM_EXT  extern
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                        DEFAULT CONFIGURATION
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                             MEMORY LIBRARY ARGUMENT CHECK CONFIGURATION
N*
N* Note(s) : (1) Configure LIB_MEM_CFG_ARG_CHK_EXT_EN to enable/disable the memory library suite external
N*               argument check feature :
N*
N*               (a) When ENABLED,      arguments received from any port interface provided by the developer
N*                   or application are checked/validated.
N*
N*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
N*                   or application are checked/validated.
N*********************************************************************************************************
N*/
N
N                                                        /* Configure external argument check feature (see Note #1) :    */
N#ifndef  LIB_MEM_CFG_ARG_CHK_EXT_EN
S#define  LIB_MEM_CFG_ARG_CHK_EXT_EN     DEF_DISABLED
S                                                        /*   DEF_DISABLED     Argument check DISABLED                   */
S                                                        /*   DEF_ENABLED      Argument check ENABLED                    */
N#endif
N
N
N/*
N*********************************************************************************************************
N*                         MEMORY LIBRARY ASSEMBLY OPTIMIZATION CONFIGURATION
N*
N* Note(s) : (1) Configure LIB_MEM_CFG_OPTIMIZE_ASM_EN to enable/disable assembly-optimized memory functions.
N*********************************************************************************************************
N*/
N
N                                                        /* Configure assembly-optimized function(s) [see Note #1] :     */
N#ifndef  LIB_MEM_CFG_OPTIMIZE_ASM_EN
S#define  LIB_MEM_CFG_OPTIMIZE_ASM_EN    DEF_DISABLED
S                                                        /*   DEF_DISABLED     Assembly-optimized function(s) DISABLED   */
S                                                        /*   DEF_ENABLED      Assembly-optimized function(s) ENABLED    */
N#endif
N
N
N/*
N*********************************************************************************************************
N*                                   MEMORY ALLOCATION CONFIGURATION
N*
N* Note(s) : (1) Configure LIB_MEM_CFG_ALLOC_EN to enable/disable memory allocation functions.
N*********************************************************************************************************
N*/
N
N                                                        /* Configure memory allocation feature (see Note #1) :          */
N#ifndef  LIB_MEM_CFG_ALLOC_EN
S#define  LIB_MEM_CFG_ALLOC_EN           DEF_DISABLED
S                                                        /*   DEF_DISABLED     Memory allocation DISABLED                */
S                                                        /*   DEF_ENABLED      Memory allocation ENABLED                 */
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                               DEFINES
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                     MEMORY LIBRARY TYPE DEFINES
N*
N* Note(s) : (1) LIB_MEM_TYPE_&&& #define values specifically chosen as ASCII representations of the memory
N*               library types.  Memory displays of memory library objects will display the library TYPEs
N*               with their chosen ASCII names.
N*********************************************************************************************************
N*/
N
N#define  LIB_MEM_TYPE_NONE                        CPU_TYPE_CREATE('N', 'O', 'N', 'E')
N#define  LIB_MEM_TYPE_HEAP                        CPU_TYPE_CREATE('H', 'E', 'A', 'P')
N#define  LIB_MEM_TYPE_POOL                        CPU_TYPE_CREATE('P', 'O', 'O', 'L')
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                             DATA TYPES
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                            LIB MEM TYPE
N*
N* Note(s) : (1) 'LIB_MEM_TYPE' declared as 'CPU_INT32U' & all 'LIB_MEM_TYPE's #define'd with large, non-trivial
N*               values to trap & discard invalid/corrupted library memory objects based on 'LIB_MEM_TYPE'.
N*********************************************************************************************************
N*/
N
Ntypedef  CPU_INT32U  LIB_MEM_TYPE;
N
N
N/*
N*********************************************************************************************************
N*                                MEMORY POOL BLOCK QUANTITY DATA TYPE
N*********************************************************************************************************
N*/
N
Ntypedef  CPU_SIZE_T  MEM_POOL_BLK_QTY;
N
N
N/*
N*********************************************************************************************************
N*                                      MEMORY POOL TABLE IX TYPE
N*********************************************************************************************************
N*/
N
Ntypedef  MEM_POOL_BLK_QTY  MEM_POOL_IX;
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                        MEMORY POOL DATA TYPES
N*
N*                                                                      MEMORY SEGMENT
N*                                                                     ----------------
N*                                            MEMORY POOL'S            |              | <----
N*                                             POINTERS TO             |    MEMORY    |     |
N*                    MEM_POOL                MEMORY BLOCKS            |    BLOCKS    |     |
N*               |----------------|            |---------|             |   --------   |     |
N*               |        O------------------> |    O--------------------> |      |   |     |
N*               |----------------|            |---------|             |   |      |   |     |
N*               | Pool Addr Ptrs |            |    O-------------     |   --------   |     |
N*               | Pool Size      |            |---------|       |     |              |     |
N*               |----------------|            |         |       |     |   --------   |     |
N*               |    Blk Size    |            |         |       --------> |      |   |     |
N*               |    Blk Nbr     |            |         |             |   |      |   |     |
N*               |    Blk Ix      |            |    .    |             |   --------   |     |
N*               |----------------|            |    .    |             |              |     |
N*               |----------------|            |    .    |             |      .       |     |
N*               |        O-----------------   |         |             |      .       |     |
N*               |----------------|        |   |         |             |      .       |     |
N*               |        O------------    |   |         |             |              |     |
N*               |----------------|   |    |   |---------|             |   --------   |     |
N*               |  Seg Size Tot  |   |    |   |    O--------------------> |      |   |     |
N*               |  Seg Size Rem  |   |    |   |---------|             |   |      |   |     |
N*               |----------------|   |    |   |         |             |   --------   |     |
N*               | Seg List Ptrs  |   |    |   |---------|             |              |     |
N*               |----------------|   |    |                           | ------------ |     |
N*                                    |    |                           |              | <--------
N*                                    |    |                           |              |     |   |
N*                                    |    |                           |              |     |   |
N*                                    |    |                           |              |     |   |
N*                                    |    |                           |              |     |   |
N*                                    |    |                           |              |     |   |
N*                                    |    |                           ----------------     |   |
N*                                    |    |                                                |   |
N*                                    |    --------------------------------------------------   |
N*                                    |                                                         |
N*                                    -----------------------------------------------------------
N*
N*********************************************************************************************************
N*/
N
Ntypedef  struct  mem_pool  MEM_POOL;
N
N                                                                /* --------------------- MEM POOL --------------------- */
Nstruct  mem_pool {
N    LIB_MEM_TYPE        Type;                                   /* Pool type : LIB_TYPE_POOL or LIB_TYPE_HEAP.          */
N
N    MEM_POOL           *SegHeadPtr;                             /* Ptr to head mem seg.                                 */
N    MEM_POOL           *SegPrevPtr;                             /* Ptr to PREV mem seg.                                 */
N    MEM_POOL           *SegNextPtr;                             /* Ptr to NEXT mem seg.                                 */
N    MEM_POOL           *PoolPrevPtr;                            /* Ptr to PREV mem pool.                                */
N    MEM_POOL           *PoolNextPtr;                            /* Ptr to NEXT mem pool.                                */
N
N    void               *PoolAddrStart;                          /* Ptr   to start of mem seg for mem pool blks.         */
N    void               *PoolAddrEnd;                            /* Ptr   to end   of mem seg for mem pool blks.         */
N    void              **PoolPtrs;                               /* Ptr   to mem pool's array of blk ptrs.               */
N    MEM_POOL_IX         BlkIx;                                  /* Ix  into mem pool's array of blk ptrs.               */
N    CPU_SIZE_T          PoolSize;                               /* Size  of mem pool        (in octets).                */
N    MEM_POOL_BLK_QTY    BlkNbr;                                 /* Nbr   of mem pool   blks.                            */
N    CPU_SIZE_T          BlkSize;                                /* Size  of mem pool   blks (in octets).                */
N    CPU_SIZE_T          BlkAlign;                               /* Align of mem pool   blks (in octets).                */
N
N                                                                /* --------------------- MEM SEG ---------------------- */
N    void               *SegAddr;                                /* Ptr      to mem seg's base/start addr.               */
N    void               *SegAddrNextAvail;                       /* Ptr      to mem seg's next avail addr.               */
N    CPU_SIZE_T          SegSizeTot;                             /* Tot size of mem seg (in octets).                     */
N    CPU_SIZE_T          SegSizeRem;                             /* Rem size of mem seg (in octets).                     */
N};
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          GLOBAL VARIABLES
N*********************************************************************************************************
N*/
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                              MACRO'S
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                      MEMORY DATA VALUE MACRO'S
N*
N* Note(s) : (1) (a) Some variables & variable buffers to pass & receive data values MUST start on appropriate
N*                   CPU word-aligned addresses.  This is required because most word-aligned processors are more
N*                   efficient & may even REQUIRE that multi-octet words start on CPU word-aligned addresses.
N*
N*                   (1) For 16-bit word-aligned processors, this means that
N*
N*                           all 16- & 32-bit words MUST start on addresses that are multiples of 2 octets
N*
N*                   (2) For 32-bit word-aligned processors, this means that
N*
N*                           all 16-bit       words MUST start on addresses that are multiples of 2 octets
N*                           all 32-bit       words MUST start on addresses that are multiples of 4 octets
N*
N*               (b) However, some data values macro's appropriately access data values from any CPU addresses,
N*                   word-aligned or not.  Thus for processors that require data word alignment, data words can
N*                   be accessed to/from any CPU address, word-aligned or not, without generating data-word-
N*                   alignment exceptions/faults.
N*********************************************************************************************************
N*/
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                      ENDIAN WORD ORDER MACRO'S
N*
N* Description : Convert data values to & from big-, little, or host-endian CPU word order.
N*
N* Argument(s) : val       Data value to convert (see Notes #1 & #2).
N*
N* Return(s)   : Converted data value (see Notes #1 & #2).
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) Convert data values to the desired data-word order :
N*
N*                       MEM_VAL_BIG_TO_LITTLE_xx()      Convert big-        endian data values
N*                                                            to little-     endian data values
N*                       MEM_VAL_LITTLE_TO_BIG_xx()      Convert little-     endian data values
N*                                                            to big-        endian data values
N*                       MEM_VAL_xxx_TO_HOST_xx()        Convert big-/little-endian data values
N*                                                            to host-       endian data values
N*                       MEM_VAL_HOST_TO_xxx_xx()        Convert host-       endian data values
N*                                                            to big-/little-endian data values
N*
N*                   See also 'cpu.h  CPU WORD CONFIGURATION  Note #2'.
N*
N*               (2) 'val' data value to convert & any variable to receive the returned conversion MUST
N*                   start on appropriate CPU word-aligned addresses.
N*
N*                   See also 'MEMORY DATA VALUE MACRO'S  Note #1a'.
N*
N*               (3) MEM_VAL_COPY_xxx() macro's are more efficient than generic endian word order macro's &
N*                   are also independent of CPU data-word-alignment & SHOULD be used whenever possible.
N*
N*                   See also 'MEM_VAL_COPY_GET_xxx()  Note #4'
N*                          & 'MEM_VAL_COPY_SET_xxx()  Note #4'.
N*
N*               (4) Generic endian word order macro's are NOT atomic operations & MUST NOT be used on any
N*                   non-static (i.e. volatile) variables, registers, hardware, etc.; without the caller of
N*                   the macro's providing some form of additional protection (e.g. mutual exclusion).
N*
N*               (5) The 'CPU_CFG_ENDIAN_TYPE' pre-processor 'else'-conditional code SHOULD never be compiled/
N*                   linked since each 'cpu.h' SHOULD ensure that the CPU data-word-memory order configuration
N*                   constant (CPU_CFG_ENDIAN_TYPE) is configured with an appropriate data-word-memory order
N*                   value (see 'cpu.h  CPU WORD CONFIGURATION  Note #2').  The 'else'-conditional code is
N*                   included as an extra precaution in case 'cpu.h' is incorrectly configured.
N*********************************************************************************************************
N*/
N/*$PAGE*/
N
N#if    ((CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_64) || \
N        (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_32))
X#if    ((4 == 8) ||         (4 == 4))
N
N#define  MEM_VAL_BIG_TO_LITTLE_16(val)        ((CPU_INT16U)(((CPU_INT16U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0xFF00u) >> (1u * DEF_OCTET_NBR_BITS))) | \
N                                                            ((CPU_INT16U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0x00FFu) << (1u * DEF_OCTET_NBR_BITS)))))
X#define  MEM_VAL_BIG_TO_LITTLE_16(val)        ((CPU_INT16U)(((CPU_INT16U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0xFF00u) >> (1u * DEF_OCTET_NBR_BITS))) |                                                             ((CPU_INT16U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0x00FFu) << (1u * DEF_OCTET_NBR_BITS)))))
N
N#define  MEM_VAL_BIG_TO_LITTLE_32(val)        ((CPU_INT32U)(((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0xFF000000u) >> (3u * DEF_OCTET_NBR_BITS))) | \
N                                                            ((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x00FF0000u) >> (1u * DEF_OCTET_NBR_BITS))) | \
N                                                            ((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x0000FF00u) << (1u * DEF_OCTET_NBR_BITS))) | \
N                                                            ((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x000000FFu) << (3u * DEF_OCTET_NBR_BITS)))))
X#define  MEM_VAL_BIG_TO_LITTLE_32(val)        ((CPU_INT32U)(((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0xFF000000u) >> (3u * DEF_OCTET_NBR_BITS))) |                                                             ((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x00FF0000u) >> (1u * DEF_OCTET_NBR_BITS))) |                                                             ((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x0000FF00u) << (1u * DEF_OCTET_NBR_BITS))) |                                                             ((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x000000FFu) << (3u * DEF_OCTET_NBR_BITS)))))
N
N#elif   (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_16)
S
S#define  MEM_VAL_BIG_TO_LITTLE_16(val)        ((CPU_INT16U)(((CPU_INT16U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0xFF00u) >> (1u * DEF_OCTET_NBR_BITS))) | \
S                                                            ((CPU_INT16U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0x00FFu) << (1u * DEF_OCTET_NBR_BITS)))))
X#define  MEM_VAL_BIG_TO_LITTLE_16(val)        ((CPU_INT16U)(((CPU_INT16U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0xFF00u) >> (1u * DEF_OCTET_NBR_BITS))) |                                                             ((CPU_INT16U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0x00FFu) << (1u * DEF_OCTET_NBR_BITS)))))
S
S#define  MEM_VAL_BIG_TO_LITTLE_32(val)        ((CPU_INT32U)(((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0xFF000000u) >> (1u * DEF_OCTET_NBR_BITS))) | \
S                                                            ((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x00FF0000u) << (1u * DEF_OCTET_NBR_BITS))) | \
S                                                            ((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x0000FF00u) >> (1u * DEF_OCTET_NBR_BITS))) | \
S                                                            ((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x000000FFu) << (1u * DEF_OCTET_NBR_BITS)))))
X#define  MEM_VAL_BIG_TO_LITTLE_32(val)        ((CPU_INT32U)(((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0xFF000000u) >> (1u * DEF_OCTET_NBR_BITS))) |                                                             ((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x00FF0000u) << (1u * DEF_OCTET_NBR_BITS))) |                                                             ((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x0000FF00u) >> (1u * DEF_OCTET_NBR_BITS))) |                                                             ((CPU_INT32U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x000000FFu) << (1u * DEF_OCTET_NBR_BITS)))))
S
S#else
S
S#define  MEM_VAL_BIG_TO_LITTLE_16(val)                                                  (val)
S#define  MEM_VAL_BIG_TO_LITTLE_32(val)                                                  (val)
S
N#endif
N
N
N#define  MEM_VAL_LITTLE_TO_BIG_16(val)                          MEM_VAL_BIG_TO_LITTLE_16(val)
N#define  MEM_VAL_LITTLE_TO_BIG_32(val)                          MEM_VAL_BIG_TO_LITTLE_32(val)
N
N
N
N#if     (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
X#if     (2u == 1u)
S
S#define  MEM_VAL_BIG_TO_HOST_16(val)                                                    (val)
S#define  MEM_VAL_BIG_TO_HOST_32(val)                                                    (val)
S#define  MEM_VAL_LITTLE_TO_HOST_16(val)                         MEM_VAL_LITTLE_TO_BIG_16(val)
S#define  MEM_VAL_LITTLE_TO_HOST_32(val)                         MEM_VAL_LITTLE_TO_BIG_32(val)
S
N#elif   (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_LITTLE)
X#elif   (2u == 2u)
N
N#define  MEM_VAL_BIG_TO_HOST_16(val)                            MEM_VAL_BIG_TO_LITTLE_16(val)
N#define  MEM_VAL_BIG_TO_HOST_32(val)                            MEM_VAL_BIG_TO_LITTLE_32(val)
N#define  MEM_VAL_LITTLE_TO_HOST_16(val)                                                 (val)
N#define  MEM_VAL_LITTLE_TO_HOST_32(val)                                                 (val)
N
N#else                                                               /* See Note #5.                                     */
S
S#error  "CPU_CFG_ENDIAN_TYPE  illegally #defined in 'cpu.h'      "
S#error  "                     [See 'cpu.h  CONFIGURATION ERRORS']"
S
N#endif
N
N
N#define  MEM_VAL_HOST_TO_BIG_16(val)                            MEM_VAL_BIG_TO_HOST_16(val)
N#define  MEM_VAL_HOST_TO_BIG_32(val)                            MEM_VAL_BIG_TO_HOST_32(val)
N#define  MEM_VAL_HOST_TO_LITTLE_16(val)                         MEM_VAL_LITTLE_TO_HOST_16(val)
N#define  MEM_VAL_HOST_TO_LITTLE_32(val)                         MEM_VAL_LITTLE_TO_HOST_32(val)
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          MEM_VAL_GET_xxx()
N*
N* Description : Decode data values from any CPU memory address.
N*
N* Argument(s) : addr        Lowest CPU memory address of data value to decode (see Notes #2 & #3a).
N*
N* Return(s)   : Decoded data value from CPU memory address (see Notes #1 & #3b).
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) Decode data values based on the values' data-word order in CPU memory :
N*
N*                       MEM_VAL_GET_xxx_BIG()           Decode big-   endian data values -- data words' most
N*                                                           significant octet @ lowest memory address
N*                       MEM_VAL_GET_xxx_LITTLE()        Decode little-endian data values -- data words' least
N*                                                           significant octet @ lowest memory address
N*                       MEM_VAL_GET_xxx()               Decode data values using CPU's native or configured
N*                                                           data-word order
N*
N*                   See also 'cpu.h  CPU WORD CONFIGURATION  Note #2'.
N*
N*               (2) CPU memory addresses/pointers NOT checked for NULL.
N*
N*               (3) (a) MEM_VAL_GET_xxx() macro's decode data values without regard to CPU word-aligned addresses.
N*                       Thus for processors that require data word alignment, data words can be decoded from any
N*                       CPU address, word-aligned or not, without generating data-word-alignment exceptions/faults.
N*
N*                   (b) However, any variable to receive the returned data value MUST start on an appropriate CPU
N*                       word-aligned address.
N*
N*                   See also 'MEMORY DATA VALUE MACRO'S  Note #1'.
N*
N*               (4) MEM_VAL_COPY_GET_xxx() macro's are more efficient than MEM_VAL_GET_xxx() macro's & are
N*                   also independent of CPU data-word-alignment & SHOULD be used whenever possible.
N*
N*                   See also 'MEM_VAL_COPY_GET_xxx()  Note #4'.
N*
N*               (5) MEM_VAL_GET_xxx() macro's are NOT atomic operations & MUST NOT be used on any non-static
N*                   (i.e. volatile) variables, registers, hardware, etc.; without the caller of the macro's
N*                   providing some form of additional protection (e.g. mutual exclusion).
N*
N*               (6) The 'CPU_CFG_ENDIAN_TYPE' pre-processor 'else'-conditional code SHOULD never be compiled/
N*                   linked since each 'cpu.h' SHOULD ensure that the CPU data-word-memory order configuration
N*                   constant (CPU_CFG_ENDIAN_TYPE) is configured with an appropriate data-word-memory order
N*                   value (see 'cpu.h  CPU WORD CONFIGURATION  Note #2').  The 'else'-conditional code is
N*                   included as an extra precaution in case 'cpu.h' is incorrectly configured.
N*********************************************************************************************************
N*/
N/*$PAGE*/
N
N#define  MEM_VAL_GET_INT08U_BIG(addr)           ((CPU_INT08U) ((CPU_INT08U)(((CPU_INT08U)(*(((CPU_INT08U *)(addr)) + 0))) << (0u * DEF_OCTET_NBR_BITS))))
N
N#define  MEM_VAL_GET_INT16U_BIG(addr)           ((CPU_INT16U)(((CPU_INT16U)(((CPU_INT16U)(*(((CPU_INT08U *)(addr)) + 0))) << (1u * DEF_OCTET_NBR_BITS))) + \
N                                                              ((CPU_INT16U)(((CPU_INT16U)(*(((CPU_INT08U *)(addr)) + 1))) << (0u * DEF_OCTET_NBR_BITS)))))
X#define  MEM_VAL_GET_INT16U_BIG(addr)           ((CPU_INT16U)(((CPU_INT16U)(((CPU_INT16U)(*(((CPU_INT08U *)(addr)) + 0))) << (1u * DEF_OCTET_NBR_BITS))) +                                                               ((CPU_INT16U)(((CPU_INT16U)(*(((CPU_INT08U *)(addr)) + 1))) << (0u * DEF_OCTET_NBR_BITS)))))
N
N#define  MEM_VAL_GET_INT32U_BIG(addr)           ((CPU_INT32U)(((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 0))) << (3u * DEF_OCTET_NBR_BITS))) + \
N                                                              ((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 1))) << (2u * DEF_OCTET_NBR_BITS))) + \
N                                                              ((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 2))) << (1u * DEF_OCTET_NBR_BITS))) + \
N                                                              ((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 3))) << (0u * DEF_OCTET_NBR_BITS)))))
X#define  MEM_VAL_GET_INT32U_BIG(addr)           ((CPU_INT32U)(((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 0))) << (3u * DEF_OCTET_NBR_BITS))) +                                                               ((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 1))) << (2u * DEF_OCTET_NBR_BITS))) +                                                               ((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 2))) << (1u * DEF_OCTET_NBR_BITS))) +                                                               ((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 3))) << (0u * DEF_OCTET_NBR_BITS)))))
N
N
N
N#define  MEM_VAL_GET_INT08U_LITTLE(addr)        ((CPU_INT08U) ((CPU_INT08U)(((CPU_INT08U)(*(((CPU_INT08U *)(addr)) + 0))) << (0u * DEF_OCTET_NBR_BITS))))
N
N#define  MEM_VAL_GET_INT16U_LITTLE(addr)        ((CPU_INT16U)(((CPU_INT16U)(((CPU_INT16U)(*(((CPU_INT08U *)(addr)) + 0))) << (0u * DEF_OCTET_NBR_BITS))) + \
N                                                              ((CPU_INT16U)(((CPU_INT16U)(*(((CPU_INT08U *)(addr)) + 1))) << (1u * DEF_OCTET_NBR_BITS)))))
X#define  MEM_VAL_GET_INT16U_LITTLE(addr)        ((CPU_INT16U)(((CPU_INT16U)(((CPU_INT16U)(*(((CPU_INT08U *)(addr)) + 0))) << (0u * DEF_OCTET_NBR_BITS))) +                                                               ((CPU_INT16U)(((CPU_INT16U)(*(((CPU_INT08U *)(addr)) + 1))) << (1u * DEF_OCTET_NBR_BITS)))))
N
N#define  MEM_VAL_GET_INT32U_LITTLE(addr)        ((CPU_INT32U)(((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 0))) << (0u * DEF_OCTET_NBR_BITS))) + \
N                                                              ((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 1))) << (1u * DEF_OCTET_NBR_BITS))) + \
N                                                              ((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 2))) << (2u * DEF_OCTET_NBR_BITS))) + \
N                                                              ((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 3))) << (3u * DEF_OCTET_NBR_BITS)))))
X#define  MEM_VAL_GET_INT32U_LITTLE(addr)        ((CPU_INT32U)(((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 0))) << (0u * DEF_OCTET_NBR_BITS))) +                                                               ((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 1))) << (1u * DEF_OCTET_NBR_BITS))) +                                                               ((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 2))) << (2u * DEF_OCTET_NBR_BITS))) +                                                               ((CPU_INT32U)(((CPU_INT32U)(*(((CPU_INT08U *)(addr)) + 3))) << (3u * DEF_OCTET_NBR_BITS)))))
N
N
N
N#if     (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
X#if     (2u == 1u)
S
S#define  MEM_VAL_GET_INT08U(addr)                               MEM_VAL_GET_INT08U_BIG(addr)
S#define  MEM_VAL_GET_INT16U(addr)                               MEM_VAL_GET_INT16U_BIG(addr)
S#define  MEM_VAL_GET_INT32U(addr)                               MEM_VAL_GET_INT32U_BIG(addr)
S
N#elif   (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_LITTLE)
X#elif   (2u == 2u)
N
N#define  MEM_VAL_GET_INT08U(addr)                               MEM_VAL_GET_INT08U_LITTLE(addr)
N#define  MEM_VAL_GET_INT16U(addr)                               MEM_VAL_GET_INT16U_LITTLE(addr)
N#define  MEM_VAL_GET_INT32U(addr)                               MEM_VAL_GET_INT32U_LITTLE(addr)
N
N#else                                                               /* See Note #6.                                     */
S
S#error  "CPU_CFG_ENDIAN_TYPE  illegally #defined in 'cpu.h'      "
S#error  "                     [See 'cpu.h  CONFIGURATION ERRORS']"
S
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          MEM_VAL_SET_xxx()
N*
N* Description : Encode data values to any CPU memory address.
N*
N* Argument(s) : addr        Lowest CPU memory address to encode data value (see Notes #2 & #3a).
N*
N*               val         Data value to encode (see Notes #1 & #3b).
N*
N* Return(s)   : none.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) Encode data values into CPU memory based on the values' data-word order :
N*
N*                       MEM_VAL_SET_xxx_BIG()           Encode big-   endian data values -- data words' most
N*                                                           significant octet @ lowest memory address
N*                       MEM_VAL_SET_xxx_LITTLE()        Encode little-endian data values -- data words' least
N*                                                           significant octet @ lowest memory address
N*                       MEM_VAL_SET_xxx()               Encode data values using CPU's native or configured
N*                                                           data-word order
N*
N*                   See also 'cpu.h  CPU WORD CONFIGURATION  Note #2'.
N*
N*               (2) CPU memory addresses/pointers NOT checked for NULL.
N*
N*               (3) (a) MEM_VAL_SET_xxx() macro's encode data values without regard to CPU word-aligned addresses.
N*                       Thus for processors that require data word alignment, data words can be encoded to any
N*                       CPU address, word-aligned or not, without generating data-word-alignment exceptions/faults.
N*
N*                   (b) However, 'val' data value to encode MUST start on an appropriate CPU word-aligned address.
N*
N*                   See also 'MEMORY DATA VALUE MACRO'S  Note #1'.
N*
N*               (4) MEM_VAL_COPY_SET_xxx() macro's are more efficient than MEM_VAL_SET_xxx() macro's & are
N*                   also independent of CPU data-word-alignment & SHOULD be used whenever possible.
N*
N*                   See also 'MEM_VAL_COPY_SET_xxx()  Note #4'.
N*
N*               (5) MEM_VAL_SET_xxx() macro's are NOT atomic operations & MUST NOT be used on any non-static
N*                   (i.e. volatile) variables, registers, hardware, etc.; without the caller of the macro's
N*                   providing some form of additional protection (e.g. mutual exclusion).
N*
N*               (6) The 'CPU_CFG_ENDIAN_TYPE' pre-processor 'else'-conditional code SHOULD never be compiled/
N*                   linked since each 'cpu.h' SHOULD ensure that the CPU data-word-memory order configuration
N*                   constant (CPU_CFG_ENDIAN_TYPE) is configured with an appropriate data-word-memory order
N*                   value (see 'cpu.h  CPU WORD CONFIGURATION  Note #2').  The 'else'-conditional code is
N*                   included as an extra precaution in case 'cpu.h' is incorrectly configured.
N*********************************************************************************************************
N*/
N/*$PAGE*/
N
N#define  MEM_VAL_SET_INT08U_BIG(addr, val)                     do { (*(((CPU_INT08U *)(addr)) + 0)) = ((CPU_INT08U)((((CPU_INT08U)(val)) & (CPU_INT08U)      0xFFu) >> (0u * DEF_OCTET_NBR_BITS))); } while (0)
N
N#define  MEM_VAL_SET_INT16U_BIG(addr, val)                     do { (*(((CPU_INT08U *)(addr)) + 0)) = ((CPU_INT08U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0xFF00u) >> (1u * DEF_OCTET_NBR_BITS))); \
N                                                                    (*(((CPU_INT08U *)(addr)) + 1)) = ((CPU_INT08U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0x00FFu) >> (0u * DEF_OCTET_NBR_BITS))); } while (0)
X#define  MEM_VAL_SET_INT16U_BIG(addr, val)                     do { (*(((CPU_INT08U *)(addr)) + 0)) = ((CPU_INT08U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0xFF00u) >> (1u * DEF_OCTET_NBR_BITS)));                                                                     (*(((CPU_INT08U *)(addr)) + 1)) = ((CPU_INT08U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0x00FFu) >> (0u * DEF_OCTET_NBR_BITS))); } while (0)
N
N#define  MEM_VAL_SET_INT32U_BIG(addr, val)                     do { (*(((CPU_INT08U *)(addr)) + 0)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0xFF000000u) >> (3u * DEF_OCTET_NBR_BITS))); \
N                                                                    (*(((CPU_INT08U *)(addr)) + 1)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x00FF0000u) >> (2u * DEF_OCTET_NBR_BITS))); \
N                                                                    (*(((CPU_INT08U *)(addr)) + 2)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x0000FF00u) >> (1u * DEF_OCTET_NBR_BITS))); \
N                                                                    (*(((CPU_INT08U *)(addr)) + 3)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x000000FFu) >> (0u * DEF_OCTET_NBR_BITS))); } while (0)
X#define  MEM_VAL_SET_INT32U_BIG(addr, val)                     do { (*(((CPU_INT08U *)(addr)) + 0)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0xFF000000u) >> (3u * DEF_OCTET_NBR_BITS)));                                                                     (*(((CPU_INT08U *)(addr)) + 1)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x00FF0000u) >> (2u * DEF_OCTET_NBR_BITS)));                                                                     (*(((CPU_INT08U *)(addr)) + 2)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x0000FF00u) >> (1u * DEF_OCTET_NBR_BITS)));                                                                     (*(((CPU_INT08U *)(addr)) + 3)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x000000FFu) >> (0u * DEF_OCTET_NBR_BITS))); } while (0)
N
N
N
N#define  MEM_VAL_SET_INT08U_LITTLE(addr, val)                  do { (*(((CPU_INT08U *)(addr)) + 0)) = ((CPU_INT08U)((((CPU_INT08U)(val)) & (CPU_INT08U)      0xFFu) >> (0u * DEF_OCTET_NBR_BITS))); } while (0)
N
N#define  MEM_VAL_SET_INT16U_LITTLE(addr, val)                  do { (*(((CPU_INT08U *)(addr)) + 0)) = ((CPU_INT08U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0x00FFu) >> (0u * DEF_OCTET_NBR_BITS))); \
N                                                                    (*(((CPU_INT08U *)(addr)) + 1)) = ((CPU_INT08U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0xFF00u) >> (1u * DEF_OCTET_NBR_BITS))); } while (0)
X#define  MEM_VAL_SET_INT16U_LITTLE(addr, val)                  do { (*(((CPU_INT08U *)(addr)) + 0)) = ((CPU_INT08U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0x00FFu) >> (0u * DEF_OCTET_NBR_BITS)));                                                                     (*(((CPU_INT08U *)(addr)) + 1)) = ((CPU_INT08U)((((CPU_INT16U)(val)) & (CPU_INT16U)    0xFF00u) >> (1u * DEF_OCTET_NBR_BITS))); } while (0)
N
N#define  MEM_VAL_SET_INT32U_LITTLE(addr, val)                  do { (*(((CPU_INT08U *)(addr)) + 0)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x000000FFu) >> (0u * DEF_OCTET_NBR_BITS))); \
N                                                                    (*(((CPU_INT08U *)(addr)) + 1)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x0000FF00u) >> (1u * DEF_OCTET_NBR_BITS))); \
N                                                                    (*(((CPU_INT08U *)(addr)) + 2)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x00FF0000u) >> (2u * DEF_OCTET_NBR_BITS))); \
N                                                                    (*(((CPU_INT08U *)(addr)) + 3)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0xFF000000u) >> (3u * DEF_OCTET_NBR_BITS))); } while (0)
X#define  MEM_VAL_SET_INT32U_LITTLE(addr, val)                  do { (*(((CPU_INT08U *)(addr)) + 0)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x000000FFu) >> (0u * DEF_OCTET_NBR_BITS)));                                                                     (*(((CPU_INT08U *)(addr)) + 1)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x0000FF00u) >> (1u * DEF_OCTET_NBR_BITS)));                                                                     (*(((CPU_INT08U *)(addr)) + 2)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0x00FF0000u) >> (2u * DEF_OCTET_NBR_BITS)));                                                                     (*(((CPU_INT08U *)(addr)) + 3)) = ((CPU_INT08U)((((CPU_INT32U)(val)) & (CPU_INT32U)0xFF000000u) >> (3u * DEF_OCTET_NBR_BITS))); } while (0)
N
N
N
N#if     (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
X#if     (2u == 1u)
S
S#define  MEM_VAL_SET_INT08U(addr, val)                          MEM_VAL_SET_INT08U_BIG(addr, val)
S#define  MEM_VAL_SET_INT16U(addr, val)                          MEM_VAL_SET_INT16U_BIG(addr, val)
S#define  MEM_VAL_SET_INT32U(addr, val)                          MEM_VAL_SET_INT32U_BIG(addr, val)
S
N#elif   (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_LITTLE)
X#elif   (2u == 2u)
N
N#define  MEM_VAL_SET_INT08U(addr, val)                          MEM_VAL_SET_INT08U_LITTLE(addr, val)
N#define  MEM_VAL_SET_INT16U(addr, val)                          MEM_VAL_SET_INT16U_LITTLE(addr, val)
N#define  MEM_VAL_SET_INT32U(addr, val)                          MEM_VAL_SET_INT32U_LITTLE(addr, val)
N
N#else                                                               /* See Note #6.                                     */
S
S#error  "CPU_CFG_ENDIAN_TYPE  illegally #defined in 'cpu.h'      "
S#error  "                     [See 'cpu.h  CONFIGURATION ERRORS']"
S
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                       MEM_VAL_COPY_GET_xxx()
N*
N* Description : Copy & decode data values from any CPU memory address to any CPU memory address.
N*
N* Argument(s) : addr_dest       Lowest CPU memory address to copy/decode source address's data value
N*                                   (see Notes #2 & #3).
N*
N*               addr_src        Lowest CPU memory address of data value to copy/decode
N*                                   (see Notes #2 & #3).
N*
N* Return(s)   : none.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) Copy/decode data values based on the values' data-word order :
N*
N*                       MEM_VAL_COPY_GET_xxx_BIG()      Decode big-   endian data values -- data words' most
N*                                                           significant octet @ lowest memory address
N*                       MEM_VAL_COPY_GET_xxx_LITTLE()   Decode little-endian data values -- data words' least
N*                                                           significant octet @ lowest memory address
N*                       MEM_VAL_COPY_GET_xxx()          Decode data values using CPU's native or configured
N*                                                           data-word order
N*
N*                   See also 'cpu.h  CPU WORD CONFIGURATION  Note #2'.
N*
N*               (2) (a) CPU memory addresses/pointers NOT checked for NULL.
N*
N*                   (b) CPU memory addresses/buffers  NOT checked for overlapping.
N*
N*                       (1) IEEE Std 1003.1, 2004 Edition, Section 'memcpy() : DESCRIPTION' states that
N*                           "copying ... between objects that overlap ... is undefined".
N*
N*               (3) MEM_VAL_COPY_GET_xxx() macro's copy/decode data values without regard to CPU word-aligned
N*                   addresses.  Thus for processors that require data word alignment, data words can be copied/
N*                   decoded to/from any CPU address, word-aligned or not, without generating data-word-alignment
N*                   exceptions/faults.
N*
N*               (4) MEM_VAL_COPY_GET_xxx() macro's are more efficient than MEM_VAL_GET_xxx() macro's & are
N*                   also independent of CPU data-word-alignment & SHOULD be used whenever possible.
N*
N*                   See also 'MEM_VAL_GET_xxx()  Note #4'.
N*
N*               (5) Since octet-order copy/conversion are inverse operations, MEM_VAL_COPY_GET_xxx() &
N*                   MEM_VAL_COPY_SET_xxx() macros are inverse, but identical, operations & are provided
N*                   in both forms for semantics & consistency.
N*
N*                   See also 'MEM_VAL_COPY_SET_xxx()  Note #5'.
N*
N*               (6) MEM_VAL_COPY_GET_xxx() macro's are NOT atomic operations & MUST NOT be used on any non-
N*                   static (i.e. volatile) variables, registers, hardware, etc.; without the caller of the
N*                   macro's providing some form of additional protection (e.g. mutual exclusion).
N*
N*               (7) The 'CPU_CFG_ENDIAN_TYPE' pre-processor 'else'-conditional code SHOULD never be compiled/
N*                   linked since each 'cpu.h' SHOULD ensure that the CPU data-word-memory order configuration
N*                   constant (CPU_CFG_ENDIAN_TYPE) is configured with an appropriate data-word-memory order
N*                   value (see 'cpu.h  CPU WORD CONFIGURATION  Note #2').  The 'else'-conditional code is
N*                   included as an extra precaution in case 'cpu.h' is incorrectly configured.
N*********************************************************************************************************
N*/
N/*$PAGE*/
N
N#if     (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
X#if     (2u == 1u)
S
S
S#define  MEM_VAL_COPY_GET_INT08U_BIG(addr_dest, addr_src)      do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
S
S#define  MEM_VAL_COPY_GET_INT16U_BIG(addr_dest, addr_src)      do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0)); \
S                                                                    (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 1)); } while (0)
X#define  MEM_VAL_COPY_GET_INT16U_BIG(addr_dest, addr_src)      do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 1)); } while (0)
S
S#define  MEM_VAL_COPY_GET_INT32U_BIG(addr_dest, addr_src)      do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0)); \
S                                                                    (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 1)); \
S                                                                    (*(((CPU_INT08U *)(addr_dest)) + 2)) = (*(((CPU_INT08U *)(addr_src)) + 2)); \
S                                                                    (*(((CPU_INT08U *)(addr_dest)) + 3)) = (*(((CPU_INT08U *)(addr_src)) + 3)); } while (0)
X#define  MEM_VAL_COPY_GET_INT32U_BIG(addr_dest, addr_src)      do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 1));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 2)) = (*(((CPU_INT08U *)(addr_src)) + 2));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 3)) = (*(((CPU_INT08U *)(addr_src)) + 3)); } while (0)
S
S
S
S#define  MEM_VAL_COPY_GET_INT08U_LITTLE(addr_dest, addr_src)   do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
S
S#define  MEM_VAL_COPY_GET_INT16U_LITTLE(addr_dest, addr_src)   do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 1)); \
S                                                                    (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
X#define  MEM_VAL_COPY_GET_INT16U_LITTLE(addr_dest, addr_src)   do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 1));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
S
S#define  MEM_VAL_COPY_GET_INT32U_LITTLE(addr_dest, addr_src)   do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 3)); \
S                                                                    (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 2)); \
S                                                                    (*(((CPU_INT08U *)(addr_dest)) + 2)) = (*(((CPU_INT08U *)(addr_src)) + 1)); \
S                                                                    (*(((CPU_INT08U *)(addr_dest)) + 3)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
X#define  MEM_VAL_COPY_GET_INT32U_LITTLE(addr_dest, addr_src)   do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 3));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 2));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 2)) = (*(((CPU_INT08U *)(addr_src)) + 1));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 3)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
S
S
S
S#define  MEM_VAL_COPY_GET_INT08U(addr_dest, addr_src)               MEM_VAL_COPY_GET_INT08U_BIG(addr_dest, addr_src)
S#define  MEM_VAL_COPY_GET_INT16U(addr_dest, addr_src)               MEM_VAL_COPY_GET_INT16U_BIG(addr_dest, addr_src)
S#define  MEM_VAL_COPY_GET_INT32U(addr_dest, addr_src)               MEM_VAL_COPY_GET_INT32U_BIG(addr_dest, addr_src)
S
S
S
S
N#elif   (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_LITTLE)
X#elif   (2u == 2u)
N
N
N#define  MEM_VAL_COPY_GET_INT08U_BIG(addr_dest, addr_src)      do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
N
N#define  MEM_VAL_COPY_GET_INT16U_BIG(addr_dest, addr_src)      do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 1)); \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
X#define  MEM_VAL_COPY_GET_INT16U_BIG(addr_dest, addr_src)      do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 1));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
N
N#define  MEM_VAL_COPY_GET_INT32U_BIG(addr_dest, addr_src)      do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 3)); \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 2)); \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) + 2)) = (*(((CPU_INT08U *)(addr_src)) + 1)); \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) + 3)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
X#define  MEM_VAL_COPY_GET_INT32U_BIG(addr_dest, addr_src)      do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 3));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 2));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 2)) = (*(((CPU_INT08U *)(addr_src)) + 1));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 3)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
N
N
N
N#define  MEM_VAL_COPY_GET_INT08U_LITTLE(addr_dest, addr_src)   do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
N
N#define  MEM_VAL_COPY_GET_INT16U_LITTLE(addr_dest, addr_src)   do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0)); \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 1)); } while (0)
X#define  MEM_VAL_COPY_GET_INT16U_LITTLE(addr_dest, addr_src)   do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 1)); } while (0)
N
N#define  MEM_VAL_COPY_GET_INT32U_LITTLE(addr_dest, addr_src)   do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0)); \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 1)); \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) + 2)) = (*(((CPU_INT08U *)(addr_src)) + 2)); \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) + 3)) = (*(((CPU_INT08U *)(addr_src)) + 3)); } while (0)
X#define  MEM_VAL_COPY_GET_INT32U_LITTLE(addr_dest, addr_src)   do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 1));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 2)) = (*(((CPU_INT08U *)(addr_src)) + 2));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 3)) = (*(((CPU_INT08U *)(addr_src)) + 3)); } while (0)
N
N
N
N#define  MEM_VAL_COPY_GET_INT08U(addr_dest, addr_src)               MEM_VAL_COPY_GET_INT08U_LITTLE(addr_dest, addr_src)
N#define  MEM_VAL_COPY_GET_INT16U(addr_dest, addr_src)               MEM_VAL_COPY_GET_INT16U_LITTLE(addr_dest, addr_src)
N#define  MEM_VAL_COPY_GET_INT32U(addr_dest, addr_src)               MEM_VAL_COPY_GET_INT32U_LITTLE(addr_dest, addr_src)
N
N
N
N
N#else                                                               /* See Note #7.                                     */
S
S#error  "CPU_CFG_ENDIAN_TYPE  illegally #defined in 'cpu.h'      "
S#error  "                     [See 'cpu.h  CONFIGURATION ERRORS']"
S
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                     MEM_VAL_COPY_GET_INTU_xxx()
N*
N* Description : Copy & decode data values from any CPU memory address to any CPU memory address for
N*                   any sized data values.
N*
N* Argument(s) : addr_dest       Lowest CPU memory address to copy/decode source address's data value
N*                                   (see Notes #2 & #3).
N*
N*               addr_src        Lowest CPU memory address of data value to copy/decode
N*                                   (see Notes #2 & #3).
N*
N*               val_size        Number of data value octets to copy/decode.
N*
N* Return(s)   : none.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) Copy/decode data values based on the values' data-word order :
N*
N*                       MEM_VAL_COPY_GET_INTU_BIG()     Decode big-   endian data values -- data words' most
N*                                                           significant octet @ lowest memory address
N*                       MEM_VAL_COPY_GET_INTU_LITTLE()  Decode little-endian data values -- data words' least
N*                                                           significant octet @ lowest memory address
N*                       MEM_VAL_COPY_GET_INTU()         Decode data values using CPU's native or configured
N*                                                           data-word order
N*
N*                   See also 'cpu.h  CPU WORD CONFIGURATION  Note #2'.
N*
N*               (2) (a) CPU memory addresses/pointers NOT checked for NULL.
N*
N*                   (b) CPU memory addresses/buffers  NOT checked for overlapping.
N*
N*                       (1) IEEE Std 1003.1, 2004 Edition, Section 'memcpy() : DESCRIPTION' states that
N*                           "copying ... between objects that overlap ... is undefined".
N*
N*               (3) MEM_VAL_COPY_GET_INTU_xxx() macro's copy/decode data values without regard to CPU word-
N*                   aligned addresses.  Thus for processors that require data word alignment, data words
N*                   can be copied/decoded to/from any CPU address, word-aligned or not, without generating
N*                   data-word-alignment exceptions/faults.
N*
N*               (4) MEM_VAL_COPY_GET_xxx() macro's are more efficient than MEM_VAL_COPY_GET_INTU_xxx()
N*                   macro's & SHOULD be used whenever possible.
N*
N*                   See also 'MEM_VAL_COPY_GET_xxx()  Note #4'.
N*
N*               (5) Since octet-order copy/conversion are inverse operations, MEM_VAL_COPY_GET_INTU_xxx() &
N*                   MEM_VAL_COPY_SET_INTU_xxx() macros are inverse, but identical, operations & are provided
N*                   in both forms for semantics & consistency.
N*
N*                   See also 'MEM_VAL_COPY_SET_INTU_xxx()  Note #5'.
N*
N*               (6) MEM_VAL_COPY_GET_INTU_xxx() macro's are NOT atomic operations & MUST NOT be used on any
N*                   non-static (i.e. volatile) variables, registers, hardware, etc.; without the caller of
N*                   the macro's providing some form of additional protection (e.g. mutual exclusion).
N*
N*               (7) MISRA-C 2004 Rule 5.2 states that "identifiers in an inner scope shall not use the same
N*                   name as an indentifier in an outer scope, and therefore hide that identifier".
N*
N*                   Therefore, to avoid possible redeclaration of commonly-used loop counter identifier names,
N*                   'i' & 'j', MEM_VAL_COPY_GET_INTU_xxx() loop counter identifier names are prefixed with a
N*                   single underscore.
N*
N*               (8) The 'CPU_CFG_ENDIAN_TYPE' pre-processor 'else'-conditional code SHOULD never be compiled/
N*                   linked since each 'cpu.h' SHOULD ensure that the CPU data-word-memory order configuration
N*                   constant (CPU_CFG_ENDIAN_TYPE) is configured with an appropriate data-word-memory order
N*                   value (see 'cpu.h  CPU WORD CONFIGURATION  Note #2').  The 'else'-conditional code is
N*                   included as an extra precaution in case 'cpu.h' is incorrectly configured.
N*********************************************************************************************************
N*/
N/*$PAGE*/
N
N#if     (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
X#if     (2u == 1u)
S
S
S#define  MEM_VAL_COPY_GET_INTU_BIG(addr_dest, addr_src, val_size)       do {                                                                                  \
S                                                                            CPU_SIZE_T  _i;                                                                   \
S                                                                                                                                                              \
S                                                                            for (_i = 0; _i < (val_size); _i++) {                                             \
S                                                                                (*(((CPU_INT08U *)(addr_dest)) + _i)) = (*(((CPU_INT08U *)(addr_src)) + _i)); \
S                                                                            }                                                                                 \
S                                                                        } while (0)
X#define  MEM_VAL_COPY_GET_INTU_BIG(addr_dest, addr_src, val_size)       do {                                                                                                                                                              CPU_SIZE_T  _i;                                                                                                                                                                                                                                                                                                             for (_i = 0; _i < (val_size); _i++) {                                                                                                                             (*(((CPU_INT08U *)(addr_dest)) + _i)) = (*(((CPU_INT08U *)(addr_src)) + _i));                                                                             }                                                                                                                                                         } while (0)
S
S
S#define  MEM_VAL_COPY_GET_INTU_LITTLE(addr_dest, addr_src, val_size)    do {                                                                                  \
S                                                                            CPU_SIZE_T  _i;                                                                   \
S                                                                            CPU_SIZE_T  _j;                                                                   \
S                                                                                                                                                              \
S                                                                                                                                                              \
S                                                                            _j = (val_size) - 1;                                                              \
S                                                                                                                                                              \
S                                                                            for (_i = 0; _i < (val_size); _i++) {                                             \
S                                                                                (*(((CPU_INT08U *)(addr_dest)) + _i)) = (*(((CPU_INT08U *)(addr_src)) + _j)); \
S                                                                                _j--;                                                                         \
S                                                                            }                                                                                 \
S                                                                        } while (0)
X#define  MEM_VAL_COPY_GET_INTU_LITTLE(addr_dest, addr_src, val_size)    do {                                                                                                                                                              CPU_SIZE_T  _i;                                                                                                                                               CPU_SIZE_T  _j;                                                                                                                                                                                                                                                                                                                                                                                                                                                                           _j = (val_size) - 1;                                                                                                                                                                                                                                                                                                        for (_i = 0; _i < (val_size); _i++) {                                                                                                                             (*(((CPU_INT08U *)(addr_dest)) + _i)) = (*(((CPU_INT08U *)(addr_src)) + _j));                                                                                 _j--;                                                                                                                                                     }                                                                                                                                                         } while (0)
S
S
S#define  MEM_VAL_COPY_GET_INTU(addr_dest, addr_src, val_size)           MEM_VAL_COPY_GET_INTU_BIG(addr_dest, addr_src, val_size)
S
S
S
S
N#elif   (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_LITTLE)
X#elif   (2u == 2u)
N
N
N#define  MEM_VAL_COPY_GET_INTU_BIG(addr_dest, addr_src, val_size)       do {                                                                                  \
N                                                                            CPU_SIZE_T  _i;                                                                   \
N                                                                            CPU_SIZE_T  _j;                                                                   \
N                                                                                                                                                              \
N                                                                                                                                                              \
N                                                                            _j = (val_size) - 1;                                                              \
N                                                                                                                                                              \
N                                                                            for (_i = 0; _i < (val_size); _i++) {                                             \
N                                                                                (*(((CPU_INT08U *)(addr_dest)) + _i)) = (*(((CPU_INT08U *)(addr_src)) + _j)); \
N                                                                                _j--;                                                                         \
N                                                                            }                                                                                 \
N                                                                        } while (0)
X#define  MEM_VAL_COPY_GET_INTU_BIG(addr_dest, addr_src, val_size)       do {                                                                                                                                                              CPU_SIZE_T  _i;                                                                                                                                               CPU_SIZE_T  _j;                                                                                                                                                                                                                                                                                                                                                                                                                                                                           _j = (val_size) - 1;                                                                                                                                                                                                                                                                                                        for (_i = 0; _i < (val_size); _i++) {                                                                                                                             (*(((CPU_INT08U *)(addr_dest)) + _i)) = (*(((CPU_INT08U *)(addr_src)) + _j));                                                                                 _j--;                                                                                                                                                     }                                                                                                                                                         } while (0)
N
N
N#define  MEM_VAL_COPY_GET_INTU_LITTLE(addr_dest, addr_src, val_size)    do {                                                                                  \
N                                                                            CPU_SIZE_T  _i;                                                                   \
N                                                                                                                                                              \
N                                                                            for (_i = 0; _i < (val_size); _i++) {                                             \
N                                                                                (*(((CPU_INT08U *)(addr_dest)) + _i)) = (*(((CPU_INT08U *)(addr_src)) + _i)); \
N                                                                            }                                                                                 \
N                                                                        } while (0)
X#define  MEM_VAL_COPY_GET_INTU_LITTLE(addr_dest, addr_src, val_size)    do {                                                                                                                                                              CPU_SIZE_T  _i;                                                                                                                                                                                                                                                                                                             for (_i = 0; _i < (val_size); _i++) {                                                                                                                             (*(((CPU_INT08U *)(addr_dest)) + _i)) = (*(((CPU_INT08U *)(addr_src)) + _i));                                                                             }                                                                                                                                                         } while (0)
N
N
N#define  MEM_VAL_COPY_GET_INTU(addr_dest, addr_src, val_size)           MEM_VAL_COPY_GET_INTU_LITTLE(addr_dest, addr_src, val_size)
N
N
N
N
N#else                                                                   /* See Note #8.                                 */
S
S#error  "CPU_CFG_ENDIAN_TYPE  illegally #defined in 'cpu.h'      "
S#error  "                     [See 'cpu.h  CONFIGURATION ERRORS']"
S
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                       MEM_VAL_COPY_SET_xxx()
N*
N* Description : Copy & encode data values from any CPU memory address to any CPU memory address.
N*
N* Argument(s) : addr_dest       Lowest CPU memory address to copy/encode source address's data value
N*                                   (see Notes #2 & #3).
N*
N*               addr_src        Lowest CPU memory address of data value to copy/encode
N*                                   (see Notes #2 & #3).
N*
N* Return(s)   : none.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) Copy/encode data values based on the values' data-word order :
N*
N*                       MEM_VAL_COPY_SET_xxx_BIG()      Encode big-   endian data values -- data words' most
N*                                                           significant octet @ lowest memory address
N*                       MEM_VAL_COPY_SET_xxx_LITTLE()   Encode little-endian data values -- data words' least
N*                                                           significant octet @ lowest memory address
N*                       MEM_VAL_COPY_SET_xxx()          Encode data values using CPU's native or configured
N*                                                           data-word order
N*
N*                   See also 'cpu.h  CPU WORD CONFIGURATION  Note #2'.
N*
N*               (2) (a) CPU memory addresses/pointers NOT checked for NULL.
N*
N*                   (b) CPU memory addresses/buffers  NOT checked for overlapping.
N*
N*                       (1) IEEE Std 1003.1, 2004 Edition, Section 'memcpy() : DESCRIPTION' states that
N*                           "copying ... between objects that overlap ... is undefined".
N*
N*               (3) MEM_VAL_COPY_SET_xxx() macro's copy/encode data values without regard to CPU word-aligned
N*                   addresses.  Thus for processors that require data word alignment, data words can be copied/
N*                   encoded to/from any CPU address, word-aligned or not, without generating data-word-alignment
N*                   exceptions/faults.
N*
N*               (4) MEM_VAL_COPY_SET_xxx() macro's are more efficient than MEM_VAL_SET_xxx() macro's & are
N*                   also independent of CPU data-word-alignment & SHOULD be used whenever possible.
N*
N*                   See also 'MEM_VAL_SET_xxx()  Note #4'.
N*
N*               (5) Since octet-order copy/conversion are inverse operations, MEM_VAL_COPY_GET_xxx() &
N*                   MEM_VAL_COPY_SET_xxx() macros are inverse, but identical, operations & are provided
N*                   in both forms for semantics & consistency.
N*
N*                   See also 'MEM_VAL_COPY_GET_xxx()  Note #5'.
N*
N*               (6) MEM_VAL_COPY_SET_xxx() macro's are NOT atomic operations & MUST NOT be used on any
N*                   non-static (i.e. volatile) variables, registers, hardware, etc.; without the caller
N*                   of the  macro's providing some form of additional protection (e.g. mutual exclusion).
N*********************************************************************************************************
N*/
N
N                                                                        /* See Note #5.                                 */
N#define  MEM_VAL_COPY_SET_INT08U_BIG(addr_dest, addr_src)               MEM_VAL_COPY_GET_INT08U_BIG(addr_dest, addr_src)
N#define  MEM_VAL_COPY_SET_INT16U_BIG(addr_dest, addr_src)               MEM_VAL_COPY_GET_INT16U_BIG(addr_dest, addr_src)
N#define  MEM_VAL_COPY_SET_INT32U_BIG(addr_dest, addr_src)               MEM_VAL_COPY_GET_INT32U_BIG(addr_dest, addr_src)
N
N#define  MEM_VAL_COPY_SET_INT08U_LITTLE(addr_dest, addr_src)            MEM_VAL_COPY_GET_INT08U_LITTLE(addr_dest, addr_src)
N#define  MEM_VAL_COPY_SET_INT16U_LITTLE(addr_dest, addr_src)            MEM_VAL_COPY_GET_INT16U_LITTLE(addr_dest, addr_src)
N#define  MEM_VAL_COPY_SET_INT32U_LITTLE(addr_dest, addr_src)            MEM_VAL_COPY_GET_INT32U_LITTLE(addr_dest, addr_src)
N
N
N#define  MEM_VAL_COPY_SET_INT08U(addr_dest, addr_src)                   MEM_VAL_COPY_GET_INT08U(addr_dest, addr_src)
N#define  MEM_VAL_COPY_SET_INT16U(addr_dest, addr_src)                   MEM_VAL_COPY_GET_INT16U(addr_dest, addr_src)
N#define  MEM_VAL_COPY_SET_INT32U(addr_dest, addr_src)                   MEM_VAL_COPY_GET_INT32U(addr_dest, addr_src)
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                     MEM_VAL_COPY_SET_INTU_xxx()
N*
N* Description : Copy & encode data values from any CPU memory address to any CPU memory address for
N*                   any sized data values.
N*
N* Argument(s) : addr_dest       Lowest CPU memory address to copy/encode source address's data value
N*                                   (see Notes #2 & #3).
N*
N*               addr_src        Lowest CPU memory address of data value to copy/encode
N*                                   (see Notes #2 & #3).
N*
N*               val_size        Number of data value octets to copy/encode.
N*
N* Return(s)   : none.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) Copy/encode data values based on the values' data-word order :
N*
N*                       MEM_VAL_COPY_SET_INTU_BIG()     Encode big-   endian data values -- data words' most
N*                                                           significant octet @ lowest memory address
N*                       MEM_VAL_COPY_SET_INTU_LITTLE()  Encode little-endian data values -- data words' least
N*                                                           significant octet @ lowest memory address
N*                       MEM_VAL_COPY_SET_INTU()         Encode data values using CPU's native or configured
N*                                                           data-word order
N*
N*                   See also 'cpu.h  CPU WORD CONFIGURATION  Note #2'.
N*
N*               (2) (a) CPU memory addresses/pointers NOT checked for NULL.
N*
N*                   (b) CPU memory addresses/buffers  NOT checked for overlapping.
N*
N*                       (1) IEEE Std 1003.1, 2004 Edition, Section 'memcpy() : DESCRIPTION' states that
N*                           "copying ... between objects that overlap ... is undefined".
N*
N*               (3) MEM_VAL_COPY_SET_INTU_xxx() macro's copy/encode data values without regard to CPU word-
N*                   aligned addresses.  Thus for processors that require data word alignment, data words
N*                   can be copied/encoded to/from any CPU address, word-aligned or not, without generating
N*                   data-word-alignment exceptions/faults.
N*
N*               (4) MEM_VAL_COPY_SET_xxx() macro's are more efficient than MEM_VAL_COPY_SET_INTU_xxx()
N*                   macro's & SHOULD be used whenever possible.
N*
N*                   See also 'MEM_VAL_COPY_SET_xxx()  Note #4'.
N*
N*               (5) Since octet-order copy/conversion are inverse operations, MEM_VAL_COPY_GET_INTU_xxx() &
N*                   MEM_VAL_COPY_SET_INTU_xxx() macros are inverse, but identical, operations & are provided
N*                   in both forms for semantics & consistency.
N*
N*                   See also 'MEM_VAL_COPY_GET_INTU_xxx()  Note #5'.
N*
N*               (6) MEM_VAL_COPY_SET_INTU_xxx() macro's are NOT atomic operations & MUST NOT be used on any
N*                   non-static (i.e. volatile) variables, registers, hardware, etc.; without the caller of
N*                   the macro's providing some form of additional protection (e.g. mutual exclusion).
N*********************************************************************************************************
N*/
N
N                                                                        /* See Note #5.                                 */
N#define  MEM_VAL_COPY_SET_INTU_BIG(addr_dest, addr_src, val_size)       MEM_VAL_COPY_GET_INTU_BIG(addr_dest, addr_src, val_size)
N#define  MEM_VAL_COPY_SET_INTU_LITTLE(addr_dest, addr_src, val_size)    MEM_VAL_COPY_GET_INTU_LITTLE(addr_dest, addr_src, val_size)
N#define  MEM_VAL_COPY_SET_INTU(addr_dest, addr_src, val_size)           MEM_VAL_COPY_GET_INTU(addr_dest, addr_src, val_size)
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                         MEM_VAL_COPY_xxx()
N*
N* Description : Copy data values from any CPU memory address to any CPU memory address.
N*
N* Argument(s) : addr_dest       Lowest CPU memory address to copy source address's data value
N*                                   (see Notes #2 & #3).
N*
N*               addr_src        Lowest CPU memory address of data value to copy
N*                                   (see Notes #2 & #3).
N*
N*               val_size        Number of data value octets to copy.
N*
N* Return(s)   : none.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) MEM_VAL_COPY_xxx() macro's copy data values based on CPU's native data-word order.
N*
N*                   See also 'cpu.h  CPU WORD CONFIGURATION  Note #2'.
N*
N*               (2) (a) CPU memory addresses/pointers NOT checked for NULL.
N*
N*                   (b) CPU memory addresses/buffers  NOT checked for overlapping.
N*
N*                       (1) IEEE Std 1003.1, 2004 Edition, Section 'memcpy() : DESCRIPTION' states that
N*                           "copying ... between objects that overlap ... is undefined".
N*
N*               (3) MEM_VAL_COPY_xxx() macro's copy data values without regard to CPU word-aligned addresses.
N*                   Thus for processors that require data word alignment, data words can be copied to/from any
N*                   CPU address, word-aligned or not, without generating data-word-alignment exceptions/faults.
N*
N*               (4) MEM_VAL_COPY_xxx() macro's are more efficient than MEM_VAL_COPY() macro & SHOULD be
N*                   used whenever possible.
N*
N*               (5) MEM_VAL_COPY_xxx() macro's are NOT atomic operations & MUST NOT be used on any non-static
N*                   (i.e. volatile) variables, registers, hardware, etc.; without the caller of the macro's
N*                   providing some form of additional protection (e.g. mutual exclusion).
N*
N*               (6) MISRA-C 2004 Rule 5.2 states that "identifiers in an inner scope shall not use the same
N*                   name as an indentifier in an outer scope, and therefore hide that identifier".
N*
N*                   Therefore, to avoid possible redeclaration of commonly-used loop counter identifier name,
N*                   'i', MEM_VAL_COPY() loop counter identifier name is prefixed with a single underscore.
N*********************************************************************************************************
N*/
N
N#define  MEM_VAL_COPY_08(addr_dest, addr_src)                  do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0)); } while (0)
N
N#define  MEM_VAL_COPY_16(addr_dest, addr_src)                  do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0)); \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 1)); } while (0)
X#define  MEM_VAL_COPY_16(addr_dest, addr_src)                  do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 1)); } while (0)
N
N#define  MEM_VAL_COPY_32(addr_dest, addr_src)                  do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0)); \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 1)); \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) + 2)) = (*(((CPU_INT08U *)(addr_src)) + 2)); \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) + 3)) = (*(((CPU_INT08U *)(addr_src)) + 3)); } while (0)
X#define  MEM_VAL_COPY_32(addr_dest, addr_src)                  do { (*(((CPU_INT08U *)(addr_dest)) + 0)) = (*(((CPU_INT08U *)(addr_src)) + 0));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 1)) = (*(((CPU_INT08U *)(addr_src)) + 1));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 2)) = (*(((CPU_INT08U *)(addr_src)) + 2));                                                                     (*(((CPU_INT08U *)(addr_dest)) + 3)) = (*(((CPU_INT08U *)(addr_src)) + 3)); } while (0)
N
N
N#define  MEM_VAL_COPY(addr_dest, addr_src, val_size)        do {                                                                                \
N                                                                CPU_SIZE_T  _i;                                                                 \
N                                                                                                                                                \
N                                                                for (_i = 0; _i < (val_size); _i++) {                                           \
N                                                                    (*(((CPU_INT08U *)(addr_dest)) +_i)) = (*(((CPU_INT08U *)(addr_src)) +_i)); \
N                                                                }                                                                               \
N                                                            } while (0)
X#define  MEM_VAL_COPY(addr_dest, addr_src, val_size)        do {                                                                                                                                                CPU_SIZE_T  _i;                                                                                                                                                                                                                                                                                 for (_i = 0; _i < (val_size); _i++) {                                                                                                               (*(((CPU_INT08U *)(addr_dest)) +_i)) = (*(((CPU_INT08U *)(addr_src)) +_i));                                                                 }                                                                                                                                           } while (0)
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                         FUNCTION PROTOTYPES
N*********************************************************************************************************
N*/
N
Nvoid               Mem_Init              (       void);
N
N                                                                    /* ---------------- MEM API  FNCTS ---------------- */
Nvoid               Mem_Clr               (       void              *pmem,
N                                                 CPU_SIZE_T         size);
N
Nvoid               Mem_Set               (       void              *pmem,
N                                                 CPU_INT08U         data_val,
N                                                 CPU_SIZE_T         size);
N
Nvoid               Mem_Copy              (       void              *pdest,
N                                          const  void              *psrc,
N                                                 CPU_SIZE_T         size);
N
Nvoid               Mem_Move              (       void              *pdest,
N                                          const  void              *psrc,
N                                                 CPU_SIZE_T         size);
N
NCPU_BOOLEAN        Mem_Cmp               (const  void              *p1_mem,
N                                          const  void              *p2_mem,
N                                                 CPU_SIZE_T         size);
N
N
N
N#if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)                           /* ---------------- MEM POOL FNCTS ---------------- */
X#if (1u == 1u)                            
N
Nvoid              *Mem_HeapAlloc         (       CPU_SIZE_T         size,
N                                                 CPU_SIZE_T         align,
N                                                 CPU_SIZE_T        *poctets_reqd,
N                                                 LIB_ERR           *perr);
N
NCPU_SIZE_T         Mem_HeapGetSizeRem    (       CPU_SIZE_T         align,
N                                                 LIB_ERR           *perr);
N
N
NCPU_SIZE_T         Mem_SegGetSizeRem     (       MEM_POOL          *pmem_pool,
N                                                 CPU_SIZE_T         align,
N                                                 LIB_ERR           *perr);
N
N
Nvoid               Mem_PoolClr           (       MEM_POOL          *pmem_pool,
N                                                 LIB_ERR           *perr);
N
Nvoid               Mem_PoolCreate        (       MEM_POOL          *pmem_pool,
N                                                 void              *pmem_base_addr,
N                                                 CPU_SIZE_T         mem_size,
N                                                 MEM_POOL_BLK_QTY   blk_nbr,
N                                                 CPU_SIZE_T         blk_size,
N                                                 CPU_SIZE_T         blk_align,
N                                                 CPU_SIZE_T        *poctets_reqd,
N                                                 LIB_ERR           *perr);
N
N
NMEM_POOL_BLK_QTY   Mem_PoolBlkGetNbrAvail(       MEM_POOL          *pmem_pool,
N                                                 LIB_ERR           *perr);
N
Nvoid              *Mem_PoolBlkGet        (       MEM_POOL          *pmem_pool,
N                                                 CPU_SIZE_T         size,
N                                                 LIB_ERR           *perr);
N
Nvoid              *Mem_PoolBlkGetUsedAtIx(       MEM_POOL          *pmem_pool,
N                                                 MEM_POOL_IX        used_ix,
N                                                 LIB_ERR           *perr);
N
Nvoid               Mem_PoolBlkFree       (       MEM_POOL          *pmem_pool,
N                                                 void              *pmem_blk,
N                                                 LIB_ERR           *perr);
N
NMEM_POOL_IX        Mem_PoolBlkIxGet      (       MEM_POOL          *pmem_pool,
N                                                 void              *pmem_blk,
N                                                 LIB_ERR           *perr);
N
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                        CONFIGURATION ERRORS
N*********************************************************************************************************
N*/
N
N#ifndef  LIB_MEM_CFG_ARG_CHK_EXT_EN
S#error  "LIB_MEM_CFG_ARG_CHK_EXT_EN         not #define'd in 'lib_cfg.h'"
S#error  "                             [MUST be  DEF_DISABLED]           "
S#error  "                             [     ||  DEF_ENABLED ]           "
S
S#elif  ((LIB_MEM_CFG_ARG_CHK_EXT_EN != DEF_DISABLED) && \
S        (LIB_MEM_CFG_ARG_CHK_EXT_EN != DEF_ENABLED ))
X#elif  ((1u != 0u) &&         (1u != 1u ))
S#error  "LIB_MEM_CFG_ARG_CHK_EXT_EN   illegally #define'd in 'lib_cfg.h'"
S#error  "                             [MUST be  DEF_DISABLED]           "
S#error  "                             [     ||  DEF_ENABLED ]           "
N#endif
N
N
N
N#ifndef  LIB_MEM_CFG_OPTIMIZE_ASM_EN
S#error  "LIB_MEM_CFG_OPTIMIZE_ASM_EN        not #define'd in 'lib_cfg.h'"
S#error  "                             [MUST be  DEF_DISABLED]           "
S#error  "                             [     ||  DEF_ENABLED ]           "
S
S#elif  ((LIB_MEM_CFG_OPTIMIZE_ASM_EN != DEF_DISABLED) && \
S        (LIB_MEM_CFG_OPTIMIZE_ASM_EN != DEF_ENABLED ))
X#elif  ((1u != 0u) &&         (1u != 1u ))
S#error  "LIB_MEM_CFG_OPTIMIZE_ASM_EN  illegally #define'd in 'lib_cfg.h'"
S#error  "                             [MUST be  DEF_DISABLED]           "
S#error  "                             [     ||  DEF_ENABLED ]           "
N#endif
N
N
N
N
N#ifndef  LIB_MEM_CFG_ALLOC_EN
S#error  "LIB_MEM_CFG_ALLOC_EN               not #define'd in 'lib_cfg.h'"
S#error  "                             [MUST be  DEF_DISABLED]           "
S#error  "                             [     ||  DEF_ENABLED ]           "
S
S#elif  ((LIB_MEM_CFG_ALLOC_EN != DEF_DISABLED) && \
S        (LIB_MEM_CFG_ALLOC_EN != DEF_ENABLED ))
X#elif  ((1u != 0u) &&         (1u != 1u ))
S#error  "LIB_MEM_CFG_ALLOC_EN         illegally #define'd in 'lib_cfg.h'"
S#error  "                             [MUST be  DEF_DISABLED]           "
S#error  "                             [     ||  DEF_ENABLED ]           "
S
S
N#elif   (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
X#elif   (1u == 1u)
N
N
N#ifndef  LIB_MEM_CFG_HEAP_SIZE
S#error  "LIB_MEM_CFG_HEAP_SIZE              not #define'd in 'lib_cfg.h'"
S#error  "                             [MUST be  > 0]                    "
S
S#elif   (DEF_CHK_VAL_MIN(LIB_MEM_CFG_HEAP_SIZE, 1) != DEF_OK)
X#elif   ((((!(((23u * 1024u) >= 1) && ((1) < 1))) && ((((1) >= 1) && ((23u * 1024u) < 1)) || ((23u * 1024u) < (1)))) ? 0u : 1u) != 1u)
S#error  "LIB_MEM_CFG_HEAP_SIZE        illegally #define'd in 'lib_cfg.h'"
S#error  "                             [MUST be  > 0]                    "
N#endif
N
N
N#ifdef   LIB_MEM_CFG_HEAP_BASE_ADDR
S#if     (LIB_MEM_CFG_HEAP_BASE_ADDR == 0x0)
S#error  "LIB_MEM_CFG_HEAP_BASE_ADDR   illegally #define'd in 'lib_cfg.h'"
S#error  "                             [MUST be  > 0x0]                  "
S#endif
N#endif
N
N
N#endif
N
N
N/*
N*********************************************************************************************************
N*                                    LIBRARY CONFIGURATION ERRORS
N*********************************************************************************************************
N*/
N
N                                                                /* See 'lib_mem.h  Note #2a'.                           */
N#if     (CPU_CORE_VERSION < 127u)
X#if     (12901u < 127u)
S#error  "CPU_CORE_VERSION  [SHOULD be >= V1.27]"
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                             MODULE END
N*
N* Note(s) : (1) See 'lib_mem.h  MODULE'.
N*********************************************************************************************************
N*/
N
N#endif                                                          /* End of lib mem module include.                       */
N
L 110 "..\..\uCOS-III\uC-CPU\cpu_core.h" 2
N#include  <lib_str.h>
L 1 "..\..\uCOS-III\uC-LIB\lib_str.h" 1
N/*
N*********************************************************************************************************
N*                                                uC/LIB
N*                                        CUSTOM LIBRARY MODULES
N*
N*                          (c) Copyright 2004-2012; Micrium, Inc.; Weston, FL
N*
N*               All rights reserved.  Protected by international copyright laws.
N*
N*               uC/LIB is provided in source form to registered licensees ONLY.  It is 
N*               illegal to distribute this source code to any third party unless you receive 
N*               written permission by an authorized Micrium representative.  Knowledge of 
N*               the source code may NOT be used to develop a similar product.
N*
N*               Please help us continue to provide the Embedded community with the finest 
N*               software available.  Your honesty is greatly appreciated.
N*
N*               You can contact us at www.micrium.com.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*
N*                                       ASCII STRING MANAGEMENT
N*
N* Filename      : lib_str.h
N* Version       : V1.37.01
N* Programmer(s) : ITJ
N*                 JDH
N*********************************************************************************************************
N* Note(s)       : (1) NO compiler-supplied standard library functions are used in library or product software.
N*
N*                     (a) ALL standard library functions are implemented in the custom library modules :
N*
N*                         (1) \<Custom Library Directory>\lib_*.*
N*
N*                         (2) \<Custom Library Directory>\Ports\<cpu>\<compiler>\lib*_a.*
N*
N*                               where
N*                                       <Custom Library Directory>      directory path for custom library software
N*                                       <cpu>                           directory name for specific processor (CPU)
N*                                       <compiler>                      directory name for specific compiler
N*
N*                     (b) Product-specific library functions are implemented in individual products.
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                               MODULE
N*
N* Note(s) : (1) This string library header file is protected from multiple pre-processor inclusion through 
N*               use of the string library module present pre-processor macro definition.
N*********************************************************************************************************
N*/
N
N#ifndef  LIB_STR_MODULE_PRESENT                                 /* See Note #1.                                         */
N#define  LIB_STR_MODULE_PRESENT
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                 ASCII STRING CONFIGURATION DEFINES
N*
N* Note(s) : (1) Some ASCII string configuration #define's MUST be available PRIOR to including any 
N*               application configuration (see 'INCLUDE FILES  Note #1a').
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                    STRING FLOATING POINT DEFINES
N*
N* Note(s) : (1) (a) (1) The maximum accuracy for 32-bit floating-point numbers :
N*
N*
N*                             Maximum Accuracy            log [Internal-Base ^ (Number-Internal-Base-Digits)]
N*                       32-bit Floating-point Number  =  -----------------------------------------------------
N*                                                                         log [External-Base]
N*
N*                                                         log [2 ^ 24]
N*                                                     =  --------------
N*                                                           log [10]
N*
N*                                                     <  7.225  Base-10 Digits
N*
N*                           where
N*                                   Internal-Base                   Internal number base of floating-
N*                                                                       point numbers (i.e.  2)
N*                                   External-Base                   External number base of floating-
N*                                                                       point numbers (i.e. 10)
N*                                   Number-Internal-Base-Digits     Number of internal number base
N*                                                                       significant digits (i.e. 24)
N*
N*                   (2) Also, since some 32-bit floating-point calculations are converted to 32-bit 
N*                       unsigned numbers, the maximum accuracy is limited to the maximum accuracy
N*                       for 32-bit unsigned numbers of 9 digits.
N*
N*               (b) Some CPUs' &/or compilers' floating-point implementations MAY further reduce the 
N*                   maximum accuracy.
N*********************************************************************************************************
N*/
N
N#define  LIB_STR_FP_MAX_NBR_DIG_SIG_MIN                    1u
N#define  LIB_STR_FP_MAX_NBR_DIG_SIG_MAX                    9u   /* See Note #1a2.                                       */
N#define  LIB_STR_FP_MAX_NBR_DIG_SIG_DFLT                   7u   /* See Note #1a1.                                       */
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                            INCLUDE FILES
N*
N* Note(s) : (1) The custom library software files are located in the following directories :
N*
N*               (a) \<Your Product Application>\lib_cfg.h
N*
N*               (b) \<Custom Library Directory>\lib_*.*
N*
N*                       where
N*                               <Your Product Application>      directory path for Your Product's Application
N*                               <Custom Library Directory>      directory path for custom library software
N*
N*           (2) CPU-configuration  software files are located in the following directories :
N*
N*               (a) \<CPU-Compiler Directory>\cpu_*.*
N*               (b) \<CPU-Compiler Directory>\<cpu>\<compiler>\cpu*.*
N*
N*                       where
N*                               <CPU-Compiler Directory>        directory path for common CPU-compiler software
N*                               <cpu>                           directory name for specific processor (CPU)
N*                               <compiler>                      directory name for specific compiler
N*
N*           (3) Compiler MUST be configured to include as additional include path directories :
N*
N*               (a) '\<Your Product Application>\' directory                            See Note #1a
N*
N*               (b) '\<Custom Library Directory>\' directory                            See Note #1b
N*
N*               (c) (1) '\<CPU-Compiler Directory>\'                  directory         See Note #2a
N*                   (2) '\<CPU-Compiler Directory>\<cpu>\<compiler>\' directory         See Note #2b
N*
N*           (4) NO compiler-supplied standard library functions SHOULD be used.
N*
N*               #### The reference to standard library header files SHOULD be removed once all custom
N*               library functions are implemented WITHOUT reference to ANY standard library function(s).
N*
N*               See also 'STANDARD LIBRARY MACRO'S  Note #1'.
N*********************************************************************************************************
N*/
N
N#include  <cpu.h>
N
N#include  <lib_def.h>
N#include  <lib_ascii.h>
L 1 "..\..\uCOS-III\uC-LIB\lib_ascii.h" 1
N/*
N*********************************************************************************************************
N*                                                uC/LIB
N*                                        CUSTOM LIBRARY MODULES
N*
N*                          (c) Copyright 2004-2012; Micrium, Inc.; Weston, FL
N*
N*               All rights reserved.  Protected by international copyright laws.
N*
N*               uC/LIB is provided in source form to registered licensees ONLY.  It is 
N*               illegal to distribute this source code to any third party unless you receive 
N*               written permission by an authorized Micrium representative.  Knowledge of 
N*               the source code may NOT be used to develop a similar product.
N*
N*               Please help us continue to provide the Embedded community with the finest 
N*               software available.  Your honesty is greatly appreciated.
N*
N*               You can contact us at www.micrium.com.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*
N*                                     ASCII CHARACTER OPERATIONS
N*
N* Filename      : lib_ascii.h
N* Version       : V1.37.01
N* Programmer(s) : BAN
N*********************************************************************************************************
N* Note(s)       : (1) NO compiler-supplied standard library functions are used in library or product software.
N*
N*                     (a) ALL standard library functions are implemented in the custom library modules :
N*
N*                         (1) \<Custom Library Directory>\lib_*.*
N*
N*                         (2) \<Custom Library Directory>\Ports\<cpu>\<compiler>\lib*_a.*
N*
N*                               where
N*                                       <Custom Library Directory>      directory path for custom library software
N*                                       <cpu>                           directory name for specific processor (CPU)
N*                                       <compiler>                      directory name for specific compiler
N*
N*                     (b) Product-specific library functions are implemented in individual products.
N*
N*
N*                 (2) (a) ECMA-6 '7-Bit coded Character Set' (6th edition), which corresponds to the
N*                         3rd edition of ISO 646, specifies several versions of a 7-bit character set :
N*
N*                         (1) THE GENERAL VERSION, which allows characters at 0x23 and 0x24 to be given a
N*                             set alternate form and allows the characters 0x40, 0x5B, 0x5D, 0x60, 0x7B &
N*                             0x7D to be assigned a "unique graphic character" or to be declared as unused.
N*                             All other characters are explicitly specified.
N*
N*                         (2) THE INTERNATIONAL REFERENCE VERSION, which explicitly specifies all characters
N*                             in the 7-bit character set.
N*
N*                         (3) NATIONAL & APPLICATION-ORIENTED VERSIONS, which may be derived from the
N*                             standard in specified ways.
N*
N*                     (b) The character set represented in this file reproduces the Internation Reference
N*                         Version.  This is identical to the 7-bit character set which occupies Unicode
N*                         characters 0x0000 through 0x007F.  The character names are taken from v5.0 of the
N*                         Unicode specification, with certain abbreviations so that the resulting #define
N*                         names will not violate ANSI C naming restriction :
N*
N*                         (1) For the Latin capital & lowercase letters, the name components 'LETTER_CAPITAL'
N*                             & 'LETTER_SMALL' are replaced by 'UPPER' & 'LOWER', respectively.
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                               MODULE
N*
N* Note(s) : (1) This ASCII library header file is protected from multiple pre-processor inclusion through 
N*               use of the ASCII library module present pre-processor macro definition.
N*********************************************************************************************************
N*/
N
N#ifndef  LIB_ASCII_MODULE_PRESENT                               /* See Note #1.                                         */
N#define  LIB_ASCII_MODULE_PRESENT
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                            INCLUDE FILES
N*
N* Note(s) : (1) The custom library software files are located in the following directories :
N*
N*               (a) \<Custom Library Directory>\lib_*.*
N*
N*                       where
N*                               <Custom Library Directory>      directory path for custom library software
N*
N*           (2) CPU-configuration  software files are located in the following directories :
N*
N*               (a) \<CPU-Compiler Directory>\cpu_*.*
N*               (b) \<CPU-Compiler Directory>\<cpu>\<compiler>\cpu*.*
N*
N*                       where
N*                               <CPU-Compiler Directory>        directory path for common CPU-compiler software
N*                               <cpu>                           directory name for specific processor (CPU)
N*                               <compiler>                      directory name for specific compiler
N*
N*           (3) Compiler MUST be configured to include as additional include path directories :
N*
N*               (a) '\<Custom Library Directory>\' directory                            See Note #1a
N*
N*               (b) (1) '\<CPU-Compiler Directory>\'                  directory         See Note #2a
N*                   (2) '\<CPU-Compiler Directory>\<cpu>\<compiler>\' directory         See Note #2b
N*
N*           (4) NO compiler-supplied standard library functions SHOULD be used.
N*********************************************************************************************************
N*/
N
N#include  <cpu.h>
N#include  <lib_def.h>
N
N
N/*
N*********************************************************************************************************
N*                                               EXTERNS
N*********************************************************************************************************
N*/
N
N#ifdef   LIB_ASCII_MODULE
S#define  LIB_ASCII_EXT
N#else
N#define  LIB_ASCII_EXT  extern
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                               DEFINES
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                         ASCII CHARACTER DEFINES
N*********************************************************************************************************
N*/
N
N                                                                /* -------------------- C0 CONTROLS ------------------- */
N#define  ASCII_CHAR_NULL                                0x00    /* '\0'                                                 */
N#define  ASCII_CHAR_START_OF_HEADING                    0x01
N#define  ASCII_CHAR_START_OF_TEXT                       0x02
N#define  ASCII_CHAR_END_OF_TEXT                         0x03
N#define  ASCII_CHAR_END_OF_TRANSMISSION                 0x04
N#define  ASCII_CHAR_ENQUIRY                             0x05
N#define  ASCII_CHAR_ACKNOWLEDGE                         0x06
N#define  ASCII_CHAR_BELL                                0x07    /* '\a'                                                 */
N#define  ASCII_CHAR_BACKSPACE                           0x08    /* '\b'                                                 */
N#define  ASCII_CHAR_CHARACTER_TABULATION                0x09    /* '\t'                                                 */
N#define  ASCII_CHAR_LINE_FEED                           0x0A    /* '\n'                                                 */
N#define  ASCII_CHAR_LINE_TABULATION                     0x0B    /* '\v'                                                 */
N#define  ASCII_CHAR_FORM_FEED                           0x0C    /* '\f'                                                 */
N#define  ASCII_CHAR_CARRIAGE_RETURN                     0x0D    /* '\r'                                                 */
N#define  ASCII_CHAR_SHIFT_OUT                           0x0E
N#define  ASCII_CHAR_SHIFT_IN                            0x0F
N#define  ASCII_CHAR_DATA_LINK_ESCAPE                    0x10
N#define  ASCII_CHAR_DEVICE_CONTROL_ONE                  0x11
N#define  ASCII_CHAR_DEVICE_CONTROL_TWO                  0x12
N#define  ASCII_CHAR_DEVICE_CONTROL_THREE                0x13
N#define  ASCII_CHAR_DEVICE_CONTROL_FOUR                 0x14
N#define  ASCII_CHAR_NEGATIVE_ACKNOWLEDGE                0x15
N#define  ASCII_CHAR_SYNCHRONOUS_IDLE                    0x16
N#define  ASCII_CHAR_END_OF_TRANSMISSION_BLOCK           0x17
N#define  ASCII_CHAR_CANCEL                              0x18
N#define  ASCII_CHAR_END_OF_MEDIUM                       0x19
N#define  ASCII_CHAR_SUBSITUTE                           0x1A
N#define  ASCII_CHAR_ESCAPE                              0x1B
N#define  ASCII_CHAR_INFO_SEPARATOR_FOUR                 0x1C
N#define  ASCII_CHAR_INFO_SEPARATOR_THREE                0x1D
N#define  ASCII_CHAR_INFO_SEPARATOR_TWO                  0x1E
N#define  ASCII_CHAR_INFO_SEPARATOR_ONE                  0x1F
N
N#define  ASCII_CHAR_NUL                                 ASCII_CHAR_NULL
N#define  ASCII_CHAR_SOH                                 ASCII_CHAR_START_OF_HEADING
N#define  ASCII_CHAR_START_HEADING                       ASCII_CHAR_START_OF_HEADING
N#define  ASCII_CHAR_STX                                 ASCII_CHAR_START_OF_TEXT
N#define  ASCII_CHAR_START_TEXT                          ASCII_CHAR_START_OF_TEXT
N#define  ASCII_CHAR_ETX                                 ASCII_CHAR_END_OF_TEXT
N#define  ASCII_CHAR_END_TEXT                            ASCII_CHAR_END_OF_TEXT
N#define  ASCII_CHAR_EOT                                 ASCII_CHAR_END_OF_TRANSMISSION
N#define  ASCII_CHAR_END_TRANSMISSION                    ASCII_CHAR_END_OF_TRANSMISSION
N#define  ASCII_CHAR_ENQ                                 ASCII_CHAR_ENQUIRY
N#define  ASCII_CHAR_ACK                                 ASCII_CHAR_ACKNOWLEDGE
N#define  ASCII_CHAR_BEL                                 ASCII_CHAR_BELL
N#define  ASCII_CHAR_BS                                  ASCII_CHAR_BACKSPACE
N#define  ASCII_CHAR_HT                                  ASCII_CHAR_CHARACTER_TABULATION
N#define  ASCII_CHAR_TAB                                 ASCII_CHAR_CHARACTER_TABULATION
N#define  ASCII_CHAR_LF                                  ASCII_CHAR_LINE_FEED
N#define  ASCII_CHAR_VT                                  ASCII_CHAR_LINE_TABULATION
N#define  ASCII_CHAR_FF                                  ASCII_CHAR_FORM_FEED
N#define  ASCII_CHAR_CR                                  ASCII_CHAR_CARRIAGE_RETURN
N#define  ASCII_CHAR_SO                                  ASCII_CHAR_SHIFT_OUT
N#define  ASCII_CHAR_SI                                  ASCII_CHAR_SHIFT_IN
N#define  ASCII_CHAR_DLE                                 ASCII_CHAR_DATA_LINK_ESCAPE
N#define  ASCII_CHAR_DC1                                 ASCII_CHAR_DEVICE_CONTROL_ONE
N#define  ASCII_CHAR_DC2                                 ASCII_CHAR_DEVICE_CONTROL_TWO
N#define  ASCII_CHAR_DC3                                 ASCII_CHAR_DEVICE_CONTROL_THREE
N#define  ASCII_CHAR_DC4                                 ASCII_CHAR_DEVICE_CONTROL_FOUR
N#define  ASCII_CHAR_DEV_CTRL_ONE                        ASCII_CHAR_DEVICE_CONTROL_ONE
N#define  ASCII_CHAR_DEV_CTRL_TWO                        ASCII_CHAR_DEVICE_CONTROL_TWO
N#define  ASCII_CHAR_DEV_CTRL_THREE                      ASCII_CHAR_DEVICE_CONTROL_THREE
N#define  ASCII_CHAR_DEV_CTRL_FOUR                       ASCII_CHAR_DEVICE_CONTROL_FOUR
N#define  ASCII_CHAR_NAK                                 ASCII_CHAR_NEGATIVE_ACKNOWLEDGE
N#define  ASCII_CHAR_NEG_ACK                             ASCII_CHAR_NEGATIVE_ACKNOWLEDGE
N#define  ASCII_CHAR_SYN                                 ASCII_CHAR_SYNCHRONOUS_IDLE
N#define  ASCII_CHAR_SYNC_IDLE                           ASCII_CHAR_SYNCHRONOUS_IDLE
N#define  ASCII_CHAR_ETB                                 ASCII_CHAR_END_OF_TRANSMISSION_BLOCK
N#define  ASCII_CHAR_END_TRANSMISSION_BLK                ASCII_CHAR_END_OF_TRANSMISSION_BLOCK
N#define  ASCII_CHAR_CAN                                 ASCII_CHAR_CANCEL
N#define  ASCII_CHAR_EM                                  ASCII_CHAR_END_OF_MEDIUM
N#define  ASCII_CHAR_END_MEDIUM                          ASCII_CHAR_END_OF_MEDIUM
N#define  ASCII_CHAR_SUB                                 ASCII_CHAR_SUBSITUTE
N#define  ASCII_CHAR_ESC                                 ASCII_CHAR_ESCAPE
N#define  ASCII_CHAR_IS1                                 ASCII_CHAR_INFO_SEPARATOR_ONE
N#define  ASCII_CHAR_IS2                                 ASCII_CHAR_INFO_SEPARATOR_TWO
N#define  ASCII_CHAR_IS3                                 ASCII_CHAR_INFO_SEPARATOR_THREE
N#define  ASCII_CHAR_IS4                                 ASCII_CHAR_INFO_SEPARATOR_FOUR
N
N
N/*$PAGE*/
N                                                                /* ------------ ASCII PUNCTUATION & SYMBOLS ----------- */
N#define  ASCII_CHAR_SPACE                               0x20    /* ' '                                                  */
N#define  ASCII_CHAR_EXCLAMATION_MARK                    0x21    /* '!'                                                  */
N#define  ASCII_CHAR_QUOTATION_MARK                      0x22    /* '\"'                                                 */
N#define  ASCII_CHAR_NUMBER_SIGN                         0x23    /* '#'                                                  */
N#define  ASCII_CHAR_DOLLAR_SIGN                         0x24    /* '$'                                                  */
N#define  ASCII_CHAR_PERCENTAGE_SIGN                     0x25    /* '%'                                                  */
N#define  ASCII_CHAR_AMPERSAND                           0x26    /* '&'                                                  */
N#define  ASCII_CHAR_APOSTROPHE                          0x27    /* '\''                                                 */
N#define  ASCII_CHAR_LEFT_PARENTHESIS                    0x28    /* '('                                                  */
N#define  ASCII_CHAR_RIGHT_PARENTHESIS                   0x29    /* ')'                                                  */
N#define  ASCII_CHAR_ASTERISK                            0x2A    /* '*'                                                  */
N#define  ASCII_CHAR_PLUS_SIGN                           0x2B    /* '+'                                                  */
N#define  ASCII_CHAR_COMMA                               0x2C    /* ','                                                  */
N#define  ASCII_CHAR_HYPHEN_MINUS                        0x2D    /* '-'                                                  */
N#define  ASCII_CHAR_FULL_STOP                           0x2E    /* '.'                                                  */
N#define  ASCII_CHAR_SOLIDUS                             0x2F    /* '/'                                                  */
N
N#define  ASCII_CHAR_PAREN_LEFT                          ASCII_CHAR_LEFT_PARENTHESIS
N#define  ASCII_CHAR_PAREN_RIGHT                         ASCII_CHAR_RIGHT_PARENTHESIS
N
N
N                                                                /* ------------------- ASCII DIGITS ------------------- */
N#define  ASCII_CHAR_DIGIT_ZERO                          0x30    /* '0'                                                  */
N#define  ASCII_CHAR_DIGIT_ONE                           0x31    /* '1'                                                  */
N#define  ASCII_CHAR_DIGIT_TWO                           0x32    /* '2'                                                  */
N#define  ASCII_CHAR_DIGIT_THREE                         0x33    /* '3'                                                  */
N#define  ASCII_CHAR_DIGIT_FOUR                          0x34    /* '4'                                                  */
N#define  ASCII_CHAR_DIGIT_FIVE                          0x35    /* '5'                                                  */
N#define  ASCII_CHAR_DIGIT_SIX                           0x36    /* '6'                                                  */
N#define  ASCII_CHAR_DIGIT_SEVEN                         0x37    /* '7'                                                  */
N#define  ASCII_CHAR_DIGIT_EIGHT                         0x38    /* '8'                                                  */
N#define  ASCII_CHAR_DIGIT_NINE                          0x39    /* '9'                                                  */
N
N#define  ASCII_CHAR_DIG_ZERO                            ASCII_CHAR_DIGIT_ZERO
N#define  ASCII_CHAR_DIG_ONE                             ASCII_CHAR_DIGIT_ONE
N#define  ASCII_CHAR_DIG_TWO                             ASCII_CHAR_DIGIT_TWO
N#define  ASCII_CHAR_DIG_THREE                           ASCII_CHAR_DIGIT_THREE
N#define  ASCII_CHAR_DIG_FOUR                            ASCII_CHAR_DIGIT_FOUR
N#define  ASCII_CHAR_DIG_FIVE                            ASCII_CHAR_DIGIT_FIVE
N#define  ASCII_CHAR_DIG_SIX                             ASCII_CHAR_DIGIT_SIX
N#define  ASCII_CHAR_DIG_SEVEN                           ASCII_CHAR_DIGIT_SEVEN
N#define  ASCII_CHAR_DIG_EIGHT                           ASCII_CHAR_DIGIT_EIGHT
N#define  ASCII_CHAR_DIG_NINE                            ASCII_CHAR_DIGIT_NINE
N
N
N                                                                /* ------------ ASCII PUNCTUATION & SYMBOLS ----------- */
N#define  ASCII_CHAR_COLON                               0x3A    /* ':'                                                  */
N#define  ASCII_CHAR_SEMICOLON                           0x3B    /* ';'                                                  */
N#define  ASCII_CHAR_LESS_THAN_SIGN                      0x3C    /* '<'                                                  */
N#define  ASCII_CHAR_EQUALS_SIGN                         0x3D    /* '='                                                  */
N#define  ASCII_CHAR_GREATER_THAN_SIGN                   0x3E    /* '>'                                                  */
N#define  ASCII_CHAR_QUESTION_MARK                       0x3F    /* '\?'                                                 */
N#define  ASCII_CHAR_COMMERCIAL_AT                       0x40    /* '@'                                                  */
N
N#define  ASCII_CHAR_AT_SIGN                             ASCII_CHAR_COMMERCIAL_AT
N
N
N/*$PAGE*/
N                                                                /* ------------- UPPERCASE LATIN ALPHABET ------------- */
N#define  ASCII_CHAR_LATIN_UPPER_A                       0x41    /* 'A'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_B                       0x42    /* 'B'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_C                       0x43    /* 'C'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_D                       0x44    /* 'D'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_E                       0x45    /* 'E'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_F                       0x46    /* 'F'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_G                       0x47    /* 'G'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_H                       0x48    /* 'H'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_I                       0x49    /* 'I'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_J                       0x4A    /* 'J'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_K                       0x4B    /* 'K'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_L                       0x4C    /* 'L'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_M                       0x4D    /* 'M'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_N                       0x4E    /* 'N'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_O                       0x4F    /* 'O'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_P                       0x50    /* 'P'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_Q                       0x51    /* 'Q'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_R                       0x52    /* 'R'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_S                       0x53    /* 'S'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_T                       0x54    /* 'T'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_U                       0x55    /* 'U'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_V                       0x56    /* 'V'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_W                       0x57    /* 'W'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_X                       0x58    /* 'X'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_Y                       0x59    /* 'Y'                                                  */
N#define  ASCII_CHAR_LATIN_UPPER_Z                       0x5A    /* 'Z'                                                  */
N
N
N                                                                /* ------------ ASCII PUNCTUATION & SYMBOLS ----------- */
N#define  ASCII_CHAR_LEFT_SQUARE_BRACKET                 0x5B    /* '['                                                  */
N#define  ASCII_CHAR_REVERSE_SOLIDUS                     0x5C    /* '\\'                                                 */
N#define  ASCII_CHAR_RIGHT_SQUARE_BRACKET                0x5D    /* ']'                                                  */
N#define  ASCII_CHAR_CIRCUMFLEX_ACCENT                   0x5E    /* '^'                                                  */
N#define  ASCII_CHAR_LOW_LINE                            0x5F    /* '_'                                                  */
N#define  ASCII_CHAR_GRAVE_ACCENT                        0x60    /* '`'                                                  */
N
N#define  ASCII_CHAR_BRACKET_SQUARE_LEFT                 ASCII_CHAR_LEFT_SQUARE_BRACKET
N#define  ASCII_CHAR_BRACKET_SQUARE_RIGHT                ASCII_CHAR_RIGHT_SQUARE_BRACKET
N
N
N                                                                /* ------------- LOWERCASE LATIN ALPHABET ------------- */
N#define  ASCII_CHAR_LATIN_LOWER_A                       0x61    /* 'a'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_B                       0x62    /* 'b'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_C                       0x63    /* 'c'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_D                       0x64    /* 'd'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_E                       0x65    /* 'e'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_F                       0x66    /* 'f'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_G                       0x67    /* 'g'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_H                       0x68    /* 'h'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_I                       0x69    /* 'i'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_J                       0x6A    /* 'j'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_K                       0x6B    /* 'k'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_L                       0x6C    /* 'l'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_M                       0x6D    /* 'm'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_N                       0x6E    /* 'n'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_O                       0x6F    /* 'o'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_P                       0x70    /* 'p'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_Q                       0x71    /* 'q'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_R                       0x72    /* 'r'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_S                       0x73    /* 's'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_T                       0x74    /* 't'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_U                       0x75    /* 'u'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_V                       0x76    /* 'v'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_W                       0x77    /* 'w'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_X                       0x78    /* 'x'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_Y                       0x79    /* 'y'                                                  */
N#define  ASCII_CHAR_LATIN_LOWER_Z                       0x7A    /* 'z'                                                  */
N
N
N                                                                /* ------------ ASCII PUNCTUATION & SYMBOLS ----------- */
N#define  ASCII_CHAR_LEFT_CURLY_BRACKET                  0x7B    /* '{'                                                  */
N#define  ASCII_CHAR_VERTICAL_LINE                       0x7C    /* '|'                                                  */
N#define  ASCII_CHAR_RIGHT_CURLY_BRACKET                 0x7D    /* '}'                                                  */
N#define  ASCII_CHAR_TILDE                               0x7E    /* '~'                                                  */
N
N#define  ASCII_CHAR_BRACKET_CURLY_LEFT                  ASCII_CHAR_LEFT_CURLY_BRACKET
N#define  ASCII_CHAR_BRACKET_CURLY_RIGHT                 ASCII_CHAR_RIGHT_CURLY_BRACKET
N
N
N                                                                /* ---------------- CONTROL CHARACTERS ---------------- */
N#define  ASCII_CHAR_DELETE                              0x7F
N
N#define  ASCII_CHAR_DEL                                 ASCII_CHAR_DELETE
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                             DATA TYPES
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                          GLOBAL VARIABLES
N*********************************************************************************************************
N*/
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                              MACRO'S
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                               ASCII CHARACTER CLASSIFICATION MACRO's
N*
N* Note(s) : (1) ISO/IEC 9899:TC2, Section 7.4.1.(1) states that "character classification functions ...
N*               return nonzero (true) if and only if the value of the argument 'c' conforms to ... the
N*               description of the function."
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                           ASCII_IS_DIG()
N*
N* Description : Determine whether a character is a decimal-digit character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     a decimal-digit character.
N*
N*               DEF_NO,	 if character is NOT a decimal-digit character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) ISO/IEC 9899:TC2, Section 7.4.1.5.(2)  states that "isdigit()  ... tests for any
N*                   decimal-digit character".
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_DIG(c)               ((((c) >= ASCII_CHAR_DIG_ZERO) && ((c) <= ASCII_CHAR_DIG_NINE)) ? (DEF_YES) : (DEF_NO))
N
N
N/*
N*********************************************************************************************************
N*                                         ASCII_IS_DIG_OCT()
N*
N* Description : Determine whether a character is an octal-digit character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     an octal-digit character.
N*
N*               DEF_NO,	 if character is NOT an octal-digit character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : none.
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_DIG_OCT(c)          ((((c) >= ASCII_CHAR_DIG_ZERO) && ((c) <= ASCII_CHAR_DIG_SEVEN)) ? (DEF_YES) : (DEF_NO))
N
N
N/*
N*********************************************************************************************************
N*                                         ASCII_IS_DIG_HEX()
N*
N* Description : Determine whether a character is a hexadecimal-digit character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     a hexadecimal-digit character.
N*
N*               DEF_NO,	 if character is NOT a hexadecimal-digit character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) ISO/IEC 9899:TC2, Section 7.4.1.12.(2) states that "isxdigit() ... tests for any
N*                   hexadecimal-digit character".
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_DIG_HEX(c)          (((((c) >= ASCII_CHAR_DIG_ZERO     ) && ((c) <= ASCII_CHAR_DIG_NINE     )) || \
N                                        (((c) >= ASCII_CHAR_LATIN_UPPER_A) && ((c) <= ASCII_CHAR_LATIN_UPPER_F)) || \
N                                        (((c) >= ASCII_CHAR_LATIN_LOWER_A) && ((c) <= ASCII_CHAR_LATIN_LOWER_F))) ? (DEF_YES) : (DEF_NO))
X#define  ASCII_IS_DIG_HEX(c)          (((((c) >= ASCII_CHAR_DIG_ZERO     ) && ((c) <= ASCII_CHAR_DIG_NINE     )) ||                                         (((c) >= ASCII_CHAR_LATIN_UPPER_A) && ((c) <= ASCII_CHAR_LATIN_UPPER_F)) ||                                         (((c) >= ASCII_CHAR_LATIN_LOWER_A) && ((c) <= ASCII_CHAR_LATIN_LOWER_F))) ? (DEF_YES) : (DEF_NO))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          ASCII_IS_LOWER()
N*
N* Description : Determine whether a character is a lowercase alphabetic character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     a lowercase alphabetic character.
N*
N*               DEF_NO,	 if character is NOT a lowercase alphabetic character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) ISO/IEC 9899:TC2, Section 7.4.1.7.(2)  states that "islower() returns true only for
N*                   the lowercase letters".
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_LOWER(c)             ((((c) >= ASCII_CHAR_LATIN_LOWER_A) && ((c) <= ASCII_CHAR_LATIN_LOWER_Z)) ? (DEF_YES) : (DEF_NO))
N
N
N/*
N*********************************************************************************************************
N*                                          ASCII_IS_UPPER()
N*
N* Description : Determine whether a character is an uppercase alphabetic character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     an uppercase alphabetic character.
N*
N*               DEF_NO,	 if character is NOT an uppercase alphabetic character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) ISO/IEC 9899:TC2, Section 7.4.1.11.(2) states that "isupper() returns true only for
N*                   the uppercase letters".
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_UPPER(c)             ((((c) >= ASCII_CHAR_LATIN_UPPER_A) && ((c) <= ASCII_CHAR_LATIN_UPPER_Z)) ? (DEF_YES) : (DEF_NO))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          ASCII_IS_ALPHA()
N*
N* Description : Determine whether a character is an alphabetic character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     an alphabetic character.
N*
N*               DEF_NO,	 if character is NOT an alphabetic character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) ISO/IEC 9899:TC2, Section 7.4.1.2.(2) states that "isalpha() returns true only for the
N*                   characters for which isupper() or islower() is true".
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_ALPHA(c)             ((((ASCII_IS_UPPER(c)) == DEF_YES) || \
N                                         ((ASCII_IS_LOWER(c)) == DEF_YES)) ? (DEF_YES) : (DEF_NO))
X#define  ASCII_IS_ALPHA(c)             ((((ASCII_IS_UPPER(c)) == DEF_YES) ||                                          ((ASCII_IS_LOWER(c)) == DEF_YES)) ? (DEF_YES) : (DEF_NO))
N
N
N/*
N*********************************************************************************************************
N*                                        ASCII_IS_ALPHA_NUM()
N*
N* Description : Determine whether a character is an alphanumeric character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     an alphanumeric character.
N*
N*               DEF_NO,	 if character is NOT an alphanumeric character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) ISO/IEC 9899:TC2, Section 7.4.1.1.(2) states that "isalnum() ... tests for any character
N*                   for which isalpha() or isdigit() is true".
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_ALPHA_NUM(c)         ((((ASCII_IS_ALPHA(c)) == DEF_YES) || \
N                                         ((ASCII_IS_DIG  (c)) == DEF_YES)) ? (DEF_YES) : (DEF_NO))
X#define  ASCII_IS_ALPHA_NUM(c)         ((((ASCII_IS_ALPHA(c)) == DEF_YES) ||                                          ((ASCII_IS_DIG  (c)) == DEF_YES)) ? (DEF_YES) : (DEF_NO))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          ASCII_IS_BLANK()
N*
N* Description : Determine whether a character is a standard blank character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     a standard blank character.
N*
N*               DEF_NO,	 if character is NOT a standard blank character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) (a) ISO/IEC 9899:TC2, Section 7.4.1.3.(2) states that "isblank() returns true only for
N*                       the standard blank characters".
N*
N*                   (b) ISO/IEC 9899:TC2, Section 7.4.1.3.(2) defines "the standard blank characters" as
N*                       the "space (' '), and horizontal tab ('\t')".
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_BLANK(c)             ((((c) == ASCII_CHAR_SPACE) || ((c) == ASCII_CHAR_HT)) ? (DEF_YES) : (DEF_NO))
N
N
N/*
N*********************************************************************************************************
N*                                          ASCII_IS_SPACE()
N*
N* Description : Determine whether a character is a white-space character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     a white-space character.
N*
N*               DEF_NO,	 if character is NOT a white-space character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) (a) ISO/IEC 9899:TC2, Section 7.4.1.10.(2) states that "isspace() returns true only
N*                       for the standard white-space characters".
N*
N*                   (b) ISO/IEC 9899:TC2, Section 7.4.1.10.(2) defines "the standard white-space characters"
N*                       as the "space (' '), form feed ('\f'), new-line ('\n'), carriage return ('\r'),
N*                       horizontal tab ('\t'), and vertical tab ('\v')".
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_SPACE(c)             ((((c) == ASCII_CHAR_SPACE) || ((c) == ASCII_CHAR_CR) || \
N                                         ((c) == ASCII_CHAR_LF   ) || ((c) == ASCII_CHAR_FF) || \
N                                         ((c) == ASCII_CHAR_HT   ) || ((c) == ASCII_CHAR_VT)) ? (DEF_YES) : (DEF_NO))
X#define  ASCII_IS_SPACE(c)             ((((c) == ASCII_CHAR_SPACE) || ((c) == ASCII_CHAR_CR) ||                                          ((c) == ASCII_CHAR_LF   ) || ((c) == ASCII_CHAR_FF) ||                                          ((c) == ASCII_CHAR_HT   ) || ((c) == ASCII_CHAR_VT)) ? (DEF_YES) : (DEF_NO))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          ASCII_IS_PRINT()
N*
N* Description : Determine whether a character is a printing character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     a printing character.
N*
N*               DEF_NO,	 if character is NOT a printing character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) (a) ISO/IEC 9899:TC2, Section 7.4.1.8.(2) states that "isprint() ... tests for any
N*                       printing character including space (' ')".
N*
N*                   (b) ISO/IEC 9899:TC2, Section 7.4.(3), Note 169, states that in "the seven-bit US
N*                       ASCII character set, the printing characters are those whose values lie from
N*                       0x20 (space) through 0x7E (tilde)".
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_PRINT(c)             ((((c) >= ASCII_CHAR_SPACE) && ((c) <= ASCII_CHAR_TILDE)) ? (DEF_YES) : (DEF_NO))
N
N
N/*
N*********************************************************************************************************
N*                                          ASCII_IS_GRAPH()
N*
N* Description : Determine whether a character is any printing character except a space character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     a graphic character.
N*
N*               DEF_NO,	 if character is NOT a graphic character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) (a) ISO/IEC 9899:TC2, Section 7.4.1.6.(2) states that "isgraph() ... tests for any
N*                       printing character except space (' ')".
N*
N*                   (b) ISO/IEC 9899:TC2, Section 7.4.(3), Note 169, states that in "the seven-bit US
N*                       ASCII character set, the printing characters are those whose values lie from
N*                       0x20 (space) through 0x7E (tilde)".
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_GRAPH(c)             ((((c) >= ASCII_CHAR_EXCLAMATION_MARK) && ((c) <= ASCII_CHAR_TILDE)) ? (DEF_YES) : (DEF_NO))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          ASCII_IS_PUNCT()
N*
N* Description : Determine whether a character is a punctuation character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     a punctuation character.
N*
N*               DEF_NO,	 if character is NOT a punctuation character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) ISO/IEC 9899:TC2, Section 7.4.1.9.(2) states that "ispunct() returns true for every
N*                   printing character for which neither isspace() nor isalnum() is true".
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_PUNCT(c)             ((((ASCII_IS_PRINT(c)) == DEF_YES) && \
N                                         ((ASCII_IS_SPACE(c)) == DEF_NO ) && \
N                                         ((ASCII_IS_ALPHA_NUM(c)) == DEF_NO )) ? (DEF_YES) : (DEF_NO))
X#define  ASCII_IS_PUNCT(c)             ((((ASCII_IS_PRINT(c)) == DEF_YES) &&                                          ((ASCII_IS_SPACE(c)) == DEF_NO ) &&                                          ((ASCII_IS_ALPHA_NUM(c)) == DEF_NO )) ? (DEF_YES) : (DEF_NO))
N
N
N/*
N*********************************************************************************************************
N*                                           ASCII_IS_CTRL()
N*
N* Description : Determine whether a character is a control character.
N*
N* Argument(s) : c           Character to examine.
N*
N* Return(s)   : DEF_YES, if character is     a control character.
N*
N*               DEF_NO,	 if character is NOT a control character.
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) (a) ISO/IEC 9899:TC2, Section 7.4.1.4.(2) states that "iscntrl() ... tests for any
N*                       control character".
N*
N*                   (b) ISO/IEC 9899:TC2, Section 7.4.(3), Note 169, states that in "the seven-bit US
N*                       ASCII character set, ... the control characters are those whose values lie from
N*                       0 (NUL) through 0x1F (US), and the character 0x7F (DEL)".
N*********************************************************************************************************
N*/
N
N#define  ASCII_IS_CTRL(c)             (((((CPU_INT08S)(c) >= ASCII_CHAR_NULL  ) && ((c) <= ASCII_CHAR_IS1)) || \
N                                                                                   ((c) == ASCII_CHAR_DEL))  ? (DEF_YES) : (DEF_NO))
X#define  ASCII_IS_CTRL(c)             (((((CPU_INT08S)(c) >= ASCII_CHAR_NULL  ) && ((c) <= ASCII_CHAR_IS1)) ||                                                                                    ((c) == ASCII_CHAR_DEL))  ? (DEF_YES) : (DEF_NO))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                ASCII CHARACTER CASE MAPPING MACRO's
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                          ASCII_TO_LOWER()
N*
N* Description : Convert uppercase alphabetic character to its corresponding lowercase alphabetic character.
N*
N* Argument(s) : c           Character to convert.
N*
N* Return(s)   : Lowercase equivalent of 'c', if character 'c' is an uppercase character (see Note #1b1).
N*
N*               Character 'c',               otherwise                                  (see Note #1b2).
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) (a) ISO/IEC 9899:TC2, Section 7.4.2.1.(2) states that "tolower() ... converts an
N*                       uppercase letter to a corresponding lowercase letter".
N*
N*                   (b) ISO/IEC 9899:TC2, Section 7.4.2.1.(3) states that :
N*
N*                       (1) (A) "if the argument is a character for which isupper() is true and there are
N*                                one or more corresponding characters ... for which islower() is true," ...
N*                           (B) "tolower() ... returns one of the corresponding characters;" ...
N*
N*                       (2) "otherwise, the argument is returned unchanged."
N*********************************************************************************************************
N*/
N
N#define  ASCII_TO_LOWER(c)              (((ASCII_IS_UPPER(c)) == DEF_YES) ? ((c) + (ASCII_CHAR_LATIN_LOWER_A - ASCII_CHAR_LATIN_UPPER_A)) : (c))
N
N
N/*
N*********************************************************************************************************
N*                                          ASCII_TO_UPPER()
N*
N* Description : Convert lowercase alphabetic character to its corresponding uppercase alphabetic character.
N*
N* Argument(s) : c           Character to convert.
N*
N* Return(s)   : Uppercase equivalent of 'c', if character 'c' is a lowercase character (see Note #1b1).
N*
N*               Character 'c',               otherwise                                 (see Note #1b2).
N*
N* Caller(s)   : Application.
N*
N* Note(s)     : (1) (a) ISO/IEC 9899:TC2, Section 7.4.2.2.(2) states that "toupper() ... converts a
N*                       lowercase letter to a corresponding uppercase letter".
N*
N*                   (b) ISO/IEC 9899:TC2, Section 7.4.2.2.(3) states that :
N*
N*                       (1) (A) "if the argument is a character for which islower() is true and there are
N*                                one or more corresponding characters ... for which isupper() is true," ...
N*                           (B) "toupper() ... returns one of the corresponding characters;" ...
N*
N*                       (2) "otherwise, the argument is returned unchanged."
N*********************************************************************************************************
N*/
N
N#define  ASCII_TO_UPPER(c)              (((ASCII_IS_LOWER(c)) == DEF_YES) ? ((c) - (ASCII_CHAR_LATIN_LOWER_A - ASCII_CHAR_LATIN_UPPER_A)) : (c))
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                         FUNCTION PROTOTYPES
N*********************************************************************************************************
N*/
N
NCPU_BOOLEAN  ASCII_IsAlpha   (CPU_CHAR  c);
N
NCPU_BOOLEAN  ASCII_IsAlphaNum(CPU_CHAR  c);
N
NCPU_BOOLEAN  ASCII_IsLower   (CPU_CHAR  c);
N
NCPU_BOOLEAN  ASCII_IsUpper   (CPU_CHAR  c);
N
NCPU_BOOLEAN  ASCII_IsDig     (CPU_CHAR  c);
N
NCPU_BOOLEAN  ASCII_IsDigOct  (CPU_CHAR  c);
N
NCPU_BOOLEAN  ASCII_IsDigHex  (CPU_CHAR  c);
N
NCPU_BOOLEAN  ASCII_IsBlank   (CPU_CHAR  c);
N
NCPU_BOOLEAN  ASCII_IsSpace   (CPU_CHAR  c);
N
NCPU_BOOLEAN  ASCII_IsPrint   (CPU_CHAR  c);
N
NCPU_BOOLEAN  ASCII_IsGraph   (CPU_CHAR  c);
N
NCPU_BOOLEAN  ASCII_IsPunct   (CPU_CHAR  c);
N
NCPU_BOOLEAN  ASCII_IsCtrl    (CPU_CHAR  c);
N
N
NCPU_CHAR     ASCII_ToLower   (CPU_CHAR  c);
N
NCPU_CHAR     ASCII_ToUpper   (CPU_CHAR  c);
N
N
NCPU_BOOLEAN  ASCII_Cmp       (CPU_CHAR  c1,
N                              CPU_CHAR  c2);
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                        CONFIGURATION ERRORS
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                             MODULE END
N*
N* Note(s) : (1) See 'lib_ascii.h  MODULE'.
N*********************************************************************************************************
N*/
N
N#endif                                                          /* End of lib ascii module include.                     */
N
L 159 "..\..\uCOS-III\uC-LIB\lib_str.h" 2
N
N#include  <lib_cfg.h>
N
N#if 0                                                           /* See Note #4.                                         */
S#include  <stdio.h>
N#endif
N
N
N/*
N*********************************************************************************************************
N*                                               EXTERNS
N*********************************************************************************************************
N*/
N
N#ifdef   LIB_STR_MODULE
S#define  LIB_STR_EXT
N#else
N#define  LIB_STR_EXT  extern
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                        DEFAULT CONFIGURATION
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                 STRING FLOATING POINT CONFIGURATION
N*
N* Note(s) : (1) Configure LIB_STR_CFG_FP_EN to enable/disable floating point string function(s).
N*
N*           (2) Configure LIB_STR_CFG_FP_MAX_NBR_DIG_SIG to configure the maximum number of significant 
N*               digits to calculate &/or display for floating point string function(s).
N*
N*               See also 'STRING FLOATING POINT DEFINES  Note #1'.
N*********************************************************************************************************
N*/
N
N                                                                /* Configure floating point feature(s) [see Note #1] :  */
N#ifndef  LIB_STR_CFG_FP_EN
N#define  LIB_STR_CFG_FP_EN                      DEF_DISABLED
N                                                                /*   DEF_DISABLED     Floating point functions DISABLED */
N                                                                /*   DEF_ENABLED      Floating point functions ENABLED  */
N#endif
N
N                                                                /* Configure floating point feature(s)' number of ...   */
N                                                                /* ... significant digits (see Note #2).                */
N#ifndef  LIB_STR_CFG_FP_MAX_NBR_DIG_SIG
N#define  LIB_STR_CFG_FP_MAX_NBR_DIG_SIG         LIB_STR_FP_MAX_NBR_DIG_SIG_DFLT
N#endif
N
N
N/*
N*********************************************************************************************************
N*                                               DEFINES
N*********************************************************************************************************
N*/
N
N#define  STR_CR_LF                     "\r\n"
N#define  STR_LF_CR                     "\n\r"
N#define  STR_NEW_LINE                   STR_CR_LF
N#define  STR_PARENT_PATH               ".."
N
N#define  STR_CR_LF_LEN                 (sizeof(STR_CR_LF)       - 1)
N#define  STR_LF_CR_LEN                 (sizeof(STR_LF_CR)       - 1)
N#define  STR_NEW_LINE_LEN              (sizeof(STR_NEW_LINE)    - 1)
N#define  STR_PARENT_PATH_LEN           (sizeof(STR_PARENT_PATH) - 1)
N
N
N/*
N*********************************************************************************************************
N*                                             DATA TYPES
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                          GLOBAL VARIABLES
N*********************************************************************************************************
N*/
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                              MACRO'S
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                      STANDARD LIBRARY MACRO'S
N*
N* Note(s) : (1) NO compiler-supplied standard library functions SHOULD be used.
N*
N*               #### The reference to standard memory functions SHOULD be removed once all custom library
N*               functions are implemented WITHOUT reference to ANY standard library function(s).
N*
N*               See also 'INCLUDE FILES  Note #3'.
N*********************************************************************************************************
N*/
N
N                                                                /* See Note #1.                                         */
N#define  Str_FmtPrint                   snprintf
N#define  Str_FmtScan                    sscanf
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                         FUNCTION PROTOTYPES
N*********************************************************************************************************
N*/
N
N                                                                /* ------------------ STR LEN  FNCTS ------------------ */
NCPU_SIZE_T   Str_Len            (const  CPU_CHAR      *pstr);
N
NCPU_SIZE_T   Str_Len_N          (const  CPU_CHAR      *pstr,
N                                        CPU_SIZE_T     len_max);
N
N
N                                                                       /* ------------------ STR COPY FNCTS ------------------ */
NCPU_CHAR    *Str_Copy           (       CPU_CHAR      *pstr_dest,
N                                 const  CPU_CHAR      *pstr_src);
N
NCPU_CHAR    *Str_Copy_N         (       CPU_CHAR      *pstr_dest,
N                                 const  CPU_CHAR      *pstr_src,
N                                        CPU_SIZE_T     len_max);
N
N
NCPU_CHAR    *Str_Cat            (       CPU_CHAR      *pstr_dest,
N                                 const  CPU_CHAR      *pstr_cat);
N
NCPU_CHAR    *Str_Cat_N          (       CPU_CHAR      *pstr_dest,
N                                 const  CPU_CHAR      *pstr_cat,
N                                        CPU_SIZE_T     len_max);
N
N
N                                                                       /* ------------------ STR CMP  FNCTS ------------------ */
NCPU_INT16S   Str_Cmp            (const  CPU_CHAR      *p1_str,
N                                 const  CPU_CHAR      *p2_str);
N
NCPU_INT16S   Str_Cmp_N          (const  CPU_CHAR      *p1_str,
N                                 const  CPU_CHAR      *p2_str,
N                                        CPU_SIZE_T     len_max);
N
NCPU_INT16S   Str_CmpIgnoreCase  (const  CPU_CHAR      *p1_str,
N                                 const  CPU_CHAR      *p2_str);
N
NCPU_INT16S   Str_CmpIgnoreCase_N(const  CPU_CHAR      *p1_str,
N                                 const  CPU_CHAR      *p2_str,
N                                        CPU_SIZE_T     len_max);
N
N
N                                                                       /* ------------------ STR SRCH FNCTS ------------------ */
NCPU_CHAR    *Str_Char           (const  CPU_CHAR      *pstr,
N                                        CPU_CHAR       srch_char);
N
NCPU_CHAR    *Str_Char_N         (const  CPU_CHAR      *pstr,
N                                        CPU_SIZE_T     len_max,
N                                        CPU_CHAR       srch_char);
N
NCPU_CHAR    *Str_Char_Last      (const  CPU_CHAR      *pstr,
N                                        CPU_CHAR       srch_char);
N
NCPU_CHAR    *Str_Char_Last_N    (const  CPU_CHAR      *pstr,
N                                        CPU_SIZE_T     len_max,
N                                        CPU_CHAR       srch_char);
N
NCPU_CHAR    *Str_Char_Replace   (       CPU_CHAR      *pstr,
N                                        CPU_CHAR       char_srch,
N                                        CPU_CHAR       char_replace);
N
NCPU_CHAR    *Str_Char_Replace_N (       CPU_CHAR      *pstr,
N                                        CPU_CHAR       char_srch,
N                                        CPU_CHAR       char_replace,
N                                        CPU_SIZE_T     len_max);
N
NCPU_CHAR    *Str_Str            (const  CPU_CHAR      *pstr,
N                                 const  CPU_CHAR      *pstr_srch);
N
NCPU_CHAR    *Str_Str_N          (const  CPU_CHAR      *pstr,
N                                 const  CPU_CHAR      *pstr_srch,
N                                        CPU_SIZE_T     len_max);
N
N
N/*$PAGE*/
N                                                                       /* ------------------ STR FMT  FNCTS ------------------ */
NCPU_CHAR    *Str_FmtNbr_Int32U  (       CPU_INT32U     nbr,
N                                        CPU_INT08U     nbr_dig,
N                                        CPU_INT08U     nbr_base,
N                                        CPU_CHAR       lead_char,
N                                        CPU_BOOLEAN    lower_case,
N                                        CPU_BOOLEAN    nul,
N                                        CPU_CHAR      *pstr);
N
NCPU_CHAR    *Str_FmtNbr_Int32S  (       CPU_INT32S     nbr,
N                                        CPU_INT08U     nbr_dig,
N                                        CPU_INT08U     nbr_base,
N                                        CPU_CHAR       lead_char,
N                                        CPU_BOOLEAN    lower_case,
N                                        CPU_BOOLEAN    nul,
N                                        CPU_CHAR      *pstr);
N
N#if (LIB_STR_CFG_FP_EN == DEF_ENABLED)
X#if (0u == 1u)
SCPU_CHAR    *Str_FmtNbr_32      (       CPU_FP32       nbr,
S                                        CPU_INT08U     nbr_dig,
S                                        CPU_INT08U     nbr_dp,
S                                        CPU_CHAR       lead_char,
S                                        CPU_BOOLEAN    nul,
S                                        CPU_CHAR      *pstr);
N#endif
N
N
N                                                                       /* ----------------- STR PARSE FNCTS ------------------ */
NCPU_INT32U   Str_ParseNbr_Int32U(const  CPU_CHAR      *pstr,
N                                        CPU_CHAR     **pstr_next,
N                                        CPU_INT08U     nbr_base);
N
NCPU_INT32S   Str_ParseNbr_Int32S(const  CPU_CHAR      *pstr,
N                                        CPU_CHAR     **pstr_next,
N                                        CPU_INT08U     nbr_base);
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                        CONFIGURATION ERRORS
N*********************************************************************************************************
N*/
N
N#ifndef  LIB_STR_CFG_FP_EN
S#error  "LIB_STR_CFG_FP_EN                     not #define'd in 'lib_cfg.h'"
S#error  "                                [MUST be  DEF_DISABLED]           "
S#error  "                                [     ||  DEF_ENABLED ]           "
S
S#elif  ((LIB_STR_CFG_FP_EN != DEF_DISABLED) && \
S        (LIB_STR_CFG_FP_EN != DEF_ENABLED ))
X#elif  ((0u != 0u) &&         (0u != 1u ))
S#error  "LIB_STR_CFG_FP_EN               illegally #define'd in 'lib_cfg.h'"
S#error  "                                [MUST be  DEF_DISABLED]           "
S#error  "                                [     ||  DEF_ENABLED ]           "
S
S
S#elif   (LIB_STR_CFG_FP_EN == DEF_ENABLED)
X#elif   (0u == 1u)
S
S#ifndef  LIB_STR_CFG_FP_MAX_NBR_DIG_SIG
S#error  "LIB_STR_CFG_FP_MAX_NBR_DIG_SIG        not #define'd in 'lib_cfg.h'          "
S#error  "                                [MUST be  >= LIB_STR_FP_MAX_NBR_DIG_SIG_MIN]"
S#error  "                                [     &&  <= LIB_STR_FP_MAX_NBR_DIG_SIG_MAX]"
S
S#elif   (DEF_CHK_VAL(LIB_STR_CFG_FP_MAX_NBR_DIG_SIG,          \
S                     LIB_STR_FP_MAX_NBR_DIG_SIG_MIN,          \
S                     LIB_STR_FP_MAX_NBR_DIG_SIG_MAX) != DEF_OK)
X#elif   (DEF_CHK_VAL(LIB_STR_CFG_FP_MAX_NBR_DIG_SIG,                               LIB_STR_FP_MAX_NBR_DIG_SIG_MIN,                               LIB_STR_FP_MAX_NBR_DIG_SIG_MAX) != DEF_OK)
S#error  "LIB_STR_CFG_FP_MAX_NBR_DIG_SIG  illegally #define'd in 'lib_cfg.h'          "
S#error  "                                [MUST be  >= LIB_STR_FP_MAX_NBR_DIG_SIG_MIN]"
S#error  "                                [     &&  <= LIB_STR_FP_MAX_NBR_DIG_SIG_MAX]"
S#endif
S
N#endif
N
N
N/*
N*********************************************************************************************************
N*                                             MODULE END
N*
N* Note(s) : (1) See 'lib_str.h  MODULE'.
N*********************************************************************************************************
N*/
N
N#endif                                                          /* End of lib str module include.                       */
N
L 111 "..\..\uCOS-III\uC-CPU\cpu_core.h" 2
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          CPU CONFIGURATION
N*
N* Note(s) : (1) The following pre-processor directives correctly configure CPU parameters.  DO NOT MODIFY.
N*
N*           (2) CPU timestamp timer feature is required for :
N*
N*               (a) CPU timestamps
N*               (b) CPU interrupts disabled time measurement
N*
N*               See also 'cpu_cfg.h  CPU TIMESTAMP CONFIGURATION  Note #1'
N*                      & 'cpu_cfg.h  CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION  Note #1'.
N*********************************************************************************************************
N*/
N
N#ifdef   CPU_CFG_TS_EN
S#undef   CPU_CFG_TS_EN
N#endif
N
N
N#if    ((CPU_CFG_TS_32_EN == DEF_ENABLED) || \
N        (CPU_CFG_TS_64_EN == DEF_ENABLED))
X#if    ((1u == 1u) ||         (0u == 1u))
N#define  CPU_CFG_TS_EN                          DEF_ENABLED
N#else
S#define  CPU_CFG_TS_EN                          DEF_DISABLED
N#endif
N
N#if    ((CPU_CFG_TS_EN == DEF_ENABLED) || \
N(defined(CPU_CFG_INT_DIS_MEAS_EN)))
X#if    ((1u == 1u) || (0L))
N#define  CPU_CFG_TS_TMR_EN                      DEF_ENABLED
N#else
S#define  CPU_CFG_TS_TMR_EN                      DEF_DISABLED
N#endif
N
N
N/*
N*********************************************************************************************************
N*                                               DEFINES
N*********************************************************************************************************
N*/
N
N#define  CPU_TIME_MEAS_NBR_MIN                             1u
N#define  CPU_TIME_MEAS_NBR_MAX                           128u
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                             DATA TYPES
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                           CPU ERROR CODES
N*********************************************************************************************************
N*/
N
Ntypedef enum cpu_err {
N
N    CPU_ERR_NONE                            =         0u,
N    CPU_ERR_NULL_PTR                        =        10u,
N
N    CPU_ERR_NAME_SIZE                       =      1000u,
N
N    CPU_ERR_TS_FREQ_INVALID                 =      2000u
N
N} CPU_ERR;
N
N
N/*
N*********************************************************************************************************
N*                                      CPU TIMESTAMP DATA TYPES
N*
N* Note(s) : (1) CPU timestamp timer data type defined to the binary-multiple of 8-bit octets as configured 
N*               by 'CPU_CFG_TS_TMR_SIZE' (see 'cpu_cfg.h  CPU TIMESTAMP CONFIGURATION  Note #2').
N*********************************************************************************************************
N*/
N
Ntypedef  CPU_INT32U  CPU_TS32;
Ntypedef  CPU_INT64U  CPU_TS64;
N
Ntypedef  CPU_TS32    CPU_TS;                                    /* Req'd for backwards-compatibility.                   */
N
N
N#if     (CPU_CFG_TS_TMR_EN   == DEF_ENABLED)                    /* CPU ts tmr defined to cfg'd word size (see Note #1). */
X#if     (1u   == 1u)                     
N#if     (CPU_CFG_TS_TMR_SIZE == CPU_WORD_SIZE_08)
X#if     (4 == 1)
Stypedef  CPU_INT08U  CPU_TS_TMR;
S#elif   (CPU_CFG_TS_TMR_SIZE == CPU_WORD_SIZE_16)
X#elif   (4 == 2)
Stypedef  CPU_INT16U  CPU_TS_TMR;
S#elif   (CPU_CFG_TS_TMR_SIZE == CPU_WORD_SIZE_64)
X#elif   (4 == 8)
Stypedef  CPU_INT64U  CPU_TS_TMR;
N#else                                                           /* CPU ts tmr dflt size = 32-bits.                      */
Ntypedef  CPU_INT32U  CPU_TS_TMR;
N#endif
N#endif
N
N
N/*
N*********************************************************************************************************
N*                               CPU TIMESTAMP TIMER FREQUENCY DATA TYPE
N*********************************************************************************************************
N*/
N
Ntypedef  CPU_INT32U  CPU_TS_TMR_FREQ;
N
N
N/*
N*********************************************************************************************************
N*                                          GLOBAL VARIABLES
N*********************************************************************************************************
N*/
N
N#if    (CPU_CFG_NAME_EN   == DEF_ENABLED)
X#if    (1u   == 1u)
NCPU_CORE_EXT  CPU_CHAR         CPU_Name[CPU_CFG_NAME_SIZE];     /* CPU host name.                                       */
Xextern  CPU_CHAR         CPU_Name[16];      
N#endif
N
N
N#if ((CPU_CFG_TS_32_EN    == DEF_ENABLED)  && \
N     (CPU_CFG_TS_TMR_SIZE <  CPU_WORD_SIZE_32))
X#if ((1u    == 1u)  &&      (4 <  4))
SCPU_CORE_EXT  CPU_TS32         CPU_TS_32_Accum;                 /* 32-bit accum'd ts  (in ts tmr cnts).                 */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_TS_32_TmrPrev;               /* 32-bit ts prev tmr (in ts tmr cnts).                 */
N#endif
N
N#if ((CPU_CFG_TS_64_EN    == DEF_ENABLED)  && \
N     (CPU_CFG_TS_TMR_SIZE <  CPU_WORD_SIZE_64))
X#if ((0u    == 1u)  &&      (4 <  8))
SCPU_CORE_EXT  CPU_TS64         CPU_TS_64_Accum;                 /* 64-bit accum'd ts  (in ts tmr cnts).                 */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_TS_64_TmrPrev;               /* 64-bit ts prev tmr (in ts tmr cnts).                 */
N#endif
N
N#if  (CPU_CFG_TS_TMR_EN   == DEF_ENABLED)
X#if  (1u   == 1u)
NCPU_CORE_EXT  CPU_TS_TMR_FREQ  CPU_TS_TmrFreq_Hz;               /* CPU ts tmr freq (in Hz).                             */
Xextern  CPU_TS_TMR_FREQ  CPU_TS_TmrFreq_Hz;                
N#endif
N
N
N#ifdef  CPU_CFG_INT_DIS_MEAS_EN
SCPU_CORE_EXT  CPU_INT16U       CPU_IntDisMeasCtr;               /* Nbr tot    ints dis'd ctr.                           */
SCPU_CORE_EXT  CPU_INT16U       CPU_IntDisNestCtr;               /* Nbr nested ints dis'd ctr.                           */
S                                                                /* Ints dis'd time (in ts tmr cnts) : ...               */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_IntDisMeasStart_cnts;        /* ...  start time.                                     */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_IntDisMeasStop_cnts;         /* ...  stop  time.                                     */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_IntDisMeasOvrhd_cnts;        /* ...        time meas ovrhd.                          */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_IntDisMeasMaxCur_cnts;       /* ...     resetable max time dis'd.                    */
SCPU_CORE_EXT  CPU_TS_TMR       CPU_IntDisMeasMax_cnts;          /* ... non-resetable max time dis'd.                    */
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                               MACRO'S
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                         CPU_SW_EXCEPTION()
N*
N* Description : Trap unrecoverable software exception.
N*
N* Argument(s) : err_rtn_val     Error type &/or value of the calling function to return (see Note #2b).
N*
N* Return(s)   : none.
N*
N* Caller(s)   : various.
N*
N* Note(s)     : (1) CPU_SW_EXCEPTION() deadlocks the current code execution -- whether multi-tasked/
N*                   -processed/-threaded or single-threaded -- when the current code execution cannot 
N*                   gracefully recover or report a fault or exception condition.
N*
N*                   Example CPU_SW_EXCEPTION() call :
N*
N*                       void  Fnct (CPU_ERR  *p_err)
N*                       {
N*                           :
N*
N*                           if (p_err == (CPU_ERR *)0) {        If 'p_err' NULL, cannot return error ...
N*                               CPU_SW_EXCEPTION(;);            ... so trap invalid argument exception.
N*                           }
N*
N*                           :
N*                       }
N*
N*                   See also 'cpu_core.c  CPU_SW_Exception()  Note #1'.
N*
N*               (2) (a) CPU_SW_EXCEPTION()  MAY be developer-implemented to output &/or handle any error or 
N*                       exception conditions; but since CPU_SW_EXCEPTION() is intended to trap unrecoverable 
N*                       software  conditions, it is recommended that developer-implemented versions prevent 
N*                       execution of any code following calls to CPU_SW_EXCEPTION() by deadlocking the code 
N*                       (see Note #1).
N*
N*                           Example CPU_SW_EXCEPTION() :
N*
N*                               #define  CPU_SW_EXCEPTION(err_rtn_val)      do {                         \
N*                                                                               Log(__FILE__, __LINE__); \
N*                                                                               CPU_SW_Exception();      \
N*                                                                           } while (0)
X
N*
N*                   (b) (1) However, if execution of code following calls to CPU_SW_EXCEPTION() is required 
N*                           (e.g. for automated testing); it is recommended that the last statement in 
N*                           developer-implemented versions be to return from the current function to prevent 
N*                           possible software exception(s) in the current function from triggering CPU &/or 
N*                           hardware exception(s).
N*
N*                           Example CPU_SW_EXCEPTION() :
N*
N*                               #define  CPU_SW_EXCEPTION(err_rtn_val)      do {                         \
N*                                                                               Log(__FILE__, __LINE__); \
N*                                                                               return  err_rtn_val;     \
N*                                                                           } while (0)
X
N*
N*                           (A) Note that 'err_rtn_val' in the return statement MUST NOT be enclosed in 
N*                               parentheses.  This allows CPU_SW_EXCEPTION() to return from functions that 
N*                               return 'void', i.e. NO return type or value (see also Note #2b2A).
N*$PAGE*
N*                       (2) In order for CPU_SW_EXCEPTION() to return from functions with various return 
N*                           types/values, each caller function MUST pass an appropriate error return type 
N*                           & value to CPU_SW_EXCEPTION().
N*
N*                           (A) Note that CPU_SW_EXCEPTION()  MUST NOT be passed any return type or value 
N*                               for functions that return 'void', i.e. NO return type or value; but SHOULD 
N*                               instead be passed a single semicolon.  This prevents possible compiler 
N*                               warnings that CPU_SW_EXCEPTION() is passed too few arguments.  However, 
N*                               the compiler may warn that CPU_SW_EXCEPTION() does NOT prevent creating 
N*                               null statements on lines with NO other code statements.
N*
N*                           Example CPU_SW_EXCEPTION() calls :
N*
N*                               void  Fnct (CPU_ERR  *p_err)
N*                               {
N*                                   :
N*
N*                                   if (p_err == (CPU_ERR *)0) {
N*                                       CPU_SW_EXCEPTION(;);            Exception macro returns NO value
N*                                   }                                       (see Note #2b2A)
N*
N*                                   :
N*                               }
N*
N*                               CPU_BOOLEAN  Fnct (CPU_ERR  *p_err)
N*                               {
N*                                   :
N*
N*                                   if (p_err == (CPU_ERR *)0) {
N*                                       CPU_SW_EXCEPTION(DEF_FAIL);     Exception macro returns 'DEF_FAIL'
N*                                   }
N*
N*                                   :
N*                               }
N*
N*                               OBJ  *Fnct (CPU_ERR  *p_err)
N*                               {
N*                                   :
N*
N*                                   if (p_err == (CPU_ERR *)0) {
N*                                       CPU_SW_EXCEPTION((OBJ *)0);     Exception macro returns NULL 'OBJ *'
N*                                   }
N*
N*                                   :
N*                               }
N*
N*********************************************************************************************************
N*/
N
N#ifndef  CPU_SW_EXCEPTION                                                       /* See Note #2.                         */
N#define  CPU_SW_EXCEPTION(err_rtn_val)              do {                    \
N                                                        CPU_SW_Exception(); \
N                                                    } while (0)
X#define  CPU_SW_EXCEPTION(err_rtn_val)              do {                                                                            CPU_SW_Exception();                                                     } while (0)
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                           CPU_VAL_UNUSED()
N*
N* Description : 
N*
N* Argument(s) : none.
N*
N* Return(s)   : none.
N*
N* Caller(s)   : #### various.
N*
N* Note(s)     : none.
N*********************************************************************************************************
N*/
N
N
N#define  CPU_VAL_UNUSED(val)        ((void)&(val));
N
N
N#define  CPU_VAL_IGNORED(val)       CPU_VAL_UNUSED(val)
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                          CPU_TYPE_CREATE()
N*
N* Description : Creates a generic type value.
N*
N* Argument(s) : char_1      1st ASCII character to create generic type value.
N*
N*               char_2      2nd ASCII character to create generic type value.
N*
N*               char_3      3rd ASCII character to create generic type value.
N*
N*               char_4      4th ASCII character to create generic type value.
N*
N* Return(s)   : 32-bit generic type value.
N*
N* Caller(s)   : various.
N*
N* Note(s)     : (1) (a) Generic type values should be #define'd with large, non-trivial values to trap 
N*                       & discard invalid/corrupted objects based on type value.
N*
N*                       In other words, by assigning large, non-trivial values to valid objects' type 
N*                       fields; the likelihood that an object with an unassigned &/or corrupted type 
N*                       field will contain a value is highly improbable & therefore the object itself 
N*                       will be trapped as invalid.
N*
N*                   (b) (1) CPU_TYPE_CREATE()  creates a 32-bit type value from four values.
N*
N*                       (2) Ideally, generic type values SHOULD be created from 'CPU_CHAR' characters to 
N*                           represent ASCII string abbreviations of the specific object types.  Memory 
N*                           displays of object type values will display the specific object types with 
N*                           their chosen ASCII names.
N*
N*                           Examples :
N*
N*                               #define  FILE_TYPE  CPU_TYPE_CREATE('F', 'I', 'L', 'E')
N*                               #define  BUF_TYPE   CPU_TYPE_CREATE('B', 'U', 'F', ' ')
N*********************************************************************************************************
N*/
N
N#if     (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
X#if     (2u == 1u)
S#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (3u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_2)) << (2u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_3)) << (1u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_4)) << (0u * DEF_OCTET_NBR_BITS)))
X#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (3u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_2)) << (2u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_3)) << (1u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_4)) << (0u * DEF_OCTET_NBR_BITS)))
S
N#else
N
N#if    ((CPU_CFG_DATA_SIZE   == CPU_WORD_SIZE_64) || \
N        (CPU_CFG_DATA_SIZE   == CPU_WORD_SIZE_32))
X#if    ((4   == 8) ||         (4   == 4))
N#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (0u * DEF_OCTET_NBR_BITS)) | \
N                                                                 ((CPU_INT32U)((CPU_INT08U)(char_2)) << (1u * DEF_OCTET_NBR_BITS)) | \
N                                                                 ((CPU_INT32U)((CPU_INT08U)(char_3)) << (2u * DEF_OCTET_NBR_BITS)) | \
N                                                                 ((CPU_INT32U)((CPU_INT08U)(char_4)) << (3u * DEF_OCTET_NBR_BITS)))
X#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (0u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_2)) << (1u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_3)) << (2u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_4)) << (3u * DEF_OCTET_NBR_BITS)))
N
N
N#elif   (CPU_CFG_DATA_SIZE   == CPU_WORD_SIZE_16)
S#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (2u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_2)) << (3u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_3)) << (0u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_4)) << (1u * DEF_OCTET_NBR_BITS)))
X#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (2u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_2)) << (3u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_3)) << (0u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_4)) << (1u * DEF_OCTET_NBR_BITS)))
S
S#else                                                           /* Dflt CPU_WORD_SIZE_08.                               */
S#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (3u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_2)) << (2u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_3)) << (1u * DEF_OCTET_NBR_BITS)) | \
S                                                                 ((CPU_INT32U)((CPU_INT08U)(char_4)) << (0u * DEF_OCTET_NBR_BITS)))
X#define  CPU_TYPE_CREATE(char_1, char_2, char_3, char_4)        (((CPU_INT32U)((CPU_INT08U)(char_1)) << (3u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_2)) << (2u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_3)) << (1u * DEF_OCTET_NBR_BITS)) |                                                                  ((CPU_INT32U)((CPU_INT08U)(char_4)) << (0u * DEF_OCTET_NBR_BITS)))
N#endif
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                         FUNCTION PROTOTYPES
N*
N* Note(s) : (1) CPU interrupts disabled time measurement functions prototyped/defined only if 
N*               CPU_CFG_INT_DIS_MEAS_EN  #define'd in 'cpu_cfg.h'.
N*
N*           (2) (a) CPU_CntLeadZeros()  defined in :
N*
N*                   (1) 'cpu_a.asm',  if CPU_CFG_LEAD_ZEROS_ASM_PRESENT       #define'd in 'cpu.h'/
N*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
N*
N*                   (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT   NOT #define'd in 'cpu.h'/
N*                                         'cpu_cfg.h' to enable C-source-optimized function(s)
N*
N*               (b) CPU_CntTrailZeros() defined in :
N*
N*                   (1) 'cpu_a.asm',  if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT      #define'd in 'cpu.h'/
N*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
N*
N*                   (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT  NOT #define'd in 'cpu.h'/
N*                                         'cpu_cfg.h' to enable C-source-optimized function(s)
N*********************************************************************************************************
N*/
N
Nvoid             CPU_Init                 (void);
N
Nvoid             CPU_SW_Exception         (void);
N
N
N
N#if (CPU_CFG_NAME_EN == DEF_ENABLED)                                    /* -------------- CPU NAME FNCTS -------------- */
X#if (1u == 1u)                                     
Nvoid             CPU_NameClr              (void);
N
Nvoid             CPU_NameGet              (       CPU_CHAR  *p_name,
N                                                  CPU_ERR   *p_err);
N
Nvoid             CPU_NameSet              (const  CPU_CHAR  *p_name,
N                                                  CPU_ERR   *p_err);
N#endif
N
N
N
N                                                                        /* --------------- CPU TS FNCTS --------------- */
N#if (CPU_CFG_TS_32_EN == DEF_ENABLED)
X#if (1u == 1u)
NCPU_TS32         CPU_TS_Get32             (void);
N#endif
N
N#if (CPU_CFG_TS_64_EN == DEF_ENABLED)
X#if (0u == 1u)
SCPU_TS64         CPU_TS_Get64             (void);
N#endif
N
N#if (CPU_CFG_TS_EN    == DEF_ENABLED)
X#if (1u    == 1u)
Nvoid             CPU_TS_Update            (void);
N#endif
N
N
N#if (CPU_CFG_TS_TMR_EN == DEF_ENABLED)                                  /* ------------- CPU TS TMR FNCTS ------------- */
X#if (1u == 1u)                                   
NCPU_TS_TMR_FREQ  CPU_TS_TmrFreqGet        (CPU_ERR          *p_err);
N
Nvoid             CPU_TS_TmrFreqSet        (CPU_TS_TMR_FREQ   freq_hz);
N#endif
N
N
N
N#ifdef  CPU_CFG_INT_DIS_MEAS_EN                                         /* -------- CPU INT DIS TIME MEAS FNCTS ------- */
S                                                                        /* See Note #1.                                 */
SCPU_TS_TMR       CPU_IntDisMeasMaxCurReset(void);
S
SCPU_TS_TMR       CPU_IntDisMeasMaxCurGet  (void);
S
SCPU_TS_TMR       CPU_IntDisMeasMaxGet     (void);
S
S
Svoid             CPU_IntDisMeasStart      (void);
S
Svoid             CPU_IntDisMeasStop       (void);
N#endif
N
N
N
N                                                                        /* ----------- CPU CNT ZEROS FNCTS ------------ */
NCPU_DATA         CPU_CntLeadZeros         (CPU_DATA    val);
N
N#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_08)
X#if     (8 >= 1)
NCPU_DATA         CPU_CntLeadZeros08       (CPU_INT08U  val);
N#endif
N#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_16)
X#if     (8 >= 2)
NCPU_DATA         CPU_CntLeadZeros16       (CPU_INT16U  val);
N#endif
N#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_32)
X#if     (8 >= 4)
NCPU_DATA         CPU_CntLeadZeros32       (CPU_INT32U  val);
N#endif
N#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_64)
X#if     (8 >= 8)
NCPU_DATA         CPU_CntLeadZeros64       (CPU_INT64U  val);
N#endif
N
N
NCPU_DATA         CPU_CntTrailZeros        (CPU_DATA    val);
N
N#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_08)
X#if     (8 >= 1)
NCPU_DATA         CPU_CntTrailZeros08      (CPU_INT08U  val);
N#endif
N#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_16)
X#if     (8 >= 2)
NCPU_DATA         CPU_CntTrailZeros16      (CPU_INT16U  val);
N#endif
N#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_32)
X#if     (8 >= 4)
NCPU_DATA         CPU_CntTrailZeros32      (CPU_INT32U  val);
N#endif
N#if     (CPU_CFG_DATA_SIZE_MAX >= CPU_WORD_SIZE_64)
X#if     (8 >= 8)
NCPU_DATA         CPU_CntTrailZeros64      (CPU_INT64U  val);
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                         FUNCTION PROTOTYPES
N*                                      DEFINED IN PRODUCT'S BSP
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                          CPU_TS_TmrInit()
N*
N* Description : Initialize & start CPU timestamp timer.
N*
N* Argument(s) : none.
N*
N* Return(s)   : none.
N*
N* Caller(s)   : CPU_TS_Init().
N*
N*               This function is an INTERNAL CPU module function & MUST be implemented by application/
N*               BSP function(s) [see Note #1] but MUST NOT be called by application function(s).
N*
N* Note(s)     : (1) CPU_TS_TmrInit() is an application/BSP function that MUST be defined by the developer 
N*                   if either of the following CPU features is enabled :
N*
N*                   (a) CPU timestamps
N*                   (b) CPU interrupts disabled time measurements
N*
N*                   See 'cpu_cfg.h  CPU TIMESTAMP CONFIGURATION  Note #1'
N*                     & 'cpu_cfg.h  CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION  Note #1a'.
N*
N*               (2) (a) Timer count values MUST be returned via word-size-configurable 'CPU_TS_TMR' 
N*                       data type.
N*
N*                       (1) If timer has more bits, truncate timer values' higher-order bits greater 
N*                           than the configured 'CPU_TS_TMR' timestamp timer data type word size.
N*
N*                       (2) Since the timer MUST NOT have less bits than the configured 'CPU_TS_TMR' 
N*                           timestamp timer data type word size; 'CPU_CFG_TS_TMR_SIZE' MUST be 
N*                           configured so that ALL bits in 'CPU_TS_TMR' data type are significant.
N*
N*                           In other words, if timer size is not a binary-multiple of 8-bit octets 
N*                           (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple 
N*                           octet word size SHOULD be configured (e.g. to 16-bits).  However, the 
N*                           minimum supported word size for CPU timestamp timers is 8-bits.
N*
N*                       See also 'cpu_cfg.h   CPU TIMESTAMP CONFIGURATION  Note #2'
N*                              & 'cpu_core.h  CPU TIMESTAMP DATA TYPES     Note #1'.
N*
N*                   (b) Timer SHOULD be an 'up'  counter whose values increase with each time count.
N*
N*                   (c) When applicable, timer period SHOULD be less than the typical measured time 
N*                       but MUST be less than the maximum measured time; otherwise, timer resolution 
N*                       inadequate to measure desired times.
N*
N*                   See also 'CPU_TS_TmrRd()  Note #2'.
N*********************************************************************************************************
N*/
N
N#if (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
X#if (1u == 1u)
Nvoid  CPU_TS_TmrInit(void);
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                           CPU_TS_TmrRd()
N*
N* Description : Get current CPU timestamp timer count value.
N*
N* Argument(s) : none.
N*
N* Return(s)   : Timestamp timer count (see Notes #2a & #2b).
N*
N* Caller(s)   : CPU_TS_Init(),
N*               CPU_TS_Get32(),
N*               CPU_TS_Get64(),
N*               CPU_IntDisMeasStart(),
N*               CPU_IntDisMeasStop().
N*
N*               This function is an INTERNAL CPU module function & MUST be implemented by application/
N*               BSP function(s) [see Note #1] but SHOULD NOT be called by application function(s).
N*
N* Note(s)     : (1) CPU_TS_TmrRd() is an application/BSP function that MUST be defined by the developer 
N*                   if either of the following CPU features is enabled :
N*
N*                   (a) CPU timestamps
N*                   (b) CPU interrupts disabled time measurements
N*
N*                   See 'cpu_cfg.h  CPU TIMESTAMP CONFIGURATION  Note #1'
N*                     & 'cpu_cfg.h  CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION  Note #1a'.
N*
N*               (2) (a) Timer count values MUST be returned via word-size-configurable 'CPU_TS_TMR' 
N*                       data type.
N*
N*                       (1) If timer has more bits, truncate timer values' higher-order bits greater 
N*                           than the configured 'CPU_TS_TMR' timestamp timer data type word size.
N*
N*                       (2) Since the timer MUST NOT have less bits than the configured 'CPU_TS_TMR' 
N*                           timestamp timer data type word size; 'CPU_CFG_TS_TMR_SIZE' MUST be 
N*                           configured so that ALL bits in 'CPU_TS_TMR' data type are significant.
N*
N*                           In other words, if timer size is not a binary-multiple of 8-bit octets 
N*                           (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple 
N*                           octet word size SHOULD be configured (e.g. to 16-bits).  However, the 
N*                           minimum supported word size for CPU timestamp timers is 8-bits.
N*
N*                       See also 'cpu_cfg.h   CPU TIMESTAMP CONFIGURATION  Note #2'
N*                              & 'cpu_core.h  CPU TIMESTAMP DATA TYPES     Note #1'.
N*
N*                   (b) Timer SHOULD be an 'up'  counter whose values increase with each time count.
N*
N*                       (1) If timer is a 'down' counter whose values decrease with each time count,
N*                           then the returned timer value MUST be ones-complemented.
N*
N*                   (c) (1) When applicable, the amount of time measured by CPU timestamps is 
N*                           calculated by either of the following equations :
N*
N*                           (A) Time measured  =  Number timer counts  *  Timer period
N*
N*                                   where
N*
N*                                       Number timer counts     Number of timer counts measured 
N*                                       Timer period            Timer's period in some units of 
N*                                                                   (fractional) seconds
N*                                       Time measured           Amount of time measured, in same 
N*                                                                   units of (fractional) seconds 
N*                                                                   as the Timer period
N*
N*                                                  Number timer counts
N*                           (B) Time measured  =  ---------------------
N*                                                    Timer frequency
N*
N*                                   where
N*
N*                                       Number timer counts     Number of timer counts measured
N*                                       Timer frequency         Timer's frequency in some units 
N*                                                                   of counts per second
N*                                       Time measured           Amount of time measured, in seconds
N*
N*                       (2) Timer period SHOULD be less than the typical measured time but MUST be less 
N*                           than the maximum measured time; otherwise, timer resolution inadequate to 
N*                           measure desired times.
N*********************************************************************************************************
N*/
N
N#if (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
X#if (1u == 1u)
NCPU_TS_TMR  CPU_TS_TmrRd(void);
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                         CPU_TSxx_to_uSec()
N*
N* Description : Convert a 32-/64-bit CPU timestamp from timer counts to microseconds.
N*
N* Argument(s) : ts_cnts   CPU timestamp (in timestamp timer counts [see Note #2aA]).
N*
N* Return(s)   : Converted CPU timestamp (in microseconds           [see Note #2aD]).
N*
N* Caller(s)   : Application.
N*
N*               This function is an (optional) CPU module application programming interface (API) 
N*               function which MAY be implemented by application/BSP function(s) [see Note #1] & 
N*               MAY be called by application function(s).
N*
N* Note(s)     : (1) CPU_TS32_to_uSec()/CPU_TS64_to_uSec() are application/BSP functions that MAY be 
N*                   optionally defined by the developer when either of the following CPU features is 
N*                   enabled :
N*
N*                   (a) CPU timestamps
N*                   (b) CPU interrupts disabled time measurements
N*
N*                   See 'cpu_cfg.h  CPU TIMESTAMP CONFIGURATION  Note #1'
N*                     & 'cpu_cfg.h  CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION  Note #1a'.
N*
N*               (2) (a) The amount of time measured by CPU timestamps is calculated by either of 
N*                       the following equations :
N*
N*                                                                        10^6 microseconds
N*                       (1) Time measured  =   Number timer counts   *  -------------------  *  Timer period
N*                                                                            1 second
N*
N*                                              Number timer counts       10^6 microseconds
N*                       (2) Time measured  =  ---------------------  *  -------------------
N*                                                Timer frequency             1 second
N*
N*                               where
N*
N*                                   (A) Number timer counts     Number of timer counts measured
N*                                   (B) Timer frequency         Timer's frequency in some units 
N*                                                                   of counts per second
N*                                   (C) Timer period            Timer's period in some units of 
N*                                                                   (fractional)  seconds
N*                                   (D) Time measured           Amount of time measured, 
N*                                                                   in microseconds
N*
N*                   (b) Timer period SHOULD be less than the typical measured time but MUST be less 
N*                       than the maximum measured time; otherwise, timer resolution inadequate to 
N*                       measure desired times.
N*
N*                   (c) Specific implementations may convert any number of CPU_TS32 or CPU_TS64 bits 
N*                       -- up to 32 or 64, respectively -- into microseconds.
N*********************************************************************************************************
N*/
N
N#if (CPU_CFG_TS_32_EN == DEF_ENABLED)
X#if (1u == 1u)
NCPU_INT64U  CPU_TS32_to_uSec(CPU_TS32  ts_cnts);
N#endif
N
N#if (CPU_CFG_TS_64_EN == DEF_ENABLED)
X#if (0u == 1u)
SCPU_INT64U  CPU_TS64_to_uSec(CPU_TS64  ts_cnts);
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                        CONFIGURATION ERRORS
N*********************************************************************************************************
N*/
N
N#ifndef  CPU_CFG_NAME_EN
S#error  "CPU_CFG_NAME_EN                       not #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  DEF_ENABLED ]           "
S#error  "                                [     ||  DEF_DISABLED]           "
S
S#elif  ((CPU_CFG_NAME_EN != DEF_ENABLED ) && \
S        (CPU_CFG_NAME_EN != DEF_DISABLED))
X#elif  ((1u != 1u ) &&         (1u != 0u))
S#error  "CPU_CFG_NAME_EN                 illegally #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  DEF_ENABLED ]           "
S#error  "                                [     ||  DEF_DISABLED]           "
S
S
N#elif   (CPU_CFG_NAME_EN == DEF_ENABLED)
X#elif   (1u == 1u)
N
N#ifndef  CPU_CFG_NAME_SIZE
S#error  "CPU_CFG_NAME_SIZE                     not #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  >=   1]                 "
S#error  "                                [     &&  <= 255]                 "
S
S#elif   (DEF_CHK_VAL(CPU_CFG_NAME_SIZE,            \
S                     1,                            \
S                     DEF_INT_08U_MAX_VAL) != DEF_OK)
X#elif   (((((((!(((16) >= 1) && ((1) < 1))) && ((((1) >= 1) && ((16) < 1)) || ((16) < (1)))) ? 0u : 1u) == 0u) || ((((!(((255u) >= 1) && ((16) < 1))) && ((((16) >= 1) && ((255u) < 1)) || ((16) > (255u)))) ? 0u : 1u) == 0u)) ? 0u : 1u) != 1u)
S#error  "CPU_CFG_NAME_SIZE               illegally #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  >=   1]                 "
S#error  "                                [     &&  <= 255]                 "
N#endif
N
N#endif
N
N
N
N
N#ifndef  CPU_CFG_TS_32_EN
S#error  "CPU_CFG_TS_32_EN                      not #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  DEF_DISABLED]           "
S#error  "                                [     ||  DEF_ENABLED ]           "
S
S#elif  ((CPU_CFG_TS_32_EN != DEF_DISABLED) && \
S        (CPU_CFG_TS_32_EN != DEF_ENABLED ))
X#elif  ((1u != 0u) &&         (1u != 1u ))
S#error  "CPU_CFG_TS_32_EN                illegally #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  DEF_DISABLED]           "
S#error  "                                [     ||  DEF_ENABLED ]           "
S
N#endif
N
N
N#ifndef  CPU_CFG_TS_64_EN
S#error  "CPU_CFG_TS_64_EN                      not #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  DEF_DISABLED]           "
S#error  "                                [     ||  DEF_ENABLED ]           "
S
S#elif  ((CPU_CFG_TS_64_EN != DEF_DISABLED) && \
S        (CPU_CFG_TS_64_EN != DEF_ENABLED ))
X#elif  ((0u != 0u) &&         (0u != 1u ))
S#error  "CPU_CFG_TS_64_EN                illegally #define'd in 'cpu_cfg.h'"
S#error  "                                [MUST be  DEF_DISABLED]           "
S#error  "                                [     ||  DEF_ENABLED ]           "
S
N#endif
N
N                                                                /* Correctly configured in 'cpu_core.h'; DO NOT MODIFY. */
N#ifndef  CPU_CFG_TS_EN
S#error  "CPU_CFG_TS_EN                         not #define'd in 'cpu_core.h'"
S#error  "                                [MUST be  DEF_DISABLED]            "
S#error  "                                [     ||  DEF_ENABLED ]            "
S
S#elif  ((CPU_CFG_TS_EN != DEF_DISABLED) && \
S        (CPU_CFG_TS_EN != DEF_ENABLED ))
X#elif  ((1u != 0u) &&         (1u != 1u ))
S#error  "CPU_CFG_TS_EN                   illegally #define'd in 'cpu_core.h'"
S#error  "                                [MUST be  DEF_DISABLED]            "
S#error  "                                [     ||  DEF_ENABLED ]            "
S
N#endif
N
N
N/*$PAGE*/
N                                                                /* Correctly configured in 'cpu_core.h'; DO NOT MODIFY. */
N#ifndef  CPU_CFG_TS_TMR_EN
S#error  "CPU_CFG_TS_TMR_EN                     not #define'd in 'cpu_core.h'"
S#error  "                                [MUST be  DEF_DISABLED]            "
S#error  "                                [     ||  DEF_ENABLED ]            "
S
S#elif  ((CPU_CFG_TS_TMR_EN != DEF_DISABLED) && \
S        (CPU_CFG_TS_TMR_EN != DEF_ENABLED ))
X#elif  ((1u != 0u) &&         (1u != 1u ))
S#error  "CPU_CFG_TS_TMR_EN               illegally #define'd in 'cpu_core.h'"
S#error  "                                [MUST be  DEF_DISABLED]            "
S#error  "                                [     ||  DEF_ENABLED ]            "
S
S
N#elif   (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
X#elif   (1u == 1u)
N
N#ifndef  CPU_CFG_TS_TMR_SIZE
S#error  "CPU_CFG_TS_TMR_SIZE                   not #define'd in 'cpu_cfg.h'       "
S#error  "                                [MUST be  CPU_WORD_SIZE_08   8-bit timer]"
S#error  "                                [     ||  CPU_WORD_SIZE_16  16-bit timer]"
S#error  "                                [     ||  CPU_WORD_SIZE_32  32-bit timer]"
S#error  "                                [     ||  CPU_WORD_SIZE_64  64-bit timer]"
S
S#elif  ((CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_08) && \
S        (CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_16) && \
S        (CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_32) && \
S        (CPU_CFG_TS_TMR_SIZE != CPU_WORD_SIZE_64))
X#elif  ((4 != 1) &&         (4 != 2) &&         (4 != 4) &&         (4 != 8))
S#error  "CPU_CFG_TS_TMR_SIZE             illegally #define'd in 'cpu_cfg.h'       "
S#error  "                                [MUST be  CPU_WORD_SIZE_08   8-bit timer]"
S#error  "                                [     ||  CPU_WORD_SIZE_16  16-bit timer]"
S#error  "                                [     ||  CPU_WORD_SIZE_32  32-bit timer]"
S#error  "                                [     ||  CPU_WORD_SIZE_64  64-bit timer]"
N#endif
N
N#endif
N
N
N
N#ifndef  CPU_CFG_INT_DIS_MEAS_EN
N#if 0                                                           /* Optionally configured in 'cpu_cfg.h'; DO NOT MODIFY. */
S#error  "CPU_CFG_INT_DIS_MEAS_EN               not #define'd in 'cpu_cfg.h'"
N#endif
N
N#else
S
S#ifndef  CPU_CFG_INT_DIS_MEAS_OVRHD_NBR
S#error  "CPU_CFG_INT_DIS_MEAS_OVRHD_NBR        not #define'd in 'cpu_cfg.h' "
S#error  "                                [MUST be  >= CPU_TIME_MEAS_NBR_MIN]"
S#error  "                                [     ||  <= CPU_TIME_MEAS_NBR_MAX]"
S
S#elif   (DEF_CHK_VAL(CPU_CFG_INT_DIS_MEAS_OVRHD_NBR, \
S                     CPU_TIME_MEAS_NBR_MIN,          \
S                     CPU_TIME_MEAS_NBR_MAX) != DEF_OK)
X#elif   (DEF_CHK_VAL(CPU_CFG_INT_DIS_MEAS_OVRHD_NBR,                      CPU_TIME_MEAS_NBR_MIN,                               CPU_TIME_MEAS_NBR_MAX) != DEF_OK)
S#error  "CPU_CFG_INT_DIS_MEAS_OVRHD_NBR  illegally #define'd in 'cpu_cfg.h' "
S#error  "                                [MUST be  >= CPU_TIME_MEAS_NBR_MIN]"
S#error  "                                [     ||  <= CPU_TIME_MEAS_NBR_MAX]"
S
S#endif
S
N#endif
N
N
N
N
N#ifndef  CPU_CFG_LEAD_ZEROS_ASM_PRESENT
S#if 0                                                           /* Optionally configured in 'cpu_cfg.h'; DO NOT MODIFY. */
S#error  "CPU_CFG_LEAD_ZEROS_ASM_PRESENT        not #define'd in 'cpu.h'/'cpu_cfg.h'"
S#endif
N#endif
N
N
N#ifndef  CPU_CFG_TRAIL_ZEROS_ASM_PRESENT
S#if 0                                                           /* Optionally configured in 'cpu_cfg.h'; DO NOT MODIFY. */
S#error  "CPU_CFG_TRAIL_ZEROS_ASM_PRESENT       not #define'd in 'cpu.h'/'cpu_cfg.h'"
S#endif
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                    CPU PORT CONFIGURATION ERRORS
N*********************************************************************************************************
N*/
N
N#ifndef  CPU_CFG_ADDR_SIZE
S#error  "CPU_CFG_ADDR_SIZE      not #define'd in 'cpu.h'"
N#endif
N
N#ifndef  CPU_CFG_DATA_SIZE
S#error  "CPU_CFG_DATA_SIZE      not #define'd in 'cpu.h'"
N#endif
N
N#ifndef  CPU_CFG_DATA_SIZE_MAX
S#error  "CPU_CFG_DATA_SIZE_MAX  not #define'd in 'cpu.h'"
N#endif
N
N
N/*
N*********************************************************************************************************
N*                                    LIBRARY CONFIGURATION ERRORS
N*********************************************************************************************************
N*/
N
N                                                                /* See 'cpu_core.h  Note #1a'.                          */
N#if     (LIB_VERSION < 13500u)
X#if     (13700u < 13500u)
S#error  "LIB_VERSION  [SHOULD be >= V1.35.00]"
N#endif
N
N
N/*
N*********************************************************************************************************
N*                                             MODULE END
N*
N* Note(s) : (1) See 'cpu_core.h  MODULE'.
N*********************************************************************************************************
N*/
N
N#endif                                                          /* End of CPU core module include.                      */
N
L 62 "..\..\uCOS-III\uCOS-III\Source\os.h" 2
N#include <lib_def.h>
N#include <os_type.h>
L 1 "..\..\uCOS-III\uCOS-III\Source\os_type.h" 1
N/*
N************************************************************************************************************************
N*                                                      uC/OS-III
N*                                                 The Real-Time Kernel
N*
N*                                  (c) Copyright 2009-2012; Micrium, Inc.; Weston, FL
N*                           All rights reserved.  Protected by international copyright laws.
N*
N* File    : OS_TYPE.H
N* By      : JJL
N* Version : V3.03.01
N*
N* LICENSING TERMS:
N* ---------------
N*           uC/OS-III is provided in source form for FREE short-term evaluation, for educational use or 
N*           for peaceful research.  If you plan or intend to use uC/OS-III in a commercial application/
N*           product then, you need to contact Micrium to properly license uC/OS-III for its use in your 
N*           application/product.   We provide ALL the source code for your convenience and to help you 
N*           experience uC/OS-III.  The fact that the source is provided does NOT mean that you can use 
N*           it commercially without paying a licensing fee.
N*
N*           Knowledge of the source code may NOT be used to develop a similar product.
N*
N*           Please help us continue to provide the embedded community with the finest software available.
N*           Your honesty is greatly appreciated.
N*
N*           You can contact us at www.micrium.com, or by phone at +1 (954) 217-2036.
N************************************************************************************************************************
N*/
N
N#ifndef   OS_TYPE_H
N#define   OS_TYPE_H
N
N#ifdef    VSC_INCLUDE_H_FILE_NAMES
Sconst     CPU_CHAR  *os_type__h = "$Id: $";
N#endif
N
N/*
N************************************************************************************************************************
N*                                                 INCLUDE HEADER FILES
N************************************************************************************************************************
N*/
N
N                                                       /*       Description                                    # Bits */
N                                                       /*                                               <recommended> */
N                                                       /* ----------------------------------------------------------- */
N
Ntypedef   CPU_INT16U      OS_CPU_USAGE;                /* CPU Usage 0..10000                                  <16>/32 */
N
Ntypedef   CPU_INT32U      OS_CTR;                      /* Counter,                                                 32 */
N
Ntypedef   CPU_INT32U      OS_CTX_SW_CTR;               /* Counter of context switches,                             32 */
N
Ntypedef   CPU_INT32U      OS_CYCLES;                   /* CPU clock cycles,                                   <32>/64 */
N
Ntypedef   CPU_INT32U      OS_FLAGS;                    /* Event flags,                                      8/16/<32> */
N
Ntypedef   CPU_INT32U      OS_IDLE_CTR;                 /* Holds the number of times the idle task runs,       <32>/64 */
N
Ntypedef   CPU_INT16U      OS_MEM_QTY;                  /* Number of memory blocks,                            <16>/32 */
Ntypedef   CPU_INT16U      OS_MEM_SIZE;                 /* Size in bytes of a memory block,                    <16>/32 */
N
Ntypedef   CPU_INT16U      OS_MSG_QTY;                  /* Number of OS_MSGs in the msg pool,                  <16>/32 */
Ntypedef   CPU_INT16U      OS_MSG_SIZE;                 /* Size of messages in number of bytes,                <16>/32 */
N
Ntypedef   CPU_INT08U      OS_NESTING_CTR;              /* Interrupt and scheduler nesting,                  <8>/16/32 */
N
Ntypedef   CPU_INT16U      OS_OBJ_QTY;                  /* Number of kernel objects counter,                   <16>/32 */
Ntypedef   CPU_INT32U      OS_OBJ_TYPE;                 /* Special flag to determine object type,                   32 */
N
Ntypedef   CPU_INT16U      OS_OPT;                      /* Holds function options                              <16>/32 */
N
Ntypedef   CPU_INT08U      OS_PRIO;                     /* Priority of a task,                               <8>/16/32 */
N
Ntypedef   CPU_INT16U      OS_QTY;                      /* Quantity                                            <16>/32 */
N
Ntypedef   CPU_INT32U      OS_RATE_HZ;                  /* Rate in Hertz                                            32 */
N
Ntypedef   CPU_INT32U      OS_REG;                      /* Task register                                     8/16/<32> */
Ntypedef   CPU_INT08U      OS_REG_ID;                   /* Index to task register                            <8>/16/32 */
N
Ntypedef   CPU_INT32U      OS_SEM_CTR;                  /* Semaphore value                                     16/<32> */
N
Ntypedef   CPU_INT08U      OS_STATE;                    /* State variable                                    <8>/16/32 */
N
Ntypedef   CPU_INT08U      OS_STATUS;                   /* Status                                            <8>/16/32 */
N
Ntypedef   CPU_INT32U      OS_TICK;                     /* Clock tick counter                                  <32>/64 */
Ntypedef   CPU_INT16U      OS_TICK_SPOKE_IX;            /* Tick wheel spoke position                         8/<16>/32 */
N
Ntypedef   CPU_INT16U      OS_TMR_SPOKE_IX;             /* Timer wheel spoke position                        8/<16>/32 */
N
N#endif
L 64 "..\..\uCOS-III\uCOS-III\Source\os.h" 2
N#include <os_cpu.h>
L 1 "..\..\uCOS-III\uCOS-III\Ports\ARM-Cortex-M4\Generic\RealView\os_cpu.h" 1
N/*
N*********************************************************************************************************
N*                                                uC/OS-III
N*                                          The Real-Time Kernel
N*
N*
N*                              (c) Copyright 2010; Micrium, Inc.; Weston, FL
N*                    All rights reserved.  Protected by international copyright laws.
N*
N*                                           ARM Cortex-M4 Port
N*
N* File      : OS_CPU.H
N* Version   : V3.01.2
N* By        : JJL
N*
N* LICENSING TERMS:
N* ---------------
N*           uC/OS-III is provided in source form for FREE short-term evaluation, for educational use or 
N*           for peaceful research.  If you plan or intend to use uC/OS-III in a commercial application/
N*           product then, you need to contact Micrium to properly license uC/OS-III for its use in your 
N*           application/product.   We provide ALL the source code for your convenience and to help you 
N*           experience uC/OS-III.  The fact that the source is provided does NOT mean that you can use 
N*           it commercially without paying a licensing fee.
N*
N*           Knowledge of the source code may NOT be used to develop a similar product.
N*
N*           Please help us continue to provide the embedded community with the finest software available.
N*           Your honesty is greatly appreciated.
N*
N*           You can contact us at www.micrium.com, or by phone at +1 (954) 217-2036.
N*
N* For       : ARMv7 Cortex-M4
N* Mode      : Thumb-2 ISA
N* Toolchain : RealView
N*********************************************************************************************************
N*/
N
N#ifndef  OS_CPU_H
N#define  OS_CPU_H
N
N#ifdef   OS_CPU_GLOBALS
S#define  OS_CPU_EXT
N#else
N#define  OS_CPU_EXT  extern
N#endif
N
N/*
N*********************************************************************************************************
N*                                               DEFINES
N*********************************************************************************************************
N*/
N
N// #ifdef __ARMVFP__
N
N// #else
N// #define  OS_CPU_ARM_FP_EN                              DEF_DISABLED
N// #endif
N// #define  OS_CPU_ARM_FP_REG_NBR                           32u
N#define  OS_CPU_ARM_FP_EN                              DEF_ENABLED
N/*
N*********************************************************************************************************
N*                                               MACROS
N*********************************************************************************************************
N*/
N
N#define  OS_TASK_SW()               OSCtxSw()
N
N/*
N*********************************************************************************************************
N*                                       TIMESTAMP CONFIGURATION
N*
N* Note(s) : (1) OS_TS_GET() is generally defined as CPU_TS_Get32() to allow CPU timestamp timer to be of
N*               any data type size.
N*
N*           (2) For architectures that provide 32-bit or higher precision free running counters 
N*               (i.e. cycle count registers):
N*
N*               (a) OS_TS_GET() may be defined as CPU_TS_TmrRd() to improve performance when retrieving
N*                   the timestamp.
N*
N*               (b) CPU_TS_TmrRd() MUST be configured to be greater or equal to 32-bits to avoid
N*                   truncation of TS.
N*********************************************************************************************************
N*/
N
N#if      OS_CFG_TS_EN == 1u
X#if      0u == 1u
S#define  OS_TS_GET()               (CPU_TS)CPU_TS_TmrRd()   /* See Note #2a.                                          */
N#else
N#define  OS_TS_GET()               (CPU_TS)0u
N#endif
N
N#if (CPU_CFG_TS_32_EN    == DEF_ENABLED) && \
N    (CPU_CFG_TS_TMR_SIZE  < CPU_WORD_SIZE_32)
X#if (1u    == 1u) &&     (4  < 4)
S                                                            /* CPU_CFG_TS_TMR_SIZE MUST be >= 32-bit (see Note #2b).  */
S#error  "cpu_cfg.h, CPU_CFG_TS_TMR_SIZE MUST be >= CPU_WORD_SIZE_32"
N#endif
N
N
N/*
N*********************************************************************************************************
N*                              OS TICK INTERRUPT PRIORITY CONFIGURATION
N*
N* Note(s) : (1) For systems that don't need any high, real-time priority interrupts; the tick interrupt
N*               should be configured as the highest priority interrupt but won't adversely affect system
N*               operations.
N*
N*           (2) For systems that need one or more high, real-time interrupts; these should be configured
N*               higher than the tick interrupt which MAY delay execution of the tick interrupt.
N*
N*               (a) If the higher priority interrupts do NOT continually consume CPU cycles but only
N*                   occasionally delay tick interrupts, then the real-time interrupts can successfully
N*                   handle their intermittent/periodic events with the system not losing tick interrupts
N*                   but only increasing the jitter.
N*
N*               (b) If the higher priority interrupts consume enough CPU cycles to continually delay the
N*                   tick interrupt, then the CPU/system is most likely over-burdened & can't be expected
N*                   to handle all its interrupts/tasks. The system time reference gets compromised as a
N*                   result of losing tick interrupts.
N*********************************************************************************************************
N*/
N
N#define  OS_CPU_CFG_SYSTICK_PRIO           0u
N
N/*
N*********************************************************************************************************
N*                                          GLOBAL VARIABLES
N*********************************************************************************************************
N*/
N
NOS_CPU_EXT  CPU_STK  *OS_CPU_ExceptStkBase;
Xextern  CPU_STK  *OS_CPU_ExceptStkBase;
N
N/*
N*********************************************************************************************************
N*                                         FUNCTION PROTOTYPES
N*********************************************************************************************************
N*/
N
Nvoid  OSCtxSw              (void);
Nvoid  OSIntCtxSw           (void);
Nvoid  OSStartHighRdy       (void);
N
Nvoid  OS_CPU_PendSVHandler (void);
N
N
Nvoid  OS_CPU_SysTickHandler(void);
Nvoid  OS_CPU_SysTickInit   (CPU_INT32U  cnts);
N
N//#if (OS_CPU_ARM_FP_EN == DEF_ENABLED)
Nvoid  OS_CPU_FP_Reg_Push   (CPU_STK    *stkPtr);
Nvoid  OS_CPU_FP_Reg_Pop    (CPU_STK    *stkPtr);
N//#endif
N#endif
L 65 "..\..\uCOS-III\uCOS-III\Source\os.h" 2
N
N
N/*
N************************************************************************************************************************
N*                                               CRITICAL SECTION HANDLING
N************************************************************************************************************************
N*/
N
N
N#if      OS_CFG_SCHED_LOCK_TIME_MEAS_EN > 0u && defined(CPU_CFG_INT_DIS_MEAS_EN)
X#if      0u > 0u && 0L
S#define  OS_SCHED_LOCK_TIME_MEAS_START()    OS_SchedLockTimeMeasStart()
N#else
N#define  OS_SCHED_LOCK_TIME_MEAS_START()
N#endif
N
N
N#if      OS_CFG_SCHED_LOCK_TIME_MEAS_EN > 0u && defined(CPU_CFG_INT_DIS_MEAS_EN)
X#if      0u > 0u && 0L
S#define  OS_SCHED_LOCK_TIME_MEAS_STOP()     OS_SchedLockTimeMeasStop()
N#else
N#define  OS_SCHED_LOCK_TIME_MEAS_STOP()
N#endif
N
N#if OS_CFG_ISR_POST_DEFERRED_EN > 0u                             /* Deferred ISR Posts ------------------------------ */
X#if 0u > 0u                              
S                                                                 /* Lock the scheduler                                */
S#define  OS_CRITICAL_ENTER()                                       \
S         do {                                                      \
S             CPU_CRITICAL_ENTER();                                 \
S             OSSchedLockNestingCtr++;                              \
S             if (OSSchedLockNestingCtr == 1u) {                    \
S                 OS_SCHED_LOCK_TIME_MEAS_START();                  \
S             }                                                     \
S             CPU_CRITICAL_EXIT();                                  \
S         } while (0)
X#define  OS_CRITICAL_ENTER()                                                do {                                                                   CPU_CRITICAL_ENTER();                                              OSSchedLockNestingCtr++;                                           if (OSSchedLockNestingCtr == 1u) {                                     OS_SCHED_LOCK_TIME_MEAS_START();                               }                                                                  CPU_CRITICAL_EXIT();                                           } while (0)
S                                                                 /* Lock the scheduler but re-enable interrupts       */
S#define  OS_CRITICAL_ENTER_CPU_EXIT()                              \
S         do {                                                      \
S             OSSchedLockNestingCtr++;                              \
S                                                                   \
S             if (OSSchedLockNestingCtr == 1u) {                    \
S                 OS_SCHED_LOCK_TIME_MEAS_START();                  \
S             }                                                     \
S             CPU_CRITICAL_EXIT();                                  \
S         } while (0)
X#define  OS_CRITICAL_ENTER_CPU_EXIT()                                       do {                                                                   OSSchedLockNestingCtr++;                                                                                                              if (OSSchedLockNestingCtr == 1u) {                                     OS_SCHED_LOCK_TIME_MEAS_START();                               }                                                                  CPU_CRITICAL_EXIT();                                           } while (0)
S
S                                                                 /* Scheduling occurs only if an interrupt occurs     */
S#define  OS_CRITICAL_EXIT()                                        \
S         do {                                                      \
S             CPU_CRITICAL_ENTER();                                 \
S             OSSchedLockNestingCtr--;                              \
S             if (OSSchedLockNestingCtr == (OS_NESTING_CTR)0) {     \
S                 OS_SCHED_LOCK_TIME_MEAS_STOP();                   \
S                 if (OSIntQNbrEntries > (OS_OBJ_QTY)0) {           \
S                     CPU_CRITICAL_EXIT();                          \
S                     OS_Sched0();                                  \
S                 } else {                                          \
S                     CPU_CRITICAL_EXIT();                          \
S                 }                                                 \
S             } else {                                              \
S                 CPU_CRITICAL_EXIT();                              \
S             }                                                     \
S         } while (0)
X#define  OS_CRITICAL_EXIT()                                                 do {                                                                   CPU_CRITICAL_ENTER();                                              OSSchedLockNestingCtr--;                                           if (OSSchedLockNestingCtr == (OS_NESTING_CTR)0) {                      OS_SCHED_LOCK_TIME_MEAS_STOP();                                    if (OSIntQNbrEntries > (OS_OBJ_QTY)0) {                                CPU_CRITICAL_EXIT();                                               OS_Sched0();                                                   } else {                                                               CPU_CRITICAL_EXIT();                                           }                                                              } else {                                                               CPU_CRITICAL_EXIT();                                           }                                                              } while (0)
S
S#define  OS_CRITICAL_EXIT_NO_SCHED()                               \
S         do {                                                      \
S             CPU_CRITICAL_ENTER();                                 \
S             OSSchedLockNestingCtr--;                              \
S             if (OSSchedLockNestingCtr == (OS_NESTING_CTR)0) {     \
S                 OS_SCHED_LOCK_TIME_MEAS_STOP();                   \
S             }                                                     \
S             CPU_CRITICAL_EXIT();                                  \
S         } while (0)
X#define  OS_CRITICAL_EXIT_NO_SCHED()                                        do {                                                                   CPU_CRITICAL_ENTER();                                              OSSchedLockNestingCtr--;                                           if (OSSchedLockNestingCtr == (OS_NESTING_CTR)0) {                      OS_SCHED_LOCK_TIME_MEAS_STOP();                                }                                                                  CPU_CRITICAL_EXIT();                                           } while (0)
S
S
N#else                                                            /* Direct ISR Posts -------------------------------- */
N
N
N#define  OS_CRITICAL_ENTER()                    CPU_CRITICAL_ENTER()
N
N#define  OS_CRITICAL_ENTER_CPU_EXIT()
N
N#define  OS_CRITICAL_EXIT()                     CPU_CRITICAL_EXIT()
N
N#define  OS_CRITICAL_EXIT_NO_SCHED()            CPU_CRITICAL_EXIT()
N
N#endif
N
N/*
N************************************************************************************************************************
N*                                                     MISCELLANEOUS
N************************************************************************************************************************
N*/
N
N#ifdef   OS_GLOBALS
S#define  OS_EXT
N#else
N#define  OS_EXT  extern
N#endif
N
N
N#define  OS_PRIO_TBL_SIZE          ((OS_CFG_PRIO_MAX - 1u) / (DEF_INT_CPU_NBR_BITS) + 1u)
N
N#define  OS_MSG_EN                 (((OS_CFG_TASK_Q_EN > 0u) || (OS_CFG_Q_EN > 0u)) ? 1u : 0u)
N
N/*$PAGE*/
N/*
N************************************************************************************************************************
N************************************************************************************************************************
N*                                                   # D E F I N E S
N************************************************************************************************************************
N************************************************************************************************************************
N*/
N
N/*
N========================================================================================================================
N*                                                      TASK STATUS
N========================================================================================================================
N*/
N
N#define  OS_STATE_OS_STOPPED                    (OS_STATE)(0u)
N#define  OS_STATE_OS_RUNNING                    (OS_STATE)(1u)
N
N#define  OS_STATE_NOT_RDY                    (CPU_BOOLEAN)(0u)
N#define  OS_STATE_RDY                        (CPU_BOOLEAN)(1u)
N
N
N                                                                /* ------------------- TASK STATES ------------------ */
N#define  OS_TASK_STATE_BIT_DLY               (OS_STATE)(0x01u)  /*   /-------- SUSPENDED bit                          */
N                                                                /*   |                                                */
N#define  OS_TASK_STATE_BIT_PEND              (OS_STATE)(0x02u)  /*   | /-----  PEND      bit                          */
N                                                                /*   | |                                              */
N#define  OS_TASK_STATE_BIT_SUSPENDED         (OS_STATE)(0x04u)  /*   | | /---  Delayed/Timeout bit                    */
N                                                                /*   | | |                                            */
N                                                                /*   V V V                                            */
N
N#define  OS_TASK_STATE_RDY                    (OS_STATE)(  0u)  /*   0 0 0     Ready                                  */
N#define  OS_TASK_STATE_DLY                    (OS_STATE)(  1u)  /*   0 0 1     Delayed or Timeout                     */
N#define  OS_TASK_STATE_PEND                   (OS_STATE)(  2u)  /*   0 1 0     Pend                                   */
N#define  OS_TASK_STATE_PEND_TIMEOUT           (OS_STATE)(  3u)  /*   0 1 1     Pend + Timeout                         */
N#define  OS_TASK_STATE_SUSPENDED              (OS_STATE)(  4u)  /*   1 0 0     Suspended                              */
N#define  OS_TASK_STATE_DLY_SUSPENDED          (OS_STATE)(  5u)  /*   1 0 1     Suspended + Delayed or Timeout         */
N#define  OS_TASK_STATE_PEND_SUSPENDED         (OS_STATE)(  6u)  /*   1 1 0     Suspended + Pend                       */
N#define  OS_TASK_STATE_PEND_TIMEOUT_SUSPENDED (OS_STATE)(  7u)  /*   1 1 1     Suspended + Pend + Timeout             */
N#define  OS_TASK_STATE_DEL                    (OS_STATE)(255u)
N
N                                                                /* ----------------- PENDING ON ... ----------------- */
N#define  OS_TASK_PEND_ON_NOTHING              (OS_STATE)(  0u)  /* Pending on nothing                                 */
N#define  OS_TASK_PEND_ON_FLAG                 (OS_STATE)(  1u)  /* Pending on event flag group                        */
N#define  OS_TASK_PEND_ON_TASK_Q               (OS_STATE)(  2u)  /* Pending on message to be sent to task              */
N#define  OS_TASK_PEND_ON_MULTI                (OS_STATE)(  3u)  /* Pending on multiple semaphores and/or queues       */
N#define  OS_TASK_PEND_ON_MUTEX                (OS_STATE)(  4u)  /* Pending on mutual exclusion semaphore              */
N#define  OS_TASK_PEND_ON_Q                    (OS_STATE)(  5u)  /* Pending on queue                                   */
N#define  OS_TASK_PEND_ON_SEM                  (OS_STATE)(  6u)  /* Pending on semaphore                               */
N#define  OS_TASK_PEND_ON_TASK_SEM             (OS_STATE)(  7u)  /* Pending on signal  to be sent to task              */
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                    TASK PEND STATUS
N*                                      (Status codes for OS_TCBs field .PendStatus)
N------------------------------------------------------------------------------------------------------------------------
N*/
N
N#define  OS_STATUS_PEND_OK                   (OS_STATUS)(  0u)  /* Pending status OK, !pending, or pending complete   */
N#define  OS_STATUS_PEND_ABORT                (OS_STATUS)(  1u)  /* Pending aborted                                    */
N#define  OS_STATUS_PEND_DEL                  (OS_STATUS)(  2u)  /* Pending object deleted                             */
N#define  OS_STATUS_PEND_TIMEOUT              (OS_STATUS)(  3u)  /* Pending timed out                                  */
N
N/*
N========================================================================================================================
N*                                                   OS OBJECT TYPES
N*
N* Note(s) : (1) OS_OBJ_TYPE_&&& #define values specifically chosen as ASCII representations of the kernel
N*               object types.  Memory displays of kernel objects will display the kernel object TYPEs with
N*               their chosen ASCII names.
N========================================================================================================================
N*/
N
N#define  OS_OBJ_TYPE_NONE                    (OS_OBJ_TYPE)CPU_TYPE_CREATE('N', 'O', 'N', 'E')
N#define  OS_OBJ_TYPE_FLAG                    (OS_OBJ_TYPE)CPU_TYPE_CREATE('F', 'L', 'A', 'G')
N#define  OS_OBJ_TYPE_MEM                     (OS_OBJ_TYPE)CPU_TYPE_CREATE('M', 'E', 'M', ' ')
N#define  OS_OBJ_TYPE_MUTEX                   (OS_OBJ_TYPE)CPU_TYPE_CREATE('M', 'U', 'T', 'X')
N#define  OS_OBJ_TYPE_Q                       (OS_OBJ_TYPE)CPU_TYPE_CREATE('Q', 'U', 'E', 'U')
N#define  OS_OBJ_TYPE_SEM                     (OS_OBJ_TYPE)CPU_TYPE_CREATE('S', 'E', 'M', 'A')
N#define  OS_OBJ_TYPE_TASK_MSG                (OS_OBJ_TYPE)CPU_TYPE_CREATE('T', 'M', 'S', 'G')
N#define  OS_OBJ_TYPE_TASK_RESUME             (OS_OBJ_TYPE)CPU_TYPE_CREATE('T', 'R', 'E', 'S')
N#define  OS_OBJ_TYPE_TASK_SIGNAL             (OS_OBJ_TYPE)CPU_TYPE_CREATE('T', 'S', 'I', 'G')
N#define  OS_OBJ_TYPE_TASK_SUSPEND            (OS_OBJ_TYPE)CPU_TYPE_CREATE('T', 'S', 'U', 'S')
N#define  OS_OBJ_TYPE_TICK                    (OS_OBJ_TYPE)CPU_TYPE_CREATE('T', 'I', 'C', 'K')
N#define  OS_OBJ_TYPE_TMR                     (OS_OBJ_TYPE)CPU_TYPE_CREATE('T', 'M', 'R', ' ')
N
N/*
N========================================================================================================================
N*                                           Possible values for 'opt' argument
N========================================================================================================================
N*/
N
N#define  OS_OPT_NONE                         (OS_OPT)(0x0000u)
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                    DELETE OPTIONS
N------------------------------------------------------------------------------------------------------------------------
N*/
N
N#define  OS_OPT_DEL_NO_PEND                  (OS_OPT)(0x0000u)
N#define  OS_OPT_DEL_ALWAYS                   (OS_OPT)(0x0001u)
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                     PEND OPTIONS
N------------------------------------------------------------------------------------------------------------------------
N*/
N
N#define  OS_OPT_PEND_FLAG_MASK               (OS_OPT)(0x000Fu)
N#define  OS_OPT_PEND_FLAG_CLR_ALL            (OS_OPT)(0x0001u)  /* Wait for ALL    the bits specified to be CLR       */
N#define  OS_OPT_PEND_FLAG_CLR_AND            (OS_OPT)(0x0001u)
N
N#define  OS_OPT_PEND_FLAG_CLR_ANY            (OS_OPT)(0x0002u)  /* Wait for ANY of the bits specified to be CLR       */
N#define  OS_OPT_PEND_FLAG_CLR_OR             (OS_OPT)(0x0002u)
N
N#define  OS_OPT_PEND_FLAG_SET_ALL            (OS_OPT)(0x0004u)  /* Wait for ALL    the bits specified to be SET       */
N#define  OS_OPT_PEND_FLAG_SET_AND            (OS_OPT)(0x0004u)
N
N#define  OS_OPT_PEND_FLAG_SET_ANY            (OS_OPT)(0x0008u)  /* Wait for ANY of the bits specified to be SET       */
N#define  OS_OPT_PEND_FLAG_SET_OR             (OS_OPT)(0x0008u)
N
N#define  OS_OPT_PEND_FLAG_CONSUME            (OS_OPT)(0x0100u)  /* Consume the flags if condition(s) satisfied        */
N
N
N#define  OS_OPT_PEND_BLOCKING                (OS_OPT)(0x0000u)
N#define  OS_OPT_PEND_NON_BLOCKING            (OS_OPT)(0x8000u)
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                  PEND ABORT OPTIONS
N------------------------------------------------------------------------------------------------------------------------
N*/
N
N#define  OS_OPT_PEND_ABORT_1                 (OS_OPT)(0x0000u)  /* Pend abort a single waiting task                   */
N#define  OS_OPT_PEND_ABORT_ALL               (OS_OPT)(0x0100u)  /* Pend abort ALL tasks waiting                       */
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                     POST OPTIONS
N------------------------------------------------------------------------------------------------------------------------
N*/
N
N
N#define  OS_OPT_POST_NONE                    (OS_OPT)(0x0000u)
N
N#define  OS_OPT_POST_FLAG_SET                (OS_OPT)(0x0000u)
N#define  OS_OPT_POST_FLAG_CLR                (OS_OPT)(0x0001u)
N
N#define  OS_OPT_POST_FIFO                    (OS_OPT)(0x0000u)  /* Default is to post FIFO                            */
N#define  OS_OPT_POST_LIFO                    (OS_OPT)(0x0010u)  /* Post to highest priority task waiting              */
N#define  OS_OPT_POST_1                       (OS_OPT)(0x0000u)  /* Post message to highest priority task waiting      */
N#define  OS_OPT_POST_ALL                     (OS_OPT)(0x0200u)  /* Broadcast message to ALL tasks waiting             */
N
N#define  OS_OPT_POST_NO_SCHED                (OS_OPT)(0x8000u)  /* Do not call the scheduler if this is selected      */
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                     TASK OPTIONS
N------------------------------------------------------------------------------------------------------------------------
N*/
N
N#define  OS_OPT_TASK_NONE                    (OS_OPT)(0x0000u)  /* No option selected                                 */
N#define  OS_OPT_TASK_STK_CHK                 (OS_OPT)(0x0001u)  /* Enable stack checking for the task                 */
N#define  OS_OPT_TASK_STK_CLR                 (OS_OPT)(0x0002u)  /* Clear the stack when the task is create            */
N#define  OS_OPT_TASK_SAVE_FP                 (OS_OPT)(0x0004u)  /* Save the contents of any floating-point registers  */
N#define  OS_OPT_TASK_NO_TLS                  (OS_OPT)(0x0008u)  /* Specifies the task DOES NOT require TLS support    */
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                     TIME OPTIONS
N------------------------------------------------------------------------------------------------------------------------
N*/
N
N#define  OS_OPT_TIME_DLY                             DEF_BIT_NONE
N#define  OS_OPT_TIME_TIMEOUT                ((OS_OPT)DEF_BIT_01)
N#define  OS_OPT_TIME_MATCH                  ((OS_OPT)DEF_BIT_02)
N#define  OS_OPT_TIME_PERIODIC               ((OS_OPT)DEF_BIT_03)
N
N#define  OS_OPT_TIME_HMSM_STRICT            ((OS_OPT)DEF_BIT_NONE)
N#define  OS_OPT_TIME_HMSM_NON_STRICT        ((OS_OPT)DEF_BIT_04)
N
N#define  OS_OPT_TIME_MASK                   ((OS_OPT)(OS_OPT_TIME_DLY      | \
N                                                      OS_OPT_TIME_TIMEOUT  | \
N                                                      OS_OPT_TIME_PERIODIC | \
N                                                      OS_OPT_TIME_MATCH))
X#define  OS_OPT_TIME_MASK                   ((OS_OPT)(OS_OPT_TIME_DLY      |                                                       OS_OPT_TIME_TIMEOUT  |                                                       OS_OPT_TIME_PERIODIC |                                                       OS_OPT_TIME_MATCH))
N
N#define  OS_OPT_TIME_OPTS_MASK                       (OS_OPT_TIME_DLY            | \
N                                                      OS_OPT_TIME_TIMEOUT        | \
N                                                      OS_OPT_TIME_PERIODIC       | \
N                                                      OS_OPT_TIME_MATCH          | \
N                                                      OS_OPT_TIME_HMSM_NON_STRICT)
X#define  OS_OPT_TIME_OPTS_MASK                       (OS_OPT_TIME_DLY            |                                                       OS_OPT_TIME_TIMEOUT        |                                                       OS_OPT_TIME_PERIODIC       |                                                       OS_OPT_TIME_MATCH          |                                                       OS_OPT_TIME_HMSM_NON_STRICT)
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                    TIMER OPTIONS
N------------------------------------------------------------------------------------------------------------------------
N*/
N
N#define  OS_OPT_TMR_NONE                          (OS_OPT)(0u)  /* No option selected                                 */
N
N#define  OS_OPT_TMR_ONE_SHOT                      (OS_OPT)(1u)  /* Timer will not auto restart when it expires        */
N#define  OS_OPT_TMR_PERIODIC                      (OS_OPT)(2u)  /* Timer will     auto restart when it expires        */
N
N#define  OS_OPT_TMR_CALLBACK                      (OS_OPT)(3u)  /* OSTmrStop() option to call 'callback' w/ timer arg */
N#define  OS_OPT_TMR_CALLBACK_ARG                  (OS_OPT)(4u)  /* OSTmrStop() option to call 'callback' w/ new   arg */
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                     TIMER STATES
N------------------------------------------------------------------------------------------------------------------------
N*/
N
N#define  OS_TMR_STATE_UNUSED                    (OS_STATE)(0u)
N#define  OS_TMR_STATE_STOPPED                   (OS_STATE)(1u)
N#define  OS_TMR_STATE_RUNNING                   (OS_STATE)(2u)
N#define  OS_TMR_STATE_COMPLETED                 (OS_STATE)(3u)
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                       PRIORITY
N------------------------------------------------------------------------------------------------------------------------
N*/
N                                                                    /* Dflt prio to init task TCB                     */
N#define  OS_PRIO_INIT                       (OS_PRIO)(OS_CFG_PRIO_MAX)
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                 TIMER TICK THRESHOLDS
N------------------------------------------------------------------------------------------------------------------------
N*/
N                                                                    /* Threshold to init previous tick time           */
N#define  OS_TICK_TH_INIT                    (OS_TICK)(DEF_BIT       ((sizeof(OS_TICK) * DEF_OCTET_NBR_BITS) - 1u))
N
N                                                                    /* Threshold to check if tick time already ready  */
N#define  OS_TICK_TH_RDY                     (OS_TICK)(DEF_BIT_FIELD(((sizeof(OS_TICK) * DEF_OCTET_NBR_BITS) / 2u), \
N                                                                    ((sizeof(OS_TICK) * DEF_OCTET_NBR_BITS) / 2u)))
X#define  OS_TICK_TH_RDY                     (OS_TICK)(DEF_BIT_FIELD(((sizeof(OS_TICK) * DEF_OCTET_NBR_BITS) / 2u),                                                                     ((sizeof(OS_TICK) * DEF_OCTET_NBR_BITS) / 2u)))
N
N/*$PAGE*/
N/*
N************************************************************************************************************************
N************************************************************************************************************************
N*                                                E N U M E R A T I O N S
N************************************************************************************************************************
N************************************************************************************************************************
N*/
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                      ERROR CODES
N------------------------------------------------------------------------------------------------------------------------
N*/
N
Ntypedef  enum  os_err {
N    OS_ERR_NONE                      =     0u,
N
N    OS_ERR_A                         = 10000u,
N    OS_ERR_ACCEPT_ISR                = 10001u,
N
N    OS_ERR_B                         = 11000u,
N
N    OS_ERR_C                         = 12000u,
N    OS_ERR_CREATE_ISR                = 12001u,
N
N    OS_ERR_D                         = 13000u,
N    OS_ERR_DEL_ISR                   = 13001u,
N
N    OS_ERR_E                         = 14000u,
N
N    OS_ERR_F                         = 15000u,
N    OS_ERR_FATAL_RETURN              = 15001u,
N
N    OS_ERR_FLAG_GRP_DEPLETED         = 15101u,
N    OS_ERR_FLAG_NOT_RDY              = 15102u,
N    OS_ERR_FLAG_PEND_OPT             = 15103u,
N    OS_ERR_FLUSH_ISR                 = 15104u,
N
N    OS_ERR_G                         = 16000u,
N
N    OS_ERR_H                         = 17000u,
N
N    OS_ERR_I                         = 18000u,
N    OS_ERR_ILLEGAL_CREATE_RUN_TIME   = 18001u,
N    OS_ERR_INT_Q                     = 18002u,
N    OS_ERR_INT_Q_FULL                = 18003u,
N    OS_ERR_INT_Q_SIZE                = 18004u,
N    OS_ERR_INT_Q_STK_INVALID         = 18005u,
N    OS_ERR_INT_Q_STK_SIZE_INVALID    = 18006u,
N
N    OS_ERR_J                         = 19000u,
N
N    OS_ERR_K                         = 20000u,
N
N    OS_ERR_L                         = 21000u,
N    OS_ERR_LOCK_NESTING_OVF          = 21001u,
N
N    OS_ERR_M                         = 22000u,
N
N    OS_ERR_MEM_CREATE_ISR            = 22201u,
N    OS_ERR_MEM_FULL                  = 22202u,
N    OS_ERR_MEM_INVALID_P_ADDR        = 22203u,
N    OS_ERR_MEM_INVALID_BLKS          = 22204u,
N    OS_ERR_MEM_INVALID_PART          = 22205u,
N    OS_ERR_MEM_INVALID_P_BLK         = 22206u,
N    OS_ERR_MEM_INVALID_P_MEM         = 22207u,
N    OS_ERR_MEM_INVALID_P_DATA        = 22208u,
N    OS_ERR_MEM_INVALID_SIZE          = 22209u,
N    OS_ERR_MEM_NO_FREE_BLKS          = 22210u,
N
N    OS_ERR_MSG_POOL_EMPTY            = 22301u,
N    OS_ERR_MSG_POOL_NULL_PTR         = 22302u,
N
N    OS_ERR_MUTEX_NOT_OWNER           = 22401u,
N    OS_ERR_MUTEX_OWNER               = 22402u,
N    OS_ERR_MUTEX_NESTING             = 22403u,
N
N    OS_ERR_N                         = 23000u,
N    OS_ERR_NAME                      = 23001u,
N    OS_ERR_NO_MORE_ID_AVAIL          = 23002u,
N
N    OS_ERR_O                         = 24000u,
N    OS_ERR_OBJ_CREATED               = 24001u,
N    OS_ERR_OBJ_DEL                   = 24002u,
N    OS_ERR_OBJ_PTR_NULL              = 24003u,
N    OS_ERR_OBJ_TYPE                  = 24004u,
N
N    OS_ERR_OPT_INVALID               = 24101u,
N
N    OS_ERR_OS_NOT_RUNNING            = 24201u,
N    OS_ERR_OS_RUNNING                = 24202u,
N
N    OS_ERR_P                         = 25000u,
N    OS_ERR_PEND_ABORT                = 25001u,
N    OS_ERR_PEND_ABORT_ISR            = 25002u,
N    OS_ERR_PEND_ABORT_NONE           = 25003u,
N    OS_ERR_PEND_ABORT_SELF           = 25004u,
N    OS_ERR_PEND_DEL                  = 25005u,
N    OS_ERR_PEND_ISR                  = 25006u,
N    OS_ERR_PEND_LOCKED               = 25007u,
N    OS_ERR_PEND_WOULD_BLOCK          = 25008u,
N
N    OS_ERR_POST_NULL_PTR             = 25101u,
N    OS_ERR_POST_ISR                  = 25102u,
N
N    OS_ERR_PRIO_EXIST                = 25201u,
N    OS_ERR_PRIO                      = 25202u,
N    OS_ERR_PRIO_INVALID              = 25203u,
N
N    OS_ERR_PTR_INVALID               = 25301u,
N
N    OS_ERR_Q                         = 26000u,
N    OS_ERR_Q_FULL                    = 26001u,
N    OS_ERR_Q_EMPTY                   = 26002u,
N    OS_ERR_Q_MAX                     = 26003u,
N    OS_ERR_Q_SIZE                    = 26004u,
N
N    OS_ERR_R                         = 27000u,
N    OS_ERR_REG_ID_INVALID            = 27001u,
N    OS_ERR_ROUND_ROBIN_1             = 27002u,
N    OS_ERR_ROUND_ROBIN_DISABLED      = 27003u,
N
N    OS_ERR_S                         = 28000u,
N    OS_ERR_SCHED_INVALID_TIME_SLICE  = 28001u,
N    OS_ERR_SCHED_LOCK_ISR            = 28002u,
N    OS_ERR_SCHED_LOCKED              = 28003u,
N    OS_ERR_SCHED_NOT_LOCKED          = 28004u,
N    OS_ERR_SCHED_UNLOCK_ISR          = 28005u,
N
N    OS_ERR_SEM_OVF                   = 28101u,
N    OS_ERR_SET_ISR                   = 28102u,
N
N    OS_ERR_STAT_RESET_ISR            = 28201u,
N    OS_ERR_STAT_PRIO_INVALID         = 28202u,
N    OS_ERR_STAT_STK_INVALID          = 28203u,
N    OS_ERR_STAT_STK_SIZE_INVALID     = 28204u,
N    OS_ERR_STATE_INVALID             = 28205u,
N    OS_ERR_STATUS_INVALID            = 28206u,
N    OS_ERR_STK_INVALID               = 28207u,
N    OS_ERR_STK_SIZE_INVALID          = 28208u,
N    OS_ERR_STK_LIMIT_INVALID         = 28209u,
N
N    OS_ERR_T                         = 29000u,
N    OS_ERR_TASK_CHANGE_PRIO_ISR      = 29001u,
N    OS_ERR_TASK_CREATE_ISR           = 29002u,
N    OS_ERR_TASK_DEL                  = 29003u,
N    OS_ERR_TASK_DEL_IDLE             = 29004u,
N    OS_ERR_TASK_DEL_INVALID          = 29005u,
N    OS_ERR_TASK_DEL_ISR              = 29006u,
N    OS_ERR_TASK_INVALID              = 29007u,
N    OS_ERR_TASK_NO_MORE_TCB          = 29008u,
N    OS_ERR_TASK_NOT_DLY              = 29009u,
N    OS_ERR_TASK_NOT_EXIST            = 29010u,
N    OS_ERR_TASK_NOT_SUSPENDED        = 29011u,
N    OS_ERR_TASK_OPT                  = 29012u,
N    OS_ERR_TASK_RESUME_ISR           = 29013u,
N    OS_ERR_TASK_RESUME_PRIO          = 29014u,
N    OS_ERR_TASK_RESUME_SELF          = 29015u,
N    OS_ERR_TASK_RUNNING              = 29016u,
N    OS_ERR_TASK_STK_CHK_ISR          = 29017u,
N    OS_ERR_TASK_SUSPENDED            = 29018u,
N    OS_ERR_TASK_SUSPEND_IDLE         = 29019u,
N    OS_ERR_TASK_SUSPEND_INT_HANDLER  = 29020u,
N    OS_ERR_TASK_SUSPEND_ISR          = 29021u,
N    OS_ERR_TASK_SUSPEND_PRIO         = 29022u,
N    OS_ERR_TASK_WAITING              = 29023u,
N
N    OS_ERR_TCB_INVALID               = 29101u,
N
N    OS_ERR_TLS_ID_INVALID            = 29120u,
N    OS_ERR_TLS_ISR                   = 29121u,
N    OS_ERR_TLS_NO_MORE_AVAIL         = 29122u,
N    OS_ERR_TLS_NOT_EN                = 29123u,
N    OS_ERR_TLS_DESTRUCT_ASSIGNED     = 29124u,
N
N    OS_ERR_TICK_PRIO_INVALID         = 29201u,
N    OS_ERR_TICK_STK_INVALID          = 29202u,
N    OS_ERR_TICK_STK_SIZE_INVALID     = 29203u,
N    OS_ERR_TICK_WHEEL_SIZE           = 29204u,
N
N    OS_ERR_TIME_DLY_ISR              = 29301u,
N    OS_ERR_TIME_DLY_RESUME_ISR       = 29302u,
N    OS_ERR_TIME_GET_ISR              = 29303u,
N    OS_ERR_TIME_INVALID_HOURS        = 29304u,
N    OS_ERR_TIME_INVALID_MINUTES      = 29305u,
N    OS_ERR_TIME_INVALID_SECONDS      = 29306u,
N    OS_ERR_TIME_INVALID_MILLISECONDS = 29307u,
N    OS_ERR_TIME_NOT_DLY              = 29308u,
N    OS_ERR_TIME_SET_ISR              = 29309u,
N    OS_ERR_TIME_ZERO_DLY             = 29310u,
N
N    OS_ERR_TIMEOUT                   = 29401u,
N
N    OS_ERR_TMR_INACTIVE              = 29501u,
N    OS_ERR_TMR_INVALID_DEST          = 29502u,
N    OS_ERR_TMR_INVALID_DLY           = 29503u,
N    OS_ERR_TMR_INVALID_PERIOD        = 29504u,
N    OS_ERR_TMR_INVALID_STATE         = 29505u,
N    OS_ERR_TMR_INVALID               = 29506u,
N    OS_ERR_TMR_ISR                   = 29507u,
N    OS_ERR_TMR_NO_CALLBACK           = 29508u,
N    OS_ERR_TMR_NON_AVAIL             = 29509u,
N    OS_ERR_TMR_PRIO_INVALID          = 29510u,
N    OS_ERR_TMR_STK_INVALID           = 29511u,
N    OS_ERR_TMR_STK_SIZE_INVALID      = 29512u,
N    OS_ERR_TMR_STOPPED               = 29513u,
N
N    OS_ERR_U                         = 30000u,
N
N    OS_ERR_V                         = 31000u,
N
N    OS_ERR_W                         = 32000u,
N
N    OS_ERR_X                         = 33000u,
N
N    OS_ERR_Y                         = 34000u,
N    OS_ERR_YIELD_ISR                 = 34001u,
N
N    OS_ERR_Z                         = 35000u
N} OS_ERR;
N
N
N/*$PAGE*/
N/*
N************************************************************************************************************************
N************************************************************************************************************************
N*                                                  D A T A   T Y P E S
N************************************************************************************************************************
N************************************************************************************************************************
N*/
N
Ntypedef  struct  os_flag_grp         OS_FLAG_GRP;
N
Ntypedef  struct  os_mem              OS_MEM;
N
Ntypedef  struct  os_msg              OS_MSG;
Ntypedef  struct  os_msg_pool         OS_MSG_POOL;
Ntypedef  struct  os_msg_q            OS_MSG_Q;
N
Ntypedef  struct  os_mutex            OS_MUTEX;
N
Ntypedef  struct  os_int_q            OS_INT_Q;
N
Ntypedef  struct  os_q                OS_Q;
N
Ntypedef  struct  os_sem              OS_SEM;
N
Ntypedef  void                      (*OS_TASK_PTR)(void *p_arg);
N
Ntypedef  struct  os_tcb              OS_TCB;
N
N#if defined(OS_CFG_TLS_TBL_SIZE) && (OS_CFG_TLS_TBL_SIZE > 0u)
X#if 0L && (OS_CFG_TLS_TBL_SIZE > 0u)
Stypedef  void                       *OS_TLS;
S
Stypedef  CPU_DATA                    OS_TLS_ID;
S
Stypedef  void                      (*OS_TLS_DESTRUCT_PTR)(OS_TCB    *p_tcb,
S                                                          OS_TLS_ID  id,
S                                                          OS_TLS     value);
N#endif
N
Ntypedef  struct  os_rdy_list         OS_RDY_LIST;
N
Ntypedef  struct  os_tick_spoke       OS_TICK_SPOKE;
N
Ntypedef  void                      (*OS_TMR_CALLBACK_PTR)(void *p_tmr, void *p_arg);
Ntypedef  struct  os_tmr              OS_TMR;
Ntypedef  struct  os_tmr_spoke        OS_TMR_SPOKE;
N
N
Ntypedef  struct  os_pend_data        OS_PEND_DATA;
Ntypedef  struct  os_pend_list        OS_PEND_LIST;
Ntypedef  struct  os_pend_obj         OS_PEND_OBJ;
N
N#if OS_CFG_APP_HOOKS_EN > 0u
X#if 0u > 0u
Stypedef  void                      (*OS_APP_HOOK_VOID)(void);
Stypedef  void                      (*OS_APP_HOOK_TCB)(OS_TCB *p_tcb);
N#endif
N
N/*$PAGE*/
N/*
N************************************************************************************************************************
N************************************************************************************************************************
N*                                          D A T A   S T R U C T U R E S
N************************************************************************************************************************
N************************************************************************************************************************
N*/
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                    ISR POST DATA
N------------------------------------------------------------------------------------------------------------------------
N*/
N
N#if OS_CFG_ISR_POST_DEFERRED_EN > 0u
X#if 0u > 0u
Sstruct  os_int_q {
S    OS_OBJ_TYPE          Type;                              /* Type of object placed in the circular list             */
S    OS_INT_Q            *NextPtr;                           /* Pointer to next OS_INT_Q in  circular list             */
S    void                *ObjPtr;                            /* Pointer to object placed in the queue                  */
S    void                *MsgPtr;                            /* Pointer to message if posting to a message queue       */
S    OS_MSG_SIZE          MsgSize;                           /* Message Size       if posting to a message queue       */
S    OS_FLAGS             Flags;                             /* Value of flags if posting to an event flag group       */
S    OS_OPT               Opt;                               /* Post Options                                           */
S    CPU_TS               TS;                                /* Timestamp                                              */
S};
N#endif
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                      READY LIST
N------------------------------------------------------------------------------------------------------------------------
N*/
N
Nstruct  os_rdy_list {
N    OS_TCB              *HeadPtr;                           /* Pointer to task that will run at selected priority     */
N    OS_TCB              *TailPtr;                           /* Pointer to last task          at selected priority     */
N    OS_OBJ_QTY           NbrEntries;                        /* Number of entries             at selected priority     */
N};
N
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                PEND DATA and PEND LIST
N------------------------------------------------------------------------------------------------------------------------
N*/
N
Nstruct  os_pend_data {
N    OS_PEND_DATA        *PrevPtr;
N    OS_PEND_DATA        *NextPtr;
N    OS_TCB              *TCBPtr;
N    OS_PEND_OBJ         *PendObjPtr;
N    OS_PEND_OBJ         *RdyObjPtr;
N    void                *RdyMsgPtr;
N    OS_MSG_SIZE          RdyMsgSize;
N    CPU_TS               RdyTS;
N};
N
N
Nstruct  os_pend_list {
N    OS_PEND_DATA        *HeadPtr;
N    OS_PEND_DATA        *TailPtr;
N    OS_OBJ_QTY           NbrEntries;
N};
N
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                       PEND OBJ
N*
N* Note(s) : (1) The 'os_pend_obj' structure data type is a template/subset for specific kernel objects' data types: 
N*               'os_flag_grp', 'os_mutex', 'os_q', and 'os_sem'.  Each specific kernel object data type MUST define 
N*               ALL generic OS pend object parameters, synchronized in both the sequential order & data type of each 
N*               parameter.
N*
N*               Thus, ANY modification to the sequential order or data types of OS pend object parameters MUST be 
N*               appropriately synchronized between the generic OS pend object data type & ALL specific kernel objects' 
N*               data types.
N------------------------------------------------------------------------------------------------------------------------
N*/
N
Nstruct  os_pend_obj {
N    OS_OBJ_TYPE          Type;
N    CPU_CHAR            *NamePtr;
N    OS_PEND_LIST         PendList;                          /* List of tasks pending on object                        */
N#if OS_CFG_DBG_EN > 0u
X#if 0u > 0u
S    void                *DbgPrevPtr;
S    void                *DbgNextPtr;
S    CPU_CHAR            *DbgNamePtr;
N#endif
N};
N
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                     EVENT FLAGS
N*
N* Note(s) : See  PEND OBJ  Note #1'.
N------------------------------------------------------------------------------------------------------------------------
N*/
N
N
Nstruct  os_flag_grp {                                       /* Event Flag Group                                       */
N                                                            /* ------------------ GENERIC  MEMBERS ------------------ */
N    OS_OBJ_TYPE          Type;                              /* Should be set to OS_OBJ_TYPE_FLAG                      */
N    CPU_CHAR            *NamePtr;                           /* Pointer to Event Flag Name (NUL terminated ASCII)      */
N    OS_PEND_LIST         PendList;                          /* List of tasks waiting on event flag group              */
N#if OS_CFG_DBG_EN > 0u
X#if 0u > 0u
S    OS_FLAG_GRP         *DbgPrevPtr;
S    OS_FLAG_GRP         *DbgNextPtr;
S    CPU_CHAR            *DbgNamePtr;
N#endif
N                                                            /* ------------------ SPECIFIC MEMBERS ------------------ */
N    OS_FLAGS             Flags;                             /* 8, 16 or 32 bit flags                                  */
N    CPU_TS               TS;                                /* Timestamp of when last post occurred                   */
N};
N
N/*$PAGE*/
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                   MEMORY PARTITIONS
N------------------------------------------------------------------------------------------------------------------------
N*/
N
N
Nstruct os_mem {                                             /* MEMORY CONTROL BLOCK                                   */
N    OS_OBJ_TYPE          Type;                              /* Should be set to OS_OBJ_TYPE_MEM                       */
N    void                *AddrPtr;                           /* Pointer to beginning of memory partition               */
N    CPU_CHAR            *NamePtr;
N    void                *FreeListPtr;                       /* Pointer to list of free memory blocks                  */
N    OS_MEM_SIZE          BlkSize;                           /* Size (in bytes) of each block of memory                */
N    OS_MEM_QTY           NbrMax;                            /* Total number of blocks in this partition               */
N    OS_MEM_QTY           NbrFree;                           /* Number of memory blocks remaining in this partition    */
N#if OS_CFG_DBG_EN > 0u
X#if 0u > 0u
S    OS_MEM              *DbgPrevPtr;
S    OS_MEM              *DbgNextPtr;
N#endif
N};
N
N/*$PAGE*/
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                       MESSAGES
N------------------------------------------------------------------------------------------------------------------------
N*/
N
Nstruct  os_msg {                                            /* MESSAGE CONTROL BLOCK                                  */
N    OS_MSG              *NextPtr;                           /* Pointer to next message                                */
N    void                *MsgPtr;                            /* Actual message                                         */
N    OS_MSG_SIZE          MsgSize;                           /* Size of the message (in # bytes)                       */
N    CPU_TS               MsgTS;                             /* Time stamp of when message was sent                    */
N};
N
N
N
N
Nstruct  os_msg_pool {                                       /* OS_MSG POOL                                            */
N    OS_MSG              *NextPtr;                           /* Pointer to next message                                */
N    OS_MSG_QTY           NbrFree;                           /* Number of messages available from this pool            */
N    OS_MSG_QTY           NbrUsed;                           /* Current number of messages used                        */
N    OS_MSG_QTY           NbrUsedMax;                        /* Peak number of messages used                           */
N};
N
N
N
Nstruct  os_msg_q {                                          /* OS_MSG_Q                                               */
N    OS_MSG              *InPtr;                             /* Pointer to next OS_MSG to be inserted  in   the queue  */
N    OS_MSG              *OutPtr;                            /* Pointer to next OS_MSG to be extracted from the queue  */
N    OS_MSG_QTY           NbrEntriesSize;                    /* Maximum allowable number of entries in the queue       */
N    OS_MSG_QTY           NbrEntries;                        /* Current number of entries in the queue                 */
N    OS_MSG_QTY           NbrEntriesMax;                     /* Peak number of entries in the queue                    */
N};
N
N/*$PAGE*/
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                              MUTUAL EXCLUSION SEMAPHORES
N*
N* Note(s) : See  PEND OBJ  Note #1'.
N------------------------------------------------------------------------------------------------------------------------
N*/
N
Nstruct  os_mutex {                                          /* Mutual Exclusion Semaphore                             */
N                                                            /* ------------------ GENERIC  MEMBERS ------------------ */
N    OS_OBJ_TYPE          Type;                              /* Should be set to OS_OBJ_TYPE_MUTEX                     */
N    CPU_CHAR            *NamePtr;                           /* Pointer to Mutex Name (NUL terminated ASCII)           */
N    OS_PEND_LIST         PendList;                          /* List of tasks waiting on mutex                         */
N#if OS_CFG_DBG_EN > 0u
X#if 0u > 0u
S    OS_MUTEX            *DbgPrevPtr;
S    OS_MUTEX            *DbgNextPtr;
S    CPU_CHAR            *DbgNamePtr;
N#endif
N                                                            /* ------------------ SPECIFIC MEMBERS ------------------ */
N    OS_TCB              *OwnerTCBPtr;
N    OS_PRIO              OwnerOriginalPrio;
N    OS_NESTING_CTR       OwnerNestingCtr;                   /* Mutex is available when the counter is 0               */
N    CPU_TS               TS;
N};
N
N/*$PAGE*/
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                    MESSAGE QUEUES
N*
N* Note(s) : See  PEND OBJ  Note #1'.
N------------------------------------------------------------------------------------------------------------------------
N*/
N
Nstruct  os_q {                                              /* Message Queue                                          */
N                                                            /* ------------------ GENERIC  MEMBERS ------------------ */
N    OS_OBJ_TYPE          Type;                              /* Should be set to OS_OBJ_TYPE_Q                         */
N    CPU_CHAR            *NamePtr;                           /* Pointer to Message Queue Name (NUL terminated ASCII)   */
N    OS_PEND_LIST         PendList;                          /* List of tasks waiting on message queue                 */
N#if OS_CFG_DBG_EN > 0u
X#if 0u > 0u
S    OS_Q                *DbgPrevPtr;
S    OS_Q                *DbgNextPtr;
S    CPU_CHAR            *DbgNamePtr;
N#endif
N                                                            /* ------------------ SPECIFIC MEMBERS ------------------ */
N    OS_MSG_Q             MsgQ;                              /* List of messages                                       */
N};
N
N/*$PAGE*/
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                      SEMAPHORES
N*
N* Note(s) : See  PEND OBJ  Note #1'.
N------------------------------------------------------------------------------------------------------------------------
N*/
N
Nstruct  os_sem {                                            /* Semaphore                                              */
N                                                            /* ------------------ GENERIC  MEMBERS ------------------ */
N    OS_OBJ_TYPE          Type;                              /* Should be set to OS_OBJ_TYPE_SEM                       */
N    CPU_CHAR            *NamePtr;                           /* Pointer to Semaphore Name (NUL terminated ASCII)       */
N    OS_PEND_LIST         PendList;                          /* List of tasks waiting on semaphore                     */
N#if OS_CFG_DBG_EN > 0u
X#if 0u > 0u
S    OS_SEM              *DbgPrevPtr;
S    OS_SEM              *DbgNextPtr;
S    CPU_CHAR            *DbgNamePtr;
N#endif
N                                                            /* ------------------ SPECIFIC MEMBERS ------------------ */
N    OS_SEM_CTR           Ctr;
N    CPU_TS               TS;
N};
N
N/*$PAGE*/
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                  TASK CONTROL BLOCK
N------------------------------------------------------------------------------------------------------------------------
N*/
N
Nstruct os_tcb {
N    CPU_STK             *StkPtr;                            /* Pointer to current top of stack                        */
N
N    void                *ExtPtr;                            /* Pointer to user definable data for TCB extension       */
N
N    CPU_STK             *StkLimitPtr;                       /* Pointer used to set stack 'watermark' limit            */
N
N    OS_TCB              *NextPtr;                           /* Pointer to next     TCB in the TCB list                */
N    OS_TCB              *PrevPtr;                           /* Pointer to previous TCB in the TCB list                */
N
N    OS_TCB              *TickNextPtr;
N    OS_TCB              *TickPrevPtr;
N
N    OS_TICK_SPOKE       *TickSpokePtr;                      /* Pointer to tick spoke if task is in the tick list      */
N
N    CPU_CHAR            *NamePtr;                           /* Pointer to task name                                   */
N
N    CPU_STK             *StkBasePtr;                        /* Pointer to base address of stack                       */
N
N#if defined(OS_CFG_TLS_TBL_SIZE) && (OS_CFG_TLS_TBL_SIZE > 0u)
X#if 0L && (OS_CFG_TLS_TBL_SIZE > 0u)
S    OS_TLS               TLS_Tbl[OS_CFG_TLS_TBL_SIZE];
N#endif
N
N    OS_TASK_PTR          TaskEntryAddr;                     /* Pointer to task entry point address                    */
N    void                *TaskEntryArg;                      /* Argument passed to task when it was created            */
N
N    OS_PEND_DATA        *PendDataTblPtr;                    /* Pointer to list containing objects pended on           */
N    OS_STATE             PendOn;                            /* Indicates what task is pending on                      */
N    OS_STATUS            PendStatus;                        /* Pend status                                            */
N
N    OS_STATE             TaskState;                         /* See OS_TASK_STATE_xxx                                  */
N    OS_PRIO              Prio;                              /* Task priority (0 == highest)                           */
N    CPU_STK_SIZE         StkSize;                           /* Size of task stack (in number of stack elements)       */
N    OS_OPT               Opt;                               /* Task options as passed by OSTaskCreate()               */
N
N    OS_OBJ_QTY           PendDataTblEntries;                /* Size of array of objects to pend on                    */
N
N    CPU_TS               TS;                                /* Timestamp                                              */
N
N    OS_SEM_CTR           SemCtr;                            /* Task specific semaphore counter                        */
N
N                                                            /* DELAY / TIMEOUT                                        */
N    OS_TICK              TickCtrPrev;                       /* Previous time when task was            ready           */
N    OS_TICK              TickCtrMatch;                      /* Absolute time when task is going to be ready           */
N    OS_TICK              TickRemain;                        /* Number of ticks remaining for a match (updated at ...  */
N                                                            /* ... run-time by OS_StatTask()                          */
N    OS_TICK              TimeQuanta;
N    OS_TICK              TimeQuantaCtr;
N
N#if OS_MSG_EN > 0u
X#if (((0u > 0u) || (0u > 0u)) ? 1u : 0u) > 0u
S    void                *MsgPtr;                            /* Message received                                       */
S    OS_MSG_SIZE          MsgSize;
N#endif
N
N#if OS_CFG_TASK_Q_EN > 0u
X#if 0u > 0u
S    OS_MSG_Q             MsgQ;                              /* Message queue associated with task                     */
S#if OS_CFG_TASK_PROFILE_EN > 0u
S    CPU_TS               MsgQPendTime;                      /* Time it took for signal to be received                 */
S    CPU_TS               MsgQPendTimeMax;                   /* Max amount of time it took for signal to be received   */
S#endif
N#endif
N
N#if OS_CFG_TASK_REG_TBL_SIZE > 0u
X#if 1u > 0u
N    OS_REG               RegTbl[OS_CFG_TASK_REG_TBL_SIZE];  /* Task specific registers                                */
X    OS_REG               RegTbl[1u];   
N#endif
N
N#if OS_CFG_FLAG_EN > 0u
X#if 0u > 0u
S    OS_FLAGS             FlagsPend;                         /* Event flag(s) to wait on                               */
S    OS_FLAGS             FlagsRdy;                          /* Event flags that made task ready to run                */
S    OS_OPT               FlagsOpt;                          /* Options (See OS_OPT_FLAG_xxx)                          */
N#endif
N
N#if OS_CFG_TASK_SUSPEND_EN > 0u
X#if 0u > 0u
S    OS_NESTING_CTR       SuspendCtr;                        /* Nesting counter for OSTaskSuspend()                    */
N#endif
N
N#if OS_CFG_TASK_PROFILE_EN > 0u
X#if 0u > 0u
S    OS_CPU_USAGE         CPUUsage;                          /* CPU Usage of task (0.00-100.00%)                       */
S    OS_CPU_USAGE         CPUUsageMax;                       /* CPU Usage of task (0.00-100.00%) - Peak                */
S    OS_CTX_SW_CTR        CtxSwCtr;                          /* Number of time the task was switched in                */
S    CPU_TS               CyclesDelta;                       /* value of OS_TS_GET() - .CyclesStart                    */
S    CPU_TS               CyclesStart;                       /* Snapshot of cycle counter at start of task resumption  */
S    OS_CYCLES            CyclesTotal;                       /* Total number of # of cycles the task has been running  */
S    OS_CYCLES            CyclesTotalPrev;                   /* Snapshot of previous # of cycles                       */
S
S    CPU_TS               SemPendTime;                       /* Time it took for signal to be received                 */
S    CPU_TS               SemPendTimeMax;                    /* Max amount of time it took for signal to be received   */
N#endif
N
N#if OS_CFG_STAT_TASK_STK_CHK_EN > 0u
X#if 1u > 0u
N    CPU_STK_SIZE         StkUsed;                           /* Number of stack elements used from the stack           */
N    CPU_STK_SIZE         StkFree;                           /* Number of stack elements free on   the stack           */
N#endif
N
N#ifdef CPU_CFG_INT_DIS_MEAS_EN
S    CPU_TS               IntDisTimeMax;                     /* Maximum interrupt disable time                         */
N#endif
N#if OS_CFG_SCHED_LOCK_TIME_MEAS_EN > 0u
X#if 0u > 0u
S    CPU_TS               SchedLockTimeMax;                  /* Maximum scheduler lock time                            */
N#endif
N
N#if OS_CFG_DBG_EN > 0u
X#if 0u > 0u
S    OS_TCB              *DbgPrevPtr;
S    OS_TCB              *DbgNextPtr;
S    CPU_CHAR            *DbgNamePtr;
N#endif
N};
N
N/*$PAGE*/
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                    TICK DATA TYPE
N------------------------------------------------------------------------------------------------------------------------
N*/
N
Nstruct  os_tick_spoke {
N    OS_TCB              *FirstPtr;                          /* Pointer to list of tasks in tick spoke                 */
N    OS_OBJ_QTY           NbrEntries;                        /* Current number of entries in the tick spoke            */
N    OS_OBJ_QTY           NbrEntriesMax;                     /* Peak number of entries in the tick spoke               */
N};
N
N
N/*
N------------------------------------------------------------------------------------------------------------------------
N*                                                   TIMER DATA TYPES
N------------------------------------------------------------------------------------------------------------------------
N*/
N
Nstruct  os_tmr {
N    OS_OBJ_TYPE          Type;
N    CPU_CHAR            *NamePtr;                           /* Name to give the timer                                 */
N    OS_TMR_CALLBACK_PTR  CallbackPtr;                       /* Function to call when timer expires                    */
N    void                *CallbackPtrArg;                    /* Argument to pass to function when timer expires        */
N    OS_TMR              *NextPtr;                           /* Double link list pointers                              */
N    OS_TMR              *PrevPtr;
N    OS_TICK              Match;                             /* Timer expires when OSTmrTickCtr matches this value     */
N    OS_TICK              Remain;                            /* Amount of time remaining before timer expires          */
N    OS_TICK              Dly;                               /* Delay before start of repeat                           */
N    OS_TICK              Period;                            /* Period to repeat timer                                 */
N    OS_OPT               Opt;                               /* Options (see OS_OPT_TMR_xxx)                           */
N    OS_STATE             State;
N#if OS_CFG_DBG_EN > 0u
X#if 0u > 0u
S    OS_TMR              *DbgPrevPtr;
S    OS_TMR              *DbgNextPtr;
N#endif
N};
N
N
N
Nstruct  os_tmr_spoke {
N    OS_TMR              *FirstPtr;                          /* Pointer to first timer in linked list                  */
N    OS_OBJ_QTY           NbrEntries;
N    OS_OBJ_QTY           NbrEntriesMax;
N};
N
N/*$PAGE*/
N/*
N************************************************************************************************************************
N************************************************************************************************************************
N*                                           G L O B A L   V A R I A B L E S
N************************************************************************************************************************
N************************************************************************************************************************
N*/
N
N#if OS_CFG_APP_HOOKS_EN > 0u
X#if 0u > 0u
SOS_EXT           OS_APP_HOOK_TCB            OS_AppTaskCreateHookPtr;    /* Application hooks                          */
SOS_EXT           OS_APP_HOOK_TCB            OS_AppTaskDelHookPtr;
SOS_EXT           OS_APP_HOOK_TCB            OS_AppTaskReturnHookPtr;
S
SOS_EXT           OS_APP_HOOK_VOID           OS_AppIdleTaskHookPtr;
SOS_EXT           OS_APP_HOOK_VOID           OS_AppStatTaskHookPtr;
SOS_EXT           OS_APP_HOOK_VOID           OS_AppTaskSwHookPtr;
SOS_EXT           OS_APP_HOOK_VOID           OS_AppTimeTickHookPtr;
N#endif
N
N                                                                        /* IDLE TASK -------------------------------- */
NOS_EXT            OS_IDLE_CTR               OSIdleTaskCtr;
Xextern            OS_IDLE_CTR               OSIdleTaskCtr;
NOS_EXT            OS_TCB                    OSIdleTaskTCB;
Xextern            OS_TCB                    OSIdleTaskTCB;
N
N                                                                        /* MISCELLANEOUS ---------------------------- */
NOS_EXT            OS_NESTING_CTR            OSIntNestingCtr;            /* Interrupt nesting level                    */
Xextern            OS_NESTING_CTR            OSIntNestingCtr;             
N#ifdef CPU_CFG_INT_DIS_MEAS_EN
SOS_EXT            CPU_TS                    OSIntDisTimeMax;            /* Overall interrupt disable time             */
N#endif
N
NOS_EXT            OS_STATE                  OSRunning;                  /* Flag indicating that kernel is running     */
Xextern            OS_STATE                  OSRunning;                   
N
N
N                                                                        /* ISR HANDLER TASK ------------------------- */
N#if OS_CFG_ISR_POST_DEFERRED_EN > 0u
X#if 0u > 0u
SOS_EXT            OS_INT_Q                 *OSIntQInPtr;
SOS_EXT            OS_INT_Q                 *OSIntQOutPtr;
SOS_EXT            OS_OBJ_QTY                OSIntQNbrEntries;
SOS_EXT            OS_OBJ_QTY                OSIntQNbrEntriesMax;
SOS_EXT            OS_OBJ_QTY                OSIntQOvfCtr;
SOS_EXT            OS_TCB                    OSIntQTaskTCB;
SOS_EXT            CPU_TS                    OSIntQTaskTimeMax;
N#endif
N
N                                                                        /* FLAGS ------------------------------------ */
N#if OS_CFG_FLAG_EN > 0u
X#if 0u > 0u
S#if OS_CFG_DBG_EN  > 0u
SOS_EXT            OS_FLAG_GRP              *OSFlagDbgListPtr;
S#endif
SOS_EXT            OS_OBJ_QTY                OSFlagQty;
N#endif
N
N                                                                        /* MEMORY MANAGEMENT ------------------------ */
N#if OS_CFG_MEM_EN > 0u
X#if 0u > 0u
S#if OS_CFG_DBG_EN > 0u
SOS_EXT            OS_MEM                   *OSMemDbgListPtr;
S#endif
SOS_EXT            OS_OBJ_QTY                OSMemQty;                   /* Number of memory partitions created        */
N#endif
N
N                                                                        /* OS_MSG POOL ------------------------------ */
N#if OS_MSG_EN > 0u
X#if (((0u > 0u) || (0u > 0u)) ? 1u : 0u) > 0u
SOS_EXT            OS_MSG_POOL               OSMsgPool;                  /* Pool of OS_MSG                             */
N#endif
N
N                                                                        /* MUTEX MANAGEMENT ------------------------- */
N#if OS_CFG_MUTEX_EN > 0u
X#if 0u > 0u
S#if OS_CFG_DBG_EN   > 0u
SOS_EXT            OS_MUTEX                 *OSMutexDbgListPtr;
S#endif
SOS_EXT            OS_OBJ_QTY                OSMutexQty;                 /* Number of mutexes created                  */
N#endif
N
N                                                                        /* PRIORITIES ------------------------------- */
NOS_EXT            OS_PRIO                   OSPrioCur;                  /* Priority of current task                   */
Xextern            OS_PRIO                   OSPrioCur;                   
NOS_EXT            OS_PRIO                   OSPrioHighRdy;              /* Priority of highest priority task          */
Xextern            OS_PRIO                   OSPrioHighRdy;               
NOS_EXT            OS_PRIO                   OSPrioSaved;                /* Saved priority level when Post Deferred    */
Xextern            OS_PRIO                   OSPrioSaved;                 
Nextern            CPU_DATA                  OSPrioTbl[OS_PRIO_TBL_SIZE];
Xextern            CPU_DATA                  OSPrioTbl[((16u - 1u) / ((4 * 8u)) + 1u)];
N
N                                                                        /* QUEUES ----------------------------------- */
N#if OS_CFG_Q_EN   > 0u
X#if 0u   > 0u
S#if OS_CFG_DBG_EN > 0u
SOS_EXT            OS_Q                     *OSQDbgListPtr;
S#endif
SOS_EXT            OS_OBJ_QTY                OSQQty;                     /* Number of message queues created           */
N#endif
N
N
N
N                                                                        /* READY LIST ------------------------------- */
NOS_EXT            OS_RDY_LIST               OSRdyList[OS_CFG_PRIO_MAX]; /* Table of tasks ready to run                */
Xextern            OS_RDY_LIST               OSRdyList[16u];  
N
N
N#ifdef OS_SAFETY_CRITICAL_IEC61508
SOS_EXT            CPU_BOOLEAN               OSSafetyCriticalStartFlag;  /* Flag indicating that all init. done        */
N#endif
N                                                                        /* SCHEDULER -------------------------------- */
N#if OS_CFG_SCHED_LOCK_TIME_MEAS_EN > 0u
X#if 0u > 0u
SOS_EXT            CPU_TS_TMR                OSSchedLockTimeBegin;       /* Scheduler lock time measurement            */
SOS_EXT            CPU_TS_TMR                OSSchedLockTimeMax;
SOS_EXT            CPU_TS_TMR                OSSchedLockTimeMaxCur;
N#endif
N
NOS_EXT            OS_NESTING_CTR            OSSchedLockNestingCtr;      /* Lock nesting level                         */
Xextern            OS_NESTING_CTR            OSSchedLockNestingCtr;       
N#if OS_CFG_SCHED_ROUND_ROBIN_EN > 0u
X#if 0u > 0u
SOS_EXT            OS_TICK                   OSSchedRoundRobinDfltTimeQuanta;
SOS_EXT            CPU_BOOLEAN               OSSchedRoundRobinEn;        /* Enable/Disable round-robin scheduling      */
N#endif
N                                                                        /* SEMAPHORES ------------------------------- */
N#if OS_CFG_SEM_EN > 0u
X#if 0u > 0u
S#if OS_CFG_DBG_EN > 0u
SOS_EXT            OS_SEM                   *OSSemDbgListPtr;
S#endif
SOS_EXT            OS_OBJ_QTY                OSSemQty;                   /* Number of semaphores created               */
N#endif
N
N                                                                        /* STATISTICS ------------------------------- */
N#if OS_CFG_STAT_TASK_EN > 0u
X#if 0u > 0u
SOS_EXT            CPU_BOOLEAN               OSStatResetFlag;            /* Force the reset of the computed statistics */
SOS_EXT            OS_CPU_USAGE              OSStatTaskCPUUsage;         /* CPU Usage in %                             */
SOS_EXT            OS_CPU_USAGE              OSStatTaskCPUUsageMax;      /* CPU Usage in % (Peak)                      */
SOS_EXT            OS_TICK                   OSStatTaskCtr;
SOS_EXT            OS_TICK                   OSStatTaskCtrMax;
SOS_EXT            OS_TICK                   OSStatTaskCtrRun;
SOS_EXT            CPU_BOOLEAN               OSStatTaskRdy;
SOS_EXT            OS_TCB                    OSStatTaskTCB;
SOS_EXT            CPU_TS                    OSStatTaskTimeMax;
N#endif
N
N                                                                        /* TASKS ------------------------------------ */
NOS_EXT            OS_CTX_SW_CTR             OSTaskCtxSwCtr;             /* Number of context switches                 */
Xextern            OS_CTX_SW_CTR             OSTaskCtxSwCtr;              
N#if OS_CFG_DBG_EN > 0u
X#if 0u > 0u
SOS_EXT            OS_TCB                   *OSTaskDbgListPtr;
N#endif
NOS_EXT            OS_OBJ_QTY                OSTaskQty;                  /* Number of tasks created                    */
Xextern            OS_OBJ_QTY                OSTaskQty;                   
N
N#if OS_CFG_TASK_REG_TBL_SIZE > 0u
X#if 1u > 0u
NOS_EXT            OS_REG_ID                 OSTaskRegNextAvailID;       /* Next available Task Register ID            */
Xextern            OS_REG_ID                 OSTaskRegNextAvailID;        
N#endif
N
N                                                                        /* TICK TASK -------------------------------- */
NOS_EXT            OS_TICK                   OSTickCtr;                  /* Cnts the #ticks since startup or last set  */
Xextern            OS_TICK                   OSTickCtr;                   
NOS_EXT            OS_TCB                    OSTickTaskTCB;
Xextern            OS_TCB                    OSTickTaskTCB;
NOS_EXT            CPU_TS                    OSTickTaskTimeMax;
Xextern            CPU_TS                    OSTickTaskTimeMax;
N
N
N#if OS_CFG_TMR_EN > 0u                                                  /* TIMERS ----------------------------------- */
X#if 0u > 0u                                                   
S#if OS_CFG_DBG_EN > 0u
SOS_EXT            OS_TMR                   *OSTmrDbgListPtr;
S#endif
SOS_EXT            OS_OBJ_QTY                OSTmrQty;                   /* Number of timers created                   */
SOS_EXT            OS_TCB                    OSTmrTaskTCB;               /* TCB of timer task                          */
SOS_EXT            CPU_TS                    OSTmrTaskTimeMax;
SOS_EXT            OS_TICK                   OSTmrTickCtr;               /* Current time for the timers                */
SOS_EXT            OS_CTR                    OSTmrUpdateCnt;             /* Counter for updating timers                */
SOS_EXT            OS_CTR                    OSTmrUpdateCtr;
N#endif
N
N                                                                        /* TCBs ------------------------------------- */
NOS_EXT            OS_TCB                   *OSTCBCurPtr;                /* Pointer to currently running TCB           */
Xextern            OS_TCB                   *OSTCBCurPtr;                 
NOS_EXT            OS_TCB                   *OSTCBHighRdyPtr;            /* Pointer to highest priority  TCB           */
Xextern            OS_TCB                   *OSTCBHighRdyPtr;             
N
N/*$PAGE*/
N/*
N************************************************************************************************************************
N************************************************************************************************************************
N*                                                   E X T E R N A L S
N************************************************************************************************************************
N************************************************************************************************************************
N*/
N
Nextern  CPU_STK     * const OSCfg_IdleTaskStkBasePtr;
Nextern  CPU_STK_SIZE  const OSCfg_IdleTaskStkLimit;
Nextern  CPU_STK_SIZE  const OSCfg_IdleTaskStkSize;
Nextern  CPU_INT32U    const OSCfg_IdleTaskStkSizeRAM;
N
Nextern  OS_INT_Q    * const OSCfg_IntQBasePtr;
Nextern  OS_OBJ_QTY    const OSCfg_IntQSize;
Nextern  CPU_INT32U    const OSCfg_IntQSizeRAM;
Nextern  CPU_STK     * const OSCfg_IntQTaskStkBasePtr;
Nextern  CPU_STK_SIZE  const OSCfg_IntQTaskStkLimit;
Nextern  CPU_STK_SIZE  const OSCfg_IntQTaskStkSize;
Nextern  CPU_INT32U    const OSCfg_IntQTaskStkSizeRAM;
N
Nextern  CPU_STK     * const OSCfg_ISRStkBasePtr;
Nextern  CPU_STK_SIZE  const OSCfg_ISRStkSize;
Nextern  CPU_INT32U    const OSCfg_ISRStkSizeRAM;
N
Nextern  OS_MSG_SIZE   const OSCfg_MsgPoolSize;
Nextern  CPU_INT32U    const OSCfg_MsgPoolSizeRAM;
Nextern  OS_MSG      * const OSCfg_MsgPoolBasePtr;
N
Nextern  OS_PRIO       const OSCfg_StatTaskPrio;
Nextern  OS_RATE_HZ    const OSCfg_StatTaskRate_Hz;
Nextern  CPU_STK     * const OSCfg_StatTaskStkBasePtr;
Nextern  CPU_STK_SIZE  const OSCfg_StatTaskStkLimit;
Nextern  CPU_STK_SIZE  const OSCfg_StatTaskStkSize;
Nextern  CPU_INT32U    const OSCfg_StatTaskStkSizeRAM;
N
Nextern  CPU_STK_SIZE  const OSCfg_StkSizeMin;
N
Nextern  OS_RATE_HZ    const OSCfg_TickRate_Hz;
Nextern  OS_PRIO       const OSCfg_TickTaskPrio;
Nextern  CPU_STK     * const OSCfg_TickTaskStkBasePtr;
Nextern  CPU_STK_SIZE  const OSCfg_TickTaskStkLimit;
Nextern  CPU_STK_SIZE  const OSCfg_TickTaskStkSize;
Nextern  CPU_INT32U    const OSCfg_TickTaskStkSizeRAM;
Nextern  OS_OBJ_QTY    const OSCfg_TickWheelSize;
Nextern  CPU_INT32U    const OSCfg_TickWheelSizeRAM;
N
Nextern  OS_PRIO       const OSCfg_TmrTaskPrio;
Nextern  OS_RATE_HZ    const OSCfg_TmrTaskRate_Hz;
Nextern  CPU_STK     * const OSCfg_TmrTaskStkBasePtr;
Nextern  CPU_STK_SIZE  const OSCfg_TmrTaskStkLimit;
Nextern  CPU_STK_SIZE  const OSCfg_TmrTaskStkSize;
Nextern  CPU_INT32U    const OSCfg_TmrTaskStkSizeRAM;
Nextern  OS_OBJ_QTY    const OSCfg_TmrWheelSize;
Nextern  CPU_INT32U    const OSCfg_TmrSizeRAM;
N
N
Nextern  CPU_STK        OSCfg_IdleTaskStk[];
N
N#if (OS_CFG_ISR_POST_DEFERRED_EN > 0u)
X#if (0u > 0u)
Sextern  CPU_STK        OSCfg_IntQTaskStk[];
Sextern  OS_INT_Q       OSCfg_IntQ[];
N#endif
N
Nextern  CPU_STK        OSCfg_ISRStk[];
N
N#if (OS_MSG_EN > 0u)
X#if ((((0u > 0u) || (0u > 0u)) ? 1u : 0u) > 0u)
Sextern  OS_MSG         OSCfg_MsgPool[];
N#endif
N
N#if (OS_CFG_STAT_TASK_EN > 0u)
X#if (0u > 0u)
Sextern  CPU_STK        OSCfg_StatTaskStk[];
N#endif
N
Nextern  CPU_STK        OSCfg_TickTaskStk[];
Nextern  OS_TICK_SPOKE  OSCfg_TickWheel[];
N
N#if (OS_CFG_TMR_EN > 0u)
X#if (0u > 0u)
Sextern  CPU_STK        OSCfg_TmrTaskStk[];
Sextern  OS_TMR_SPOKE   OSCfg_TmrWheel[];
N#endif
N
N/*
N************************************************************************************************************************
N************************************************************************************************************************
N*                                        F U N C T I O N   P R O T O T Y P E S
N************************************************************************************************************************
N************************************************************************************************************************
N*/
N
N/* ================================================================================================================== */
N/*                                                    EVENT FLAGS                                                     */
N/* ================================================================================================================== */
N
N#if OS_CFG_FLAG_EN > 0u
X#if 0u > 0u
S
Svoid          OSFlagCreate              (OS_FLAG_GRP           *p_grp,
S                                         CPU_CHAR              *p_name,
S                                         OS_FLAGS               flags,
S                                         OS_ERR                *p_err);
S
S#if OS_CFG_FLAG_DEL_EN > 0u
SOS_OBJ_QTY    OSFlagDel                 (OS_FLAG_GRP           *p_grp,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S#endif
S
SOS_FLAGS      OSFlagPend                (OS_FLAG_GRP           *p_grp,
S                                         OS_FLAGS               flags,
S                                         OS_TICK                timeout,
S                                         OS_OPT                 opt,
S                                         CPU_TS                *p_ts,
S                                         OS_ERR                *p_err);
S
S#if OS_CFG_FLAG_PEND_ABORT_EN > 0u
SOS_OBJ_QTY    OSFlagPendAbort           (OS_FLAG_GRP           *p_grp,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S#endif
S
SOS_FLAGS      OSFlagPendGetFlagsRdy     (OS_ERR                *p_err);
S
SOS_FLAGS      OSFlagPost                (OS_FLAG_GRP           *p_grp,
S                                         OS_FLAGS               flags,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S
S/* ------------------------------------------------ INTERNAL FUNCTIONS ---------------------------------------------- */
S
Svoid          OS_FlagClr                (OS_FLAG_GRP           *p_grp);
S
Svoid          OS_FlagBlock              (OS_PEND_DATA          *p_pend_data,
S                                         OS_FLAG_GRP           *p_grp,
S                                         OS_FLAGS               flags,
S                                         OS_OPT                 opt,
S                                         OS_TICK                timeout);
S
S#if OS_CFG_DBG_EN > 0u
Svoid          OS_FlagDbgListAdd         (OS_FLAG_GRP           *p_grp);
S
Svoid          OS_FlagDbgListRemove      (OS_FLAG_GRP           *p_grp);
S#endif
S
Svoid          OS_FlagInit               (OS_ERR                *p_err);
S
SOS_FLAGS      OS_FlagPost               (OS_FLAG_GRP           *p_grp,
S                                         OS_FLAGS               flags,
S                                         OS_OPT                 opt,
S                                         CPU_TS                 ts,
S                                         OS_ERR                *p_err);
S
Svoid          OS_FlagTaskRdy            (OS_TCB                *p_tcb,
S                                         OS_FLAGS               flags_rdy,
S                                         CPU_TS                 ts);
N#endif
N
N/*$PAGE*/
N/* ================================================================================================================== */
N/*                                          FIXED SIZE MEMORY BLOCK MANAGEMENT                                        */
N/* ================================================================================================================== */
N
N#if OS_CFG_MEM_EN > 0u
X#if 0u > 0u
S
Svoid          OSMemCreate               (OS_MEM                *p_mem,
S                                         CPU_CHAR              *p_name,
S                                         void                  *p_addr,
S                                         OS_MEM_QTY             n_blks,
S                                         OS_MEM_SIZE            blk_size,
S                                         OS_ERR                *p_err);
S
Svoid         *OSMemGet                  (OS_MEM                *p_mem,
S                                         OS_ERR                *p_err);
S
Svoid          OSMemPut                  (OS_MEM                *p_mem,
S                                         void                  *p_blk,
S                                         OS_ERR                *p_err);
S
S/* ------------------------------------------------ INTERNAL FUNCTIONS ---------------------------------------------- */
S
S#if OS_CFG_DBG_EN > 0u
Svoid          OS_MemDbgListAdd          (OS_MEM                *p_mem);
S#endif
S
Svoid          OS_MemInit                (OS_ERR                *p_err);
S
N#endif
N
N/*$PAGE*/
N/* ================================================================================================================== */
N/*                                             MUTUAL EXCLUSION SEMAPHORES                                            */
N/* ================================================================================================================== */
N
N#if OS_CFG_MUTEX_EN > 0u
X#if 0u > 0u
S
Svoid          OSMutexCreate             (OS_MUTEX              *p_mutex,
S                                         CPU_CHAR              *p_name,
S                                         OS_ERR                *p_err);
S
S#if OS_CFG_MUTEX_DEL_EN > 0u
SOS_OBJ_QTY    OSMutexDel                (OS_MUTEX              *p_mutex,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S#endif
S
Svoid          OSMutexPend               (OS_MUTEX              *p_mutex,
S                                         OS_TICK                timeout,
S                                         OS_OPT                 opt,
S                                         CPU_TS                *p_ts,
S                                         OS_ERR                *p_err);
S
S#if OS_CFG_MUTEX_PEND_ABORT_EN > 0u
SOS_OBJ_QTY    OSMutexPendAbort          (OS_MUTEX              *p_mutex,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S#endif
S
Svoid          OSMutexPost               (OS_MUTEX              *p_mutex,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S
S
S/* ------------------------------------------------ INTERNAL FUNCTIONS ---------------------------------------------- */
S
Svoid          OS_MutexClr               (OS_MUTEX              *p_mutex);
S
S#if OS_CFG_DBG_EN > 0u
Svoid          OS_MutexDbgListAdd        (OS_MUTEX              *p_mutex);
S
Svoid          OS_MutexDbgListRemove     (OS_MUTEX              *p_mutex);
S#endif
S
Svoid          OS_MutexInit              (OS_ERR                *p_err);
N#endif
N
N/*$PAGE*/
N/* ================================================================================================================== */
N/*                                                   MESSAGE QUEUES                                                   */
N/* ================================================================================================================== */
N
N#if OS_CFG_PEND_MULTI_EN > 0u
X#if 0u > 0u
S
SOS_OBJ_QTY    OSPendMulti               (OS_PEND_DATA          *p_pend_data_tbl,
S                                         OS_OBJ_QTY             tbl_size,
S                                         OS_TICK                timeout,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S
S/* ------------------------------------------------ INTERNAL FUNCTIONS ---------------------------------------------- */
S
SOS_OBJ_QTY    OS_PendMultiGetRdy        (OS_PEND_DATA          *p_pend_data_tbl,
S                                         OS_OBJ_QTY             tbl_size);
S
SCPU_BOOLEAN   OS_PendMultiValidate      (OS_PEND_DATA          *p_pend_data_tbl,
S                                         OS_OBJ_QTY             tbl_size);
S
Svoid          OS_PendMultiWait          (OS_PEND_DATA          *p_pend_data_tbl,
S                                         OS_OBJ_QTY             tbl_size,
S                                         OS_TICK                timeout);
N#endif
N
N/* ================================================================================================================== */
N/*                                                   MESSAGE QUEUES                                                   */
N/* ================================================================================================================== */
N
N#if OS_CFG_Q_EN > 0u
X#if 0u > 0u
S
Svoid          OSQCreate                 (OS_Q                  *p_q,
S                                         CPU_CHAR              *p_name,
S                                         OS_MSG_QTY             max_qty,
S                                         OS_ERR                *p_err);
S
S#if OS_CFG_Q_DEL_EN > 0u
SOS_OBJ_QTY    OSQDel                    (OS_Q                  *p_q,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S#endif
S
S#if OS_CFG_Q_FLUSH_EN > 0u
SOS_MSG_QTY    OSQFlush                  (OS_Q                  *p_q,
S                                         OS_ERR                *p_err);
S#endif
S
Svoid         *OSQPend                   (OS_Q                  *p_q,
S                                         OS_TICK                timeout,
S                                         OS_OPT                 opt,
S                                         OS_MSG_SIZE           *p_msg_size,
S                                         CPU_TS                *p_ts,
S                                         OS_ERR                *p_err);
S
S#if OS_CFG_Q_PEND_ABORT_EN > 0u
SOS_OBJ_QTY    OSQPendAbort              (OS_Q                  *p_q,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S#endif
S
Svoid          OSQPost                   (OS_Q                  *p_q,
S                                         void                  *p_void,
S                                         OS_MSG_SIZE            msg_size,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S
S/* ------------------------------------------------ INTERNAL FUNCTIONS ---------------------------------------------- */
S
Svoid          OS_QClr                   (OS_Q                  *p_q);
S
S#if OS_CFG_DBG_EN > 0u
Svoid          OS_QDbgListAdd            (OS_Q                  *p_q);
S
Svoid          OS_QDbgListRemove         (OS_Q                  *p_q);
S#endif
S
Svoid          OS_QInit                  (OS_ERR                *p_err);
S
Svoid          OS_QPost                  (OS_Q                  *p_q,
S                                         void                  *p_void,
S                                         OS_MSG_SIZE            msg_size,
S                                         OS_OPT                 opt,
S                                         CPU_TS                 ts,
S                                         OS_ERR                *p_err);
N#endif
N
N/*$PAGE*/
N/* ================================================================================================================== */
N/*                                                     SEMAPHORES                                                     */
N/* ================================================================================================================== */
N
N#if OS_CFG_SEM_EN > 0u
X#if 0u > 0u
S
Svoid          OSSemCreate               (OS_SEM                *p_sem,
S                                         CPU_CHAR              *p_name,
S                                         OS_SEM_CTR             cnt,
S                                         OS_ERR                *p_err);
S
SOS_OBJ_QTY    OSSemDel                  (OS_SEM                *p_sem,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S
SOS_SEM_CTR    OSSemPend                 (OS_SEM                *p_sem,
S                                         OS_TICK                timeout,
S                                         OS_OPT                 opt,
S                                         CPU_TS                *p_ts,
S                                         OS_ERR                *p_err);
S
S#if OS_CFG_SEM_PEND_ABORT_EN > 0u
SOS_OBJ_QTY    OSSemPendAbort            (OS_SEM                *p_sem,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S#endif
S
SOS_SEM_CTR    OSSemPost                 (OS_SEM                *p_sem,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S
S#if OS_CFG_SEM_SET_EN > 0u
Svoid          OSSemSet                  (OS_SEM                *p_sem,
S                                         OS_SEM_CTR             cnt,
S                                         OS_ERR                *p_err);
S#endif
S
S/* ------------------------------------------------ INTERNAL FUNCTIONS ---------------------------------------------- */
S
Svoid          OS_SemClr                 (OS_SEM                *p_sem);
S
S#if OS_CFG_DBG_EN > 0u
Svoid          OS_SemDbgListAdd          (OS_SEM                *p_sem);
S
Svoid          OS_SemDbgListRemove       (OS_SEM                *p_sem);
S#endif
S
Svoid          OS_SemInit                (OS_ERR                *p_err);
S
SOS_SEM_CTR    OS_SemPost                (OS_SEM                *p_sem,
S                                         OS_OPT                 opt,
S                                         CPU_TS                 ts,
S                                         OS_ERR                *p_err);
N#endif
N
N/*$PAGE*/
N/* ================================================================================================================== */
N/*                                                 TASK MANAGEMENT                                                    */
N/* ================================================================================================================== */
N
N#if OS_CFG_TASK_CHANGE_PRIO_EN > 0u
X#if 0u > 0u
Svoid          OSTaskChangePrio          (OS_TCB                *p_tcb,
S                                         OS_PRIO                prio_new,
S                                         OS_ERR                *p_err);
N#endif
N
Nvoid          OSTaskCreate              (OS_TCB                *p_tcb,
N                                         CPU_CHAR              *p_name,
N                                         OS_TASK_PTR            p_task,
N                                         void                  *p_arg,
N                                         OS_PRIO                prio,
N                                         CPU_STK               *p_stk_base,
N                                         CPU_STK_SIZE           stk_limit,
N                                         CPU_STK_SIZE           stk_size,
N                                         OS_MSG_QTY             q_size,
N                                         OS_TICK                time_quanta,
N                                         void                  *p_ext,
N                                         OS_OPT                 opt,
N                                         OS_ERR                *p_err);
N
N#if OS_CFG_TASK_DEL_EN > 0u
X#if 0u > 0u
Svoid          OSTaskDel                 (OS_TCB                *p_tcb,
S                                         OS_ERR                *p_err);
N#endif
N
N#if OS_CFG_TASK_Q_EN > 0u
X#if 0u > 0u
SOS_MSG_QTY    OSTaskQFlush              (OS_TCB                *p_tcb,
S                                         OS_ERR                *p_err);
S
Svoid         *OSTaskQPend               (OS_TICK                timeout,
S                                         OS_OPT                 opt,
S                                         OS_MSG_SIZE           *p_msg_size,
S                                         CPU_TS                *p_ts,
S                                         OS_ERR                *p_err);
S
SCPU_BOOLEAN   OSTaskQPendAbort          (OS_TCB                *p_tcb,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S
Svoid          OSTaskQPost               (OS_TCB                *p_tcb,
S                                         void                  *p_void,
S                                         OS_MSG_SIZE            msg_size,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
S
N#endif
N
N#if OS_CFG_TASK_REG_TBL_SIZE > 0u
X#if 1u > 0u
NOS_REG        OSTaskRegGet              (OS_TCB                *p_tcb,
N                                         OS_REG_ID              id,
N                                         OS_ERR                *p_err);
N
NOS_REG_ID     OSTaskRegGetID            (OS_ERR                *p_err);
N
Nvoid          OSTaskRegSet              (OS_TCB                *p_tcb,
N                                         OS_REG_ID              id,
N                                         OS_REG                 value,
N                                         OS_ERR                *p_err);
N#endif
N
N#if OS_CFG_TASK_SUSPEND_EN > 0u
X#if 0u > 0u
Svoid          OSTaskResume              (OS_TCB                *p_tcb,
S                                         OS_ERR                *p_err);
S
Svoid          OSTaskSuspend             (OS_TCB                *p_tcb,
S                                         OS_ERR                *p_err);
N#endif
N
NOS_SEM_CTR    OSTaskSemPend             (OS_TICK                timeout,
N                                         OS_OPT                 opt,
N                                         CPU_TS                *p_ts,
N                                         OS_ERR                *p_err);
N
N#if (OS_CFG_TASK_SEM_PEND_ABORT_EN > 0u)
X#if (0u > 0u)
SCPU_BOOLEAN   OSTaskSemPendAbort        (OS_TCB                *p_tcb,
S                                         OS_OPT                 opt,
S                                         OS_ERR                *p_err);
N#endif
N
NOS_SEM_CTR    OSTaskSemPost             (OS_TCB                *p_tcb,
N                                         OS_OPT                 opt,
N                                         OS_ERR                *p_err);
N
NOS_SEM_CTR    OSTaskSemSet              (OS_TCB                *p_tcb,
N                                         OS_SEM_CTR             cnt,
N                                         OS_ERR                *p_err);
N
N#if OS_CFG_STAT_TASK_STK_CHK_EN > 0u
X#if 1u > 0u
Nvoid          OSTaskStkChk              (OS_TCB                *p_tcb,
N                                         CPU_STK_SIZE          *p_free,
N                                         CPU_STK_SIZE          *p_used,
N                                         OS_ERR                *p_err);
N#endif
N
N#if OS_CFG_SCHED_ROUND_ROBIN_EN > 0u
X#if 0u > 0u
Svoid          OSTaskTimeQuantaSet       (OS_TCB                *p_tcb,
S                                         OS_TICK                time_quanta,
S                                         OS_ERR                *p_err);
N#endif
N
N/* ------------------------------------------------ INTERNAL FUNCTIONS ---------------------------------------------- */
N
Nvoid          OS_TaskBlock              (OS_TCB                *p_tcb,
N                                         OS_TICK                timeout);
N
N#if OS_CFG_DBG_EN > 0u
X#if 0u > 0u
Svoid          OS_TaskDbgListAdd         (OS_TCB                *p_tcb);
S
Svoid          OS_TaskDbgListRemove      (OS_TCB                *p_tcb);
N#endif
N
Nvoid          OS_TaskInit               (OS_ERR                *p_err);
N
Nvoid          OS_TaskInitTCB            (OS_TCB                *p_tcb);
N
Nvoid          OS_TaskQPost              (OS_TCB                *p_tcb,
N                                         void                  *p_void,
N                                         OS_MSG_SIZE            msg_size,
N                                         OS_OPT                 opt,
N                                         CPU_TS                 ts,
N                                         OS_ERR                *p_err);
N
Nvoid          OS_TaskRdy                (OS_TCB                *p_tcb);
N
N#if OS_CFG_TASK_SUSPEND_EN > 0u
X#if 0u > 0u
Svoid          OS_TaskResume             (OS_TCB                *p_tcb,
S                                         OS_ERR                *p_err);
N#endif
N
Nvoid          OS_TaskReturn             (void);
N
NOS_SEM_CTR    OS_TaskSemPost            (OS_TCB                *p_tcb,
N                                         OS_OPT                 opt,
N                                         CPU_TS                 ts,
N                                         OS_ERR                *p_err);
N
N#if OS_CFG_TASK_SUSPEND_EN > 0u
X#if 0u > 0u
Svoid          OS_TaskSuspend            (OS_TCB                *p_tcb,
S                                         OS_ERR                *p_err);
N#endif
N
N/*$PAGE*/
N/* ================================================================================================================== */
N/*                                          TASK LOCAL STORAGE (TLS) SUPPORT                                          */
N/* ================================================================================================================== */
N
N#if defined(OS_CFG_TLS_TBL_SIZE) && (OS_CFG_TLS_TBL_SIZE > 0u)
X#if 0L && (OS_CFG_TLS_TBL_SIZE > 0u)
SOS_TLS_ID  OS_TLS_GetID       (OS_ERR              *p_err);
S
SOS_TLS     OS_TLS_GetValue    (OS_TCB              *p_tcb,
S                               OS_TLS_ID            id,
S                               OS_ERR              *p_err);
S
Svoid       OS_TLS_Init        (OS_ERR              *p_err);
S
Svoid       OS_TLS_SetValue    (OS_TCB              *p_tcb,
S                               OS_TLS_ID            id,
S                               OS_TLS               value,
S                               OS_ERR              *p_err);
S
Svoid       OS_TLS_SetDestruct (OS_TLS_ID            id,
S                               OS_TLS_DESTRUCT_PTR  p_destruct,
S                               OS_ERR              *p_err);
S
Svoid       OS_TLS_TaskCreate  (OS_TCB              *p_tcb);
S
Svoid       OS_TLS_TaskDel     (OS_TCB              *p_tcb);
S
Svoid       OS_TLS_TaskSw      (void);
N#endif
N
N/*$PAGE*/
N/* ================================================================================================================== */
N/*                                                 TIME MANAGEMENT                                                    */
N/* ================================================================================================================== */
N
Nvoid          OSTimeDly                 (OS_TICK                dly,
N                                         OS_OPT                 opt,
N                                         OS_ERR                *p_err);
N
N#if OS_CFG_TIME_DLY_HMSM_EN > 0u
X#if 1u > 0u
Nvoid          OSTimeDlyHMSM             (CPU_INT16U             hours,
N                                         CPU_INT16U             minutes,
N                                         CPU_INT16U             seconds,
N                                         CPU_INT32U             milli,
N                                         OS_OPT                 opt,
N                                         OS_ERR                *p_err);
N#endif
N
N#if OS_CFG_TIME_DLY_RESUME_EN > 0u
X#if 1u > 0u
Nvoid          OSTimeDlyResume           (OS_TCB                *p_tcb,
N                                         OS_ERR                *p_err);
N#endif
N
NOS_TICK       OSTimeGet                 (OS_ERR                *p_err);
N
Nvoid          OSTimeSet                 (OS_TICK                ticks,
N                                         OS_ERR                *p_err);
N
Nvoid          OSTimeTick                (void);
N
N/*$PAGE*/
N/* ================================================================================================================== */
N/*                                                 TIMER MANAGEMENT                                                   */
N/* ================================================================================================================== */
N
N#if OS_CFG_TMR_EN > 0u
X#if 0u > 0u
Svoid          OSTmrCreate               (OS_TMR                *p_tmr,
S                                         CPU_CHAR              *p_name,
S                                         OS_TICK                dly,
S                                         OS_TICK                period,
S                                         OS_OPT                 opt,
S                                         OS_TMR_CALLBACK_PTR    p_callback,
S                                         void                  *p_callback_arg,
S                                         OS_ERR                *p_err);
S
SCPU_BOOLEAN   OSTmrDel                  (OS_TMR                *p_tmr,
S                                         OS_ERR                *p_err);
S
SOS_TICK       OSTmrRemainGet            (OS_TMR                *p_tmr,
S                                         OS_ERR                *p_err);
S
SCPU_BOOLEAN   OSTmrStart                (OS_TMR                *p_tmr,
S                                         OS_ERR                *p_err);
S
SOS_STATE      OSTmrStateGet             (OS_TMR                *p_tmr,
S                                         OS_ERR                *p_err);
S
SCPU_BOOLEAN   OSTmrStop                 (OS_TMR                *p_tmr,
S                                         OS_OPT                 opt,
S                                         void                  *p_callback_arg,
S                                         OS_ERR                *p_err);
S
S/* ------------------------------------------------ INTERNAL FUNCTIONS ---------------------------------------------- */
S
Svoid          OS_TmrClr                 (OS_TMR                *p_tmr);
S
S#if OS_CFG_DBG_EN > 0u
Svoid          OS_TmrDbgListAdd          (OS_TMR                *p_tmr);
S
Svoid          OS_TmrDbgListRemove       (OS_TMR                *p_tmr);
S#endif
S
Svoid          OS_TmrInit                (OS_ERR                *p_err);
S
Svoid          OS_TmrLink                (OS_TMR                *p_tmr,
S                                         OS_OPT                 opt);
S
Svoid          OS_TmrResetPeak           (void);
S
Svoid          OS_TmrUnlink              (OS_TMR                *p_tmr);
S
Svoid          OS_TmrTask                (void                  *p_arg);
S
N#endif
N
N/*$PAGE*/
N/* ================================================================================================================== */
N/*                                                    MISCELLANEOUS                                                   */
N/* ================================================================================================================== */
N
Nvoid          OSInit                    (OS_ERR                *p_err);
N
Nvoid          OSIntEnter                (void);
Nvoid          OSIntExit                 (void);
N
N#ifdef OS_SAFETY_CRITICAL_IEC61508
Svoid          OSSafetyCriticalStart     (void);
N#endif
N
N#if OS_CFG_SCHED_ROUND_ROBIN_EN > 0u
X#if 0u > 0u
Svoid          OSSchedRoundRobinCfg      (CPU_BOOLEAN            en,
S                                         OS_TICK                dflt_time_quanta,
S                                         OS_ERR                *p_err);
S
Svoid          OSSchedRoundRobinYield    (OS_ERR                *p_err);
S
N#endif
N
Nvoid          OSSched                   (void);
N
Nvoid          OSSchedLock               (OS_ERR                *p_err);
Nvoid          OSSchedUnlock             (OS_ERR                *p_err);
N
Nvoid          OSStart                   (OS_ERR                *p_err);
N
N#if OS_CFG_STAT_TASK_EN > 0u
X#if 0u > 0u
Svoid          OSStatReset               (OS_ERR                *p_err);
S
Svoid          OSStatTaskCPUUsageInit    (OS_ERR                *p_err);
N#endif
N
NCPU_INT16U    OSVersion                 (OS_ERR                *p_err);
N
N/* ------------------------------------------------ INTERNAL FUNCTIONS ---------------------------------------------- */
N
Nvoid          OS_IdleTask               (void                  *p_arg);
N
Nvoid          OS_IdleTaskInit           (OS_ERR                *p_err);
N
N#if OS_CFG_STAT_TASK_EN > 0u
X#if 0u > 0u
Svoid          OS_StatTask               (void                  *p_arg);
N#endif
N
Nvoid          OS_StatTaskInit           (OS_ERR                *p_err);
N
Nvoid          OS_TickTask               (void                  *p_arg);
Nvoid          OS_TickTaskInit           (OS_ERR                *p_err);
N
N/*$PAGE*/
N/*
N************************************************************************************************************************
N************************************************************************************************************************
N*                                    T A R G E T   S P E C I F I C   F U N C T I O N S
N************************************************************************************************************************
N************************************************************************************************************************
N*/
N
Nvoid          OSInitHook                (void);
N
Nvoid          OSTaskCreateHook          (OS_TCB                *p_tcb);
Nvoid          OSTaskDelHook             (OS_TCB                *p_tcb);
N
Nvoid          OSIdleTaskHook            (void);
N
Nvoid          OSTaskReturnHook          (OS_TCB                *p_tcb);
N
Nvoid          OSStatTaskHook            (void);
N
NCPU_STK      *OSTaskStkInit             (OS_TASK_PTR            p_task,
N                                         void                  *p_arg,
N                                         CPU_STK               *p_stk_base,
N                                         CPU_STK               *p_stk_limit,
N                                         CPU_STK_SIZE           stk_size,
N                                         OS_OPT                 opt);
N
Nvoid          OSTaskSwHook              (void);
N
Nvoid          OSTimeTickHook            (void);
N
N/*$PAGE*/
N/*
N************************************************************************************************************************
N************************************************************************************************************************
N*                   u C / O S - I I I   I N T E R N A L   F U N C T I O N   P R O T O T Y P E S
N************************************************************************************************************************
N************************************************************************************************************************
N*/
N
Nvoid          OSCfg_Init                (void);
N
N#if OS_CFG_DBG_EN > 0u
X#if 0u > 0u
Svoid          OS_Dbg_Init               (void);
N#endif
N
N
N#if OS_CFG_ISR_POST_DEFERRED_EN > 0u
X#if 0u > 0u
Svoid          OS_IntQTaskInit           (OS_ERR                *p_err);
S
Svoid          OS_IntQPost               (OS_OBJ_TYPE            type,
S                                         void                  *p_obj,
S                                         void                  *p_void,
S                                         OS_MSG_SIZE            msg_size,
S                                         OS_FLAGS               flags,
S                                         OS_OPT                 opt,
S                                         CPU_TS                 ts,
S                                         OS_ERR                *p_err);
S
Svoid          OS_IntQRePost             (void);
S
Svoid          OS_IntQTask               (void                  *p_arg);
N#endif
N
N/* ----------------------------------------------- MESSAGE MANAGEMENT ----------------------------------------------- */
N
Nvoid          OS_MsgPoolInit            (OS_ERR                *p_err);
N
NOS_MSG_QTY    OS_MsgQFreeAll            (OS_MSG_Q              *p_msg_q);
N
Nvoid         *OS_MsgQGet                (OS_MSG_Q              *p_msg_q,
N                                         OS_MSG_SIZE           *p_msg_size,
N                                         CPU_TS                *p_ts,
N                                         OS_ERR                *p_err);
N
Nvoid          OS_MsgQInit               (OS_MSG_Q              *p_msg_q,
N                                         OS_MSG_QTY             size);
N
Nvoid          OS_MsgQPut                (OS_MSG_Q              *p_msg_q,
N                                         void                  *p_void,
N                                         OS_MSG_SIZE            msg_size,
N                                         OS_OPT                 opt,
N                                         CPU_TS                 ts,
N                                         OS_ERR                *p_err);
N
N/* ---------------------------------------------- PEND/POST MANAGEMENT ---------------------------------------------- */
N
Nvoid          OS_Pend                   (OS_PEND_DATA          *p_pend_data,
N                                         OS_PEND_OBJ           *p_obj,
N                                         OS_STATE               pending_on,
N                                         OS_TICK                timeout);
N
Nvoid          OS_PendAbort              (OS_PEND_OBJ           *p_obj,
N                                         OS_TCB                *p_tcb,
N                                         CPU_TS                 ts);
N
Nvoid          OS_PendAbort1             (OS_PEND_OBJ           *p_obj,
N                                         OS_TCB                *p_tcb,
N                                         CPU_TS                 ts);
N
Nvoid          OS_PendObjDel             (OS_PEND_OBJ           *p_obj,
N                                         OS_TCB                *p_tcb,
N                                         CPU_TS                 ts);
N
Nvoid          OS_PendObjDel1            (OS_PEND_OBJ           *p_obj,
N                                         OS_TCB                *p_tcb,
N                                         CPU_TS                 ts);
N
Nvoid          OS_Post                   (OS_PEND_OBJ           *p_obj,
N                                         OS_TCB                *p_tcb,
N                                         void                  *p_void,
N                                         OS_MSG_SIZE            msg_size,
N                                         CPU_TS                 ts);
N
Nvoid          OS_Post1                  (OS_PEND_OBJ           *p_obj,
N                                         OS_TCB                *p_tcb,
N                                         void                  *p_void,
N                                         OS_MSG_SIZE            msg_size,
N                                         CPU_TS                 ts);
N
N/* ----------------------------------------------- PRIORITY MANAGEMENT ---------------------------------------------- */
N
Nvoid          OS_PrioInit               (void);
N
Nvoid          OS_PrioInsert             (OS_PRIO                prio);
N
Nvoid          OS_PrioRemove             (OS_PRIO                prio);
N
NOS_PRIO       OS_PrioGetHighest         (void);
N
N/* --------------------------------------------------- SCHEDULING --------------------------------------------------- */
N
N#if OS_CFG_ISR_POST_DEFERRED_EN > 0u
X#if 0u > 0u
Svoid          OS_Sched0                 (void);
N#endif
N
N#if OS_CFG_SCHED_LOCK_TIME_MEAS_EN > 0u
X#if 0u > 0u
Svoid          OS_SchedLockTimeMeasStart (void);
Svoid          OS_SchedLockTimeMeasStop  (void);
N#endif
N
N#if OS_CFG_SCHED_ROUND_ROBIN_EN > 0u
X#if 0u > 0u
Svoid          OS_SchedRoundRobin        (OS_RDY_LIST           *p_rdy_list);
N#endif
N
N/* --------------------------------------------- READY LIST MANAGEMENT ---------------------------------------------- */
N
Nvoid          OS_RdyListInit            (void);
N
Nvoid          OS_RdyListInsert          (OS_TCB                *p_tcb);
N
Nvoid          OS_RdyListInsertHead      (OS_TCB                *p_tcb);
N
Nvoid          OS_RdyListInsertTail      (OS_TCB                *p_tcb);
N
Nvoid          OS_RdyListMoveHeadToTail  (OS_RDY_LIST           *p_rdy_list);
N
Nvoid          OS_RdyListRemove          (OS_TCB                *p_tcb);
N
N/* ---------------------------------------------- PEND LIST MANAGEMENT ---------------------------------------------- */
N
Nvoid          OS_PendDataInit           (OS_TCB                *p_tcb,
N                                         OS_PEND_DATA          *p_pend_data_tbl,
N                                         OS_OBJ_QTY             tbl_size);
N
N#if OS_CFG_DBG_EN > 0u
X#if 0u > 0u
Svoid          OS_PendDbgNameAdd         (OS_PEND_OBJ           *p_obj,
S                                         OS_TCB                *p_tcb);
S
Svoid          OS_PendDbgNameRemove      (OS_PEND_OBJ           *p_obj,
S                                         OS_TCB                *p_tcb);
N#endif
N
NOS_PEND_LIST *OS_PendListGetPtr         (OS_PEND_OBJ           *p_obj);
N
Nvoid          OS_PendListInit           (OS_PEND_LIST          *p_pend_list);
N
Nvoid          OS_PendListInsertHead     (OS_PEND_LIST          *p_pend_list,
N                                         OS_PEND_DATA          *p_pend_data);
N
Nvoid          OS_PendListInsertPrio     (OS_PEND_LIST          *p_pend_list,
N                                         OS_PEND_DATA          *p_pend_data);
N
Nvoid          OS_PendListChangePrio     (OS_TCB                *p_tcb,
N                                         OS_PRIO                prio_new);
N
Nvoid          OS_PendListRemove         (OS_TCB                *p_tcb);
N
Nvoid          OS_PendListRemove1        (OS_PEND_LIST          *p_pend_list,
N                                         OS_PEND_DATA          *p_pend_data);
N
N/* ---------------------------------------------- TICK LIST MANAGEMENT ---------------------------------------------- */
N
Nvoid          OS_TickListInit           (void);
N
Nvoid          OS_TickListInsert         (OS_TCB                *p_tcb,
N                                         OS_TICK                time,
N                                         OS_OPT                 opt,
N                                         OS_ERR                *p_err);
N
Nvoid          OS_TickListRemove         (OS_TCB                *p_tcb);
N
Nvoid          OS_TickListResetPeak      (void);
N
Nvoid          OS_TickListUpdate         (void);
N
N/*$PAGE*/
N/*
N************************************************************************************************************************
N*                                          LOOK FOR MISSING #define CONSTANTS
N*
N* This section is used to generate ERROR messages at compile time if certain #define constants are
N* MISSING in OS_CFG.H.  This allows you to quickly determine the source of the error.
N*
N* You SHOULD NOT change this section UNLESS you would like to add more comments as to the source of the
N* compile time error.
N************************************************************************************************************************
N*/
N
N/*
N************************************************************************************************************************
N*                                                     MISCELLANEOUS
N************************************************************************************************************************
N*/
N
N#ifndef OS_CFG_APP_HOOKS_EN
S#error  "OS_CFG.H, Missing OS_CFG_APP_HOOKS_EN: Enable (1) or Disable (0) application specific hook functions"
N#endif
N
N
N#ifndef OS_CFG_ARG_CHK_EN
S#error  "OS_CFG.H, Missing OS_CFG_ARG_CHK_EN: Enable (1) or Disable (0) argument checking"
N#endif
N
N
N#ifndef OS_CFG_DBG_EN
S#error  "OS_CFG.H, Missing OS_CFG_DBG_EN: Allows you to include variables for debugging or not"
N#endif
N
N
N#ifndef OS_CFG_CALLED_FROM_ISR_CHK_EN
S#error  "OS_CFG.H, Missing OS_CFG_CALLED_FROM_ISR_CHK_EN: Enable (1) or Disable (0) checking whether in an ISR in kernel services"
N#endif
N
N
N#ifndef OS_CFG_OBJ_TYPE_CHK_EN
S#error  "OS_CFG.H, Missing OS_CFG_OBJ_TYPE_CHK_EN: Enable (1) or Disable (0) checking for proper object types in kernel services"
N#endif
N
N
N#ifndef OS_CFG_PEND_MULTI_EN
S#error  "OS_CFG.H, Missing OS_CFG_PEND_MULTI_EN: Enable (1) or Disable (0) multi-pend feature"
N#endif
N
N
N#if     OS_CFG_PRIO_MAX < 8u
X#if     16u < 8u
S#error  "OS_CFG.H,         OS_CFG_PRIO_MAX must be >= 8"
N#endif
N
N
N#ifndef OS_CFG_SCHED_LOCK_TIME_MEAS_EN
S#error  "OS_CFG.H, Missing OS_CFG_SCHED_LOCK_TIME_MEAS_EN: Include code to measure scheduler lock time"
N#else
N    #if    (OS_CFG_SCHED_LOCK_TIME_MEAS_EN > 0u) && \
N           (OS_CFG_TS_EN                   < 1u)
X    #if    (0u > 0u) &&            (0u                   < 1u)
S    #error  "OS_CFG.H,         OS_CFG_TS_EN must be Enabled (1) to measure scheduler lock time"
N    #endif
N#endif
N
N
N#ifndef OS_CFG_SCHED_ROUND_ROBIN_EN
S#error  "OS_CFG.H, Missing OS_CFG_SCHED_ROUND_ROBIN_EN: Include code for Round Robin Scheduling"
N#endif
N
N
N#ifndef OS_CFG_STK_SIZE_MIN
S#error  "OS_CFG.H, Missing OS_CFG_STK_SIZE_MIN: Determines the minimum size for a task stack"
N#endif
N
N#ifndef OS_CFG_TS_EN
S#error  "OS_CFG.H, Missing OS_CFG_TS_EN: Determines whether time stamping is enabled"
N#else
N    #if    (OS_CFG_TS_EN  >  0u) && \
N           (CPU_CFG_TS_EN == DEF_DISABLED)
X    #if    (0u  >  0u) &&            (1u == 0u)
S    #error  "CPU_CFG.H,        CPU_CFG_TS_32_EN must be Enabled (1) to use time stamp feature"
N    #endif
N#endif
N
N/*
N************************************************************************************************************************
N*                                                     EVENT FLAGS
N************************************************************************************************************************
N*/
N
N#ifndef OS_CFG_FLAG_EN
S#error  "OS_CFG.H, Missing OS_CFG_FLAG_EN: Enable (1) or Disable (0) code generation for Event Flags"
N#else
N    #ifndef OS_CFG_FLAG_DEL_EN
S    #error  "OS_CFG.H, Missing OS_CFG_FLAG_DEL_EN: Include code for OSFlagDel()"
N    #endif
N
N    #ifndef OS_CFG_FLAG_MODE_CLR_EN
S    #error  "OS_CFG.H, Missing OS_CFG_FLAG_MODE_CLR_EN: Include code for Wait on Clear EVENT FLAGS"
N    #endif
N
N    #ifndef OS_CFG_FLAG_PEND_ABORT_EN
S    #error  "OS_CFG.H, Missing OS_CFG_FLAG_PEND_ABORT_EN: Include code for aborting pends from another task"
N    #endif
N#endif
N
N/*
N************************************************************************************************************************
N*                                                  MEMORY MANAGEMENT
N************************************************************************************************************************
N*/
N
N#ifndef OS_CFG_MEM_EN
S#error  "OS_CFG.H, Missing OS_CFG_MEM_EN: Enable (1) or Disable (0) code generation for MEMORY MANAGER"
N#endif
N
N/*
N************************************************************************************************************************
N*                                              MUTUAL EXCLUSION SEMAPHORES
N************************************************************************************************************************
N*/
N
N#ifndef OS_CFG_MUTEX_EN
S#error  "OS_CFG.H, Missing OS_CFG_MUTEX_EN: Enable (1) or Disable (0) code generation for MUTEX"
N#else
N    #ifndef OS_CFG_MUTEX_DEL_EN
S    #error  "OS_CFG.H, Missing OS_CFG_MUTEX_DEL_EN: Include code for OSMutexDel()"
N    #endif
N
N    #ifndef OS_CFG_MUTEX_PEND_ABORT_EN
S    #error  "OS_CFG.H, Missing OS_CFG_MUTEX_PEND_ABORT_EN: Include code for OSMutexPendAbort()"
N    #endif
N#endif
N
N/*
N************************************************************************************************************************
N*                                                    MESSAGE QUEUES
N************************************************************************************************************************
N*/
N
N#ifndef OS_CFG_Q_EN
S#error  "OS_CFG.H, Missing OS_CFG_Q_EN: Enable (1) or Disable (0) code generation for QUEUES"
N#else
N    #ifndef OS_CFG_Q_DEL_EN
S    #error  "OS_CFG.H, Missing OS_CFG_Q_DEL_EN: Include code for OSQDel()"
N    #endif
N
N    #ifndef OS_CFG_Q_FLUSH_EN
S    #error  "OS_CFG.H, Missing OS_CFG_Q_FLUSH_EN: Include code for OSQFlush()"
N    #endif
N
N    #ifndef OS_CFG_Q_PEND_ABORT_EN
S    #error  "OS_CFG.H, Missing OS_CFG_Q_PEND_ABORT_EN: Include code for OSQPendAbort()"
N    #endif
N#endif
N
N/*
N************************************************************************************************************************
N*                                                      SEMAPHORES
N************************************************************************************************************************
N*/
N
N#ifndef OS_CFG_SEM_EN
S#error  "OS_CFG.H, Missing OS_CFG_SEM_EN: Enable (1) or Disable (0) code generation for SEMAPHORES"
N#else
N    #ifndef OS_CFG_SEM_DEL_EN
S    #error  "OS_CFG.H, Missing OS_CFG_SEM_DEL_EN: Include code for OSSemDel()"
N    #endif
N
N    #ifndef OS_CFG_SEM_PEND_ABORT_EN
S    #error  "OS_CFG.H, Missing OS_CFG_SEM_PEND_ABORT_EN: Include code for OSSemPendAbort()"
N    #endif
N
N    #ifndef OS_CFG_SEM_SET_EN
S    #error  "OS_CFG.H, Missing OS_CFG_SEM_SET_EN: Include code for OSSemSet()"
N    #endif
N#endif
N
N/*
N************************************************************************************************************************
N*                                                   TASK MANAGEMENT
N************************************************************************************************************************
N*/
N
N#ifndef OS_CFG_STAT_TASK_EN
S#error  "OS_CFG.H, Missing OS_CFG_STAT_TASK_EN: Enable (1) or Disable(0) the statistics task"
N#endif
N
N#ifndef OS_CFG_STAT_TASK_STK_CHK_EN
S#error  "OS_CFG.H, Missing OS_CFG_STAT_TASK_STK_CHK_EN: Check task stacks from statistics task"
N#endif
N
N#ifndef OS_CFG_TASK_CHANGE_PRIO_EN
S#error  "OS_CFG.H, Missing OS_CFG_TASK_CHANGE_PRIO_EN: Include code for OSTaskChangePrio()"
N#endif
N
N#ifndef OS_CFG_TASK_DEL_EN
S#error  "OS_CFG.H, Missing OS_CFG_TASK_DEL_EN: Include code for OSTaskDel()"
N#endif
N
N#ifndef OS_CFG_TASK_Q_EN
S#error  "OS_CFG.H, Missing OS_CFG_TASK_Q_EN: Include code for OSTaskQxxx()"
N#endif
N
N#ifndef OS_CFG_TASK_Q_PEND_ABORT_EN
S#error  "OS_CFG.H, Missing OS_CFG_TASK_Q_PEND_ABORT_EN: Include code for OSTaskQPendAbort()"
N#endif
N
N#ifndef OS_CFG_TASK_PROFILE_EN
S#error  "OS_CFG.H, Missing OS_CFG_TASK_PROFILE_EN: Include code for task profiling"
N#endif
N
N#ifndef OS_CFG_TASK_REG_TBL_SIZE
S#error  "OS_CFG.H, Missing OS_CFG_TASK_REG_TBL_SIZE: Include support for task specific registers"
N#endif
N
N#ifndef OS_CFG_TASK_SEM_PEND_ABORT_EN
S#error  "OS_CFG.H, Missing OS_CFG_TASK_SEM_PEND_ABORT_EN: Include code for OSTaskSemPendAbort()"
N#endif
N
N#ifndef OS_CFG_TASK_SUSPEND_EN
S#error  "OS_CFG.H, Missing OS_CFG_TASK_SUSPEND_EN: Include code for OSTaskSuspend() and OSTaskResume()"
N#endif
N
N/*
N************************************************************************************************************************
N*                                                  TIME MANAGEMENT
N************************************************************************************************************************
N*/
N
N#ifndef OS_CFG_TIME_DLY_HMSM_EN
S#error  "OS_CFG.H, Missing OS_CFG_TIME_DLY_HMSM_EN: Include code for OSTimeDlyHMSM()"
N#endif
N
N#ifndef OS_CFG_TIME_DLY_RESUME_EN
S#error  "OS_CFG.H, Missing OS_CFG_TIME_DLY_RESUME_EN: Include code for OSTimeDlyResume()"
N#endif
N
N/*
N************************************************************************************************************************
N*                                                  TIMER MANAGEMENT
N************************************************************************************************************************
N*/
N
N#ifndef OS_CFG_TMR_EN
S#error  "OS_CFG.H, Missing OS_CFG_TMR_EN: When (1) enables code generation for Timer Management"
N#else
N    #ifndef OS_CFG_TMR_DEL_EN
S    #error  "OS_CFG.H, Missing OS_CFG_TMR_DEL_EN: Enables (1) or Disables (0) code for OSTmrDel()"
N    #endif
N#endif
N
N/*
N************************************************************************************************************************
N*                                             LIBRARY CONFIGURATION ERRORS
N************************************************************************************************************************
N*/
N
N                                                                /* See 'os.h  Note #1a'.                              */
N#if LIB_VERSION < 126u
X#if 13700u < 126u
S#error  "lib_def.h, LIB_VERSION SHOULD be >= V1.26"
N#endif
N
N
N                                                                /* See 'os.h  Note #1b'.                              */
N#if CPU_CORE_VERSION < 125u
X#if 12901u < 125u
S#error  "cpu_core.h, CPU_CORE_VERSION SHOULD be >= V1.25"
N#endif
N
N
N/*
N************************************************************************************************************************
N*                                                 uC/OS-III MODULE END
N************************************************************************************************************************
N*/
N
N#ifdef __cplusplus
S}
N#endif
N#endif
L 40 "..\..\User\bsp\bsp.h" 2
N
N	#define  ENABLE_INT()      OS_CRITICAL_EXIT()     /* 使能全局中断 */
N	#define  DISABLE_INT()     OS_CRITICAL_ENTER()    /* 禁止全局中断 */
N#else
S	/* 开关全局中断的宏 */
S	#define ENABLE_INT()	__set_PRIMASK(0)	/* 使能全局中断 */
S	#define DISABLE_INT()	__set_PRIMASK(1)	/* 禁止全局中断 */
N#endif
N
N/* 这个宏仅用于调试阶段排错 */
N#define BSP_Printf		printf
N//#define BSP_Printf(...)
N
N#include "stm32f4xx.h"
L 1 "..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx.h
N  * @author  MCD Application Team
N  * @version V1.4.0
N  * @date    04-August-2014
N  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File. 
N  *          This file contains all the peripheral register's definitions, bits 
N  *          definitions and memory mapping for STM32F4xx devices.            
N  *            
N  *          The file is the unique include file that the application programmer
N  *          is using in the C source code, usually in main.c. This file contains:
N  *           - Configuration section that allows to select:
N  *              - The device used in the target application
N  *              - To use or not the peripheral抯 drivers in application code(i.e. 
N  *                code will be based on direct access to peripheral抯 registers 
N  *                rather than drivers API), this option is controlled by 
N  *                "#define USE_STDPERIPH_DRIVER"
N  *              - To change few application-specific parameters such as the HSE 
N  *                crystal frequency
N  *           - Data structures and the address mapping for all peripherals
N  *           - Peripheral's registers declarations and bits definition
N  *           - Macros to access peripheral抯 registers hardware
N  *  
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************  
N  */ 
N
N/** @addtogroup CMSIS
N  * @{
N  */
N
N/** @addtogroup stm32f4xx
N  * @{
N  */
N    
N#ifndef __STM32F4xx_H
N#define __STM32F4xx_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif /* __cplusplus */
N  
N/** @addtogroup Library_configuration_section
N  * @{
N  */
N  
N/* Uncomment the line below according to the target STM32 device used in your
N   application 
N  */
N
N#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE)
X#if !1L && !0L && !0L && !0L && !0L
S  /* #define STM32F40_41xxx */   /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG,  
S                                      STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, 
S                                      STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
S
S  /* #define STM32F427_437xx */  /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II,  
S                                      STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */
S
S  /* #define STM32F429_439xx */  /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI,  
S                                      STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, 
S                                      STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI,
S                                      STM32F439IG and STM32F439II Devices */
S
S  /* #define STM32F401xx */      /*!< STM32F401CB, STM32F401CC,  STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC  
S                                      STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */
S
S  /* #define STM32F411xE */      /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
N#endif
N
N/* Old STM32F40XX definition, maintained for legacy purpose */
N#ifdef STM32F40XX
S  #define STM32F40_41xxx
N#endif /* STM32F40XX */
N
N/* Old STM32F427X definition, maintained for legacy purpose */
N#ifdef STM32F427X
S  #define STM32F427_437xx
N#endif /* STM32F427X */
N
N/*  Tip: To avoid modifying this file each time you need to switch between these
N        devices, you can define the device in your toolchain compiler preprocessor.
N  */
N
N#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE)
X#if !1L && !0L && !0L && !0L && !0L
S #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
N#endif
N
N#if !defined  (USE_STDPERIPH_DRIVER)
X#if !1L
S/**
S * @brief Comment the line below if you will not use the peripherals drivers.
S   In this case, these drivers will not be included and the application code will 
S   be based on direct access to peripherals registers 
S   */
S  /*#define USE_STDPERIPH_DRIVER */
N#endif /* USE_STDPERIPH_DRIVER */
N
N/**
N * @brief In the following line adjust the value of External High Speed oscillator (HSE)
N   used in your application 
N   
N   Tip: To avoid modifying this file each time you need to use different HSE, you
N        can define the HSE value in your toolchain compiler preprocessor.
N  */           
N
N#if !defined  (HSE_VALUE) 
X#if !0L 
N  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
N  
N#endif /* HSE_VALUE */
N
N/**
N * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
N   Timeout value 
N   */
N#if !defined  (HSE_STARTUP_TIMEOUT) 
X#if !0L 
N  #define HSE_STARTUP_TIMEOUT    ((uint16_t)0x05000)   /*!< Time out for HSE start up */
N#endif /* HSE_STARTUP_TIMEOUT */   
N
N#if !defined  (HSI_VALUE)   
X#if !0L   
N  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
N#endif /* HSI_VALUE */   
N
N/**
N * @brief STM32F4XX Standard Peripherals Library version number V1.4.0
N   */
N#define __STM32F4XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
N#define __STM32F4XX_STDPERIPH_VERSION_SUB1   (0x04) /*!< [23:16] sub1 version */
N#define __STM32F4XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
N#define __STM32F4XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
N#define __STM32F4XX_STDPERIPH_VERSION        ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
N                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
N                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
N                                             |(__STM32F4XX_STDPERIPH_VERSION_RC))
X#define __STM32F4XX_STDPERIPH_VERSION        ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)                                             |(__STM32F4XX_STDPERIPH_VERSION_RC))
N                                             
N/**
N  * @}
N  */
N
N/** @addtogroup Configuration_section_for_CMSIS
N  * @{
N  */
N
N/**
N * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
N */
N#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
N#define __MPU_PRESENT             1       /*!< STM32F4XX provides an MPU                     */
N#define __NVIC_PRIO_BITS          4       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
N#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
N#define __FPU_PRESENT             1       /*!< FPU present                                   */
N/**
N * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
N *        in @ref Library_configuration_section 
N */
Ntypedef enum IRQn
N{
N/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
N  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
N  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
N  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
N  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
N  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
N  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
N  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
N  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
N/******  STM32 specific Interrupt Numbers **********************************************************************/
N  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
N  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
N  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
N  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
N  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
N  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
N  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
N  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
N  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
N  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
N  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
N  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
N  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
N  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
N  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
N  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
N  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
N  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
N  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
N
N#if defined (STM32F40_41xxx)
X#if 1L
N  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
N  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
N  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
N  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
N  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
N  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
N  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
N  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
N  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
N  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
N  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
N  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
N  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
N  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
N  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
N  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
N  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
N  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
N  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
N  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
N  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
N  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
N  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
N  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
N  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
N  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
N  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
N  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
N  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
N  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
N  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
N  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
N  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
N  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
N  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
N  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
N  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
N  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
N  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
N  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
N  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
N  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
N  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
N  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
N  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
N  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
N  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
N  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
N  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
N  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
N  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
N  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
N  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
N  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
N  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
N  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
N  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
N  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
N  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
N  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
N  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
N  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
N  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F427_437xx)
X#if 0L
S  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
S  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
S  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
S  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
S  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
S  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
S  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
S  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
S  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
S  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
S  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
S  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
S  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
S  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
S  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
S  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
S  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
S  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
S  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
S  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
S  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
S  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
S  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
S  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
S  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
S  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
S  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
S  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
S  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
S  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
S  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
S  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
S  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
S  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
S  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
S  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
S  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
S  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
S  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
S  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
S  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
S  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
S  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
S  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
S  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
S  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
S  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
S  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
S  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
S  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
S  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
S  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
S  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
S  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
S  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
S  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
S  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
S  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
S  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
S  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
S  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
S  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
S  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
S  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
S  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
S  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
S  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
S  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
S  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
S  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */   
N#endif /* STM32F427_437xx */
N    
N#if defined (STM32F429_439xx)
X#if 0L
S  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
S  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
S  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
S  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
S  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
S  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
S  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
S  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
S  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
S  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
S  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
S  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
S  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
S  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
S  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
S  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
S  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
S  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
S  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
S  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
S  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
S  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
S  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
S  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
S  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
S  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
S  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
S  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
S  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
S  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
S  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
S  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
S  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
S  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
S  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
S  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
S  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
S  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
S  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
S  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
S  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
S  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
S  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
S  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
S  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
S  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
S  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
S  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
S  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
S  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
S  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
S  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
S  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
S  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
S  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
S  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
S  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
S  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
S  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
S  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
S  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
S  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
S  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
S  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
S  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
S  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
S  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
S  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
S  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
S  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
S  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
S  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */
N#endif /* STM32F429_439xx */
N   
N#if defined (STM32F401xx) || defined (STM32F411xE)
X#if 0L || 0L
S  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
S  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
S  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
S  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
S  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
S  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
S  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
S  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
S  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
S  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
S  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
S  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
S  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
S  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
S  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
S  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
S  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
S  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
S  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
S  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
S  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
S  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
S  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
S  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
S  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
S  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
S  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
S  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
S  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
S  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
S  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
S  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
S  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
S  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
S  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
S  FPU_IRQn                    = 81,      /*!< FPU global interrupt                                             */
S#if defined (STM32F401xx)
S  SPI4_IRQn                   = 84       /*!< SPI4 global Interrupt                                            */
S#endif /* STM32F411xE */
S#if defined (STM32F411xE)
S  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
S  SPI5_IRQn                   = 85      /*!< SPI5 global Interrupt                                             */
S#endif /* STM32F411xE */
N#endif /* STM32F401xx || STM32F411xE */
N
N} IRQn_Type;
N
N/**
N  * @}
N  */
N
N#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
L 1 "..\..\Libraries\CMSIS\Include\core_cm4.h" 1
N/**************************************************************************//**
N * @file     core_cm4.h
N * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
N * @version  V4.00
N * @date     22. August 2014
N *
N * @note
N *
N ******************************************************************************/
N/* Copyright (c) 2009 - 2014 ARM LIMITED
N
N   All rights reserved.
N   Redistribution and use in source and binary forms, with or without
N   modification, are permitted provided that the following conditions are met:
N   - Redistributions of source code must retain the above copyright
N     notice, this list of conditions and the following disclaimer.
N   - Redistributions in binary form must reproduce the above copyright
N     notice, this list of conditions and the following disclaimer in the
N     documentation and/or other materials provided with the distribution.
N   - Neither the name of ARM nor the names of its contributors may be used
N     to endorse or promote products derived from this software without
N     specific prior written permission.
N   *
N   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
N   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
N   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
N   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
N   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
N   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
N   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
N   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
N   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
N   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
N   POSSIBILITY OF SUCH DAMAGE.
N   ---------------------------------------------------------------------------*/
N
N
N#if defined ( __ICCARM__ )
X#if 0L
S #pragma system_include  /* treat file as system include file for MISRA check */
N#endif
N
N#ifndef __CORE_CM4_H_GENERIC
N#define __CORE_CM4_H_GENERIC
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
N  CMSIS violates the following MISRA-C:2004 rules:
N
N   \li Required Rule 8.5, object/function definition in header file.<br>
N     Function definitions in header files are used to allow 'inlining'.
N
N   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
N     Unions are used for effective representation of core registers.
N
N   \li Advisory Rule 19.7, Function-like macro defined.<br>
N     Function-like macros are used to allow more efficient code.
N */
N
N
N/*******************************************************************************
N *                 CMSIS definitions
N ******************************************************************************/
N/** \ingroup Cortex_M4
N  @{
N */
N
N/*  CMSIS CM4 definitions */
N#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
N#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
N#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
N                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
X#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) |                                     __CM4_CMSIS_VERSION_SUB          )      
N
N#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
N
N
N#if   defined ( __CC_ARM )
X#if   1L
N  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
N  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
N  #define __STATIC_INLINE  static __inline
N
N#elif defined ( __GNUC__ )
S  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
S  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
S  #define __STATIC_INLINE  static inline
S
S#elif defined ( __ICCARM__ )
S  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
S  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
S  #define __STATIC_INLINE  static inline
S
S#elif defined ( __TMS470__ )
S  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
S  #define __STATIC_INLINE  static inline
S
S#elif defined ( __TASKING__ )
S  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
S  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
S  #define __STATIC_INLINE  static inline
S
S#elif defined ( __CSMC__ )
S  #define __packed
S  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
S  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
S  #define __STATIC_INLINE  static inline
S
N#endif
N
N/** __FPU_USED indicates whether an FPU is used or not.
N    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
N*/
N#if defined ( __CC_ARM )
X#if 1L
N  #if defined __TARGET_FPU_VFP
X  #if 1L
N    #if (__FPU_PRESENT == 1)
X    #if (1 == 1)
N      #define __FPU_USED       1
N    #else
S      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
S      #define __FPU_USED       0
N    #endif
N  #else
S    #define __FPU_USED         0
N  #endif
N
N#elif defined ( __GNUC__ )
S  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
S    #if (__FPU_PRESENT == 1)
S      #define __FPU_USED       1
S    #else
S      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
S      #define __FPU_USED       0
S    #endif
S  #else
S    #define __FPU_USED         0
S  #endif
S
S#elif defined ( __ICCARM__ )
S  #if defined __ARMVFP__
S    #if (__FPU_PRESENT == 1)
S      #define __FPU_USED       1
S    #else
S      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
S      #define __FPU_USED       0
S    #endif
S  #else
S    #define __FPU_USED         0
S  #endif
S
S#elif defined ( __TMS470__ )
S  #if defined __TI_VFP_SUPPORT__
S    #if (__FPU_PRESENT == 1)
S      #define __FPU_USED       1
S    #else
S      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
S      #define __FPU_USED       0
S    #endif
S  #else
S    #define __FPU_USED         0
S  #endif
S
S#elif defined ( __TASKING__ )
S  #if defined __FPU_VFP__
S    #if (__FPU_PRESENT == 1)
S      #define __FPU_USED       1
S    #else
S      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
S      #define __FPU_USED       0
S    #endif
S  #else
S    #define __FPU_USED         0
S  #endif
S
S#elif defined ( __CSMC__ )		/* Cosmic */
S  #if ( __CSMC__ & 0x400)		// FPU present for parser
S    #if (__FPU_PRESENT == 1)
S      #define __FPU_USED       1
S    #else
S      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
S      #define __FPU_USED       0
S    #endif
S  #else
S    #define __FPU_USED         0
S  #endif
N#endif
N
N#include <stdint.h>                      /* standard types definitions                      */
L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h" 1
N/* Copyright (C) ARM Ltd., 1999,2014 */
N/* All rights reserved */
N
N/*
N * RCS $Revision$
N * Checkin $Date$
N * Revising $Author: agrant $
N */
N
N#ifndef __stdint_h
N#define __stdint_h
N#define __ARMCLIB_VERSION 5060037
N
N  #ifdef __INT64_TYPE__
S    /* armclang predefines '__INT64_TYPE__' and '__INT64_C_SUFFIX__' */
S    #define __INT64 __INT64_TYPE__
N  #else
N    /* armcc has builtin '__int64' which can be used in --strict mode */
N    #define __INT64 __int64
N    #define __INT64_C_SUFFIX__ ll
N  #endif
N  #define __PASTE2(x, y) x ## y
N  #define __PASTE(x, y) __PASTE2(x, y)
N  #define __INT64_C(x)  __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
N  #define __UINT64_C(x)  __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
N  #if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__))
X  #if 0L || (1L && !0L)
N    /* armclang and non-strict armcc allow 'long long' in system headers */
N    #define __LONGLONG long long
N  #else
S    /* strict armcc has '__int64' */
S    #define __LONGLONG __int64
N  #endif
N
N  #ifndef __STDINT_DECLS
N  #define __STDINT_DECLS
N
N    #undef __CLIBNS
N
N    #ifdef __cplusplus
S      namespace std {
S          #define __CLIBNS std::
S          extern "C" {
N    #else
N      #define __CLIBNS
N    #endif  /* __cplusplus */
N
N
N/*
N * 'signed' is redundant below, except for 'signed char' and if
N * the typedef is used to declare a bitfield.
N */
N
N    /* 7.18.1.1 */
N
N    /* exact-width signed integer types */
Ntypedef   signed          char int8_t;
Ntypedef   signed short     int int16_t;
Ntypedef   signed           int int32_t;
Ntypedef   signed       __INT64 int64_t;
Xtypedef   signed       __int64 int64_t;
N
N    /* exact-width unsigned integer types */
Ntypedef unsigned          char uint8_t;
Ntypedef unsigned short     int uint16_t;
Ntypedef unsigned           int uint32_t;
Ntypedef unsigned       __INT64 uint64_t;
Xtypedef unsigned       __int64 uint64_t;
N
N    /* 7.18.1.2 */
N
N    /* smallest type of at least n bits */
N    /* minimum-width signed integer types */
Ntypedef   signed          char int_least8_t;
Ntypedef   signed short     int int_least16_t;
Ntypedef   signed           int int_least32_t;
Ntypedef   signed       __INT64 int_least64_t;
Xtypedef   signed       __int64 int_least64_t;
N
N    /* minimum-width unsigned integer types */
Ntypedef unsigned          char uint_least8_t;
Ntypedef unsigned short     int uint_least16_t;
Ntypedef unsigned           int uint_least32_t;
Ntypedef unsigned       __INT64 uint_least64_t;
Xtypedef unsigned       __int64 uint_least64_t;
N
N    /* 7.18.1.3 */
N
N    /* fastest minimum-width signed integer types */
Ntypedef   signed           int int_fast8_t;
Ntypedef   signed           int int_fast16_t;
Ntypedef   signed           int int_fast32_t;
Ntypedef   signed       __INT64 int_fast64_t;
Xtypedef   signed       __int64 int_fast64_t;
N
N    /* fastest minimum-width unsigned integer types */
Ntypedef unsigned           int uint_fast8_t;
Ntypedef unsigned           int uint_fast16_t;
Ntypedef unsigned           int uint_fast32_t;
Ntypedef unsigned       __INT64 uint_fast64_t;
Xtypedef unsigned       __int64 uint_fast64_t;
N
N    /* 7.18.1.4 integer types capable of holding object pointers */
N#if __sizeof_ptr == 8
X#if 4 == 8
Stypedef   signed       __INT64 intptr_t;
Stypedef unsigned       __INT64 uintptr_t;
N#else
Ntypedef   signed           int intptr_t;
Ntypedef unsigned           int uintptr_t;
N#endif
N
N    /* 7.18.1.5 greatest-width integer types */
Ntypedef   signed     __LONGLONG intmax_t;
Xtypedef   signed     long long intmax_t;
Ntypedef unsigned     __LONGLONG uintmax_t;
Xtypedef unsigned     long long uintmax_t;
N
N
N#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS)
X#if !0L || 0L
N
N    /* 7.18.2.1 */
N
N    /* minimum values of exact-width signed integer types */
N#define INT8_MIN                   -128
N#define INT16_MIN                -32768
N#define INT32_MIN          (~0x7fffffff)   /* -2147483648 is unsigned */
N#define INT64_MIN  __INT64_C(~0x7fffffffffffffff) /* -9223372036854775808 is unsigned */
N
N    /* maximum values of exact-width signed integer types */
N#define INT8_MAX                    127
N#define INT16_MAX                 32767
N#define INT32_MAX            2147483647
N#define INT64_MAX  __INT64_C(9223372036854775807)
N
N    /* maximum values of exact-width unsigned integer types */
N#define UINT8_MAX                   255
N#define UINT16_MAX                65535
N#define UINT32_MAX           4294967295u
N#define UINT64_MAX __UINT64_C(18446744073709551615)
N
N    /* 7.18.2.2 */
N
N    /* minimum values of minimum-width signed integer types */
N#define INT_LEAST8_MIN                   -128
N#define INT_LEAST16_MIN                -32768
N#define INT_LEAST32_MIN          (~0x7fffffff)
N#define INT_LEAST64_MIN  __INT64_C(~0x7fffffffffffffff)
N
N    /* maximum values of minimum-width signed integer types */
N#define INT_LEAST8_MAX                    127
N#define INT_LEAST16_MAX                 32767
N#define INT_LEAST32_MAX            2147483647
N#define INT_LEAST64_MAX  __INT64_C(9223372036854775807)
N
N    /* maximum values of minimum-width unsigned integer types */
N#define UINT_LEAST8_MAX                   255
N#define UINT_LEAST16_MAX                65535
N#define UINT_LEAST32_MAX           4294967295u
N#define UINT_LEAST64_MAX __UINT64_C(18446744073709551615)
N
N    /* 7.18.2.3 */
N
N    /* minimum values of fastest minimum-width signed integer types */
N#define INT_FAST8_MIN           (~0x7fffffff)
N#define INT_FAST16_MIN          (~0x7fffffff)
N#define INT_FAST32_MIN          (~0x7fffffff)
N#define INT_FAST64_MIN  __INT64_C(~0x7fffffffffffffff)
N
N    /* maximum values of fastest minimum-width signed integer types */
N#define INT_FAST8_MAX             2147483647
N#define INT_FAST16_MAX            2147483647
N#define INT_FAST32_MAX            2147483647
N#define INT_FAST64_MAX  __INT64_C(9223372036854775807)
N
N    /* maximum values of fastest minimum-width unsigned integer types */
N#define UINT_FAST8_MAX            4294967295u
N#define UINT_FAST16_MAX           4294967295u
N#define UINT_FAST32_MAX           4294967295u
N#define UINT_FAST64_MAX __UINT64_C(18446744073709551615)
N
N    /* 7.18.2.4 */
N
N    /* minimum value of pointer-holding signed integer type */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define INTPTR_MIN INT64_MIN
N#else
N#define INTPTR_MIN INT32_MIN
N#endif
N
N    /* maximum value of pointer-holding signed integer type */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define INTPTR_MAX INT64_MAX
N#else
N#define INTPTR_MAX INT32_MAX
N#endif
N
N    /* maximum value of pointer-holding unsigned integer type */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define UINTPTR_MAX UINT64_MAX
N#else
N#define UINTPTR_MAX UINT32_MAX
N#endif
N
N    /* 7.18.2.5 */
N
N    /* minimum value of greatest-width signed integer type */
N#define INTMAX_MIN  __ESCAPE__(~0x7fffffffffffffffll)
N
N    /* maximum value of greatest-width signed integer type */
N#define INTMAX_MAX  __ESCAPE__(9223372036854775807ll)
N
N    /* maximum value of greatest-width unsigned integer type */
N#define UINTMAX_MAX __ESCAPE__(18446744073709551615ull)
N
N    /* 7.18.3 */
N
N    /* limits of ptrdiff_t */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define PTRDIFF_MIN INT64_MIN
S#define PTRDIFF_MAX INT64_MAX
N#else
N#define PTRDIFF_MIN INT32_MIN
N#define PTRDIFF_MAX INT32_MAX
N#endif
N
N    /* limits of sig_atomic_t */
N#define SIG_ATOMIC_MIN (~0x7fffffff)
N#define SIG_ATOMIC_MAX   2147483647
N
N    /* limit of size_t */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define SIZE_MAX UINT64_MAX
N#else
N#define SIZE_MAX UINT32_MAX
N#endif
N
N    /* limits of wchar_t */
N    /* NB we have to undef and redef because they're defined in both
N     * stdint.h and wchar.h */
N#undef WCHAR_MIN
N#undef WCHAR_MAX
N
N#if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4)
X#if 0L || (0L && __ARM_SIZEOF_WCHAR_T == 4)
S  #define WCHAR_MIN   0
S  #define WCHAR_MAX   0xffffffffU
N#else
N  #define WCHAR_MIN   0
N  #define WCHAR_MAX   65535
N#endif
N
N    /* limits of wint_t */
N#define WINT_MIN (~0x7fffffff)
N#define WINT_MAX 2147483647
N
N#endif /* __STDC_LIMIT_MACROS */
N
N#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS)
X#if !0L || 0L
N
N    /* 7.18.4.1 macros for minimum-width integer constants */
N#define INT8_C(x)   (x)
N#define INT16_C(x)  (x)
N#define INT32_C(x)  (x)
N#define INT64_C(x)  __INT64_C(x)
N
N#define UINT8_C(x)  (x ## u)
N#define UINT16_C(x) (x ## u)
N#define UINT32_C(x) (x ## u)
N#define UINT64_C(x) __UINT64_C(x)
N
N    /* 7.18.4.2 macros for greatest-width integer constants */
N#define INTMAX_C(x)  __ESCAPE__(x ## ll)
N#define UINTMAX_C(x) __ESCAPE__(x ## ull)
N
N#endif /* __STDC_CONSTANT_MACROS */
N
N    #ifdef __cplusplus
S         }  /* extern "C" */
S      }  /* namespace std */
N    #endif /* __cplusplus */
N  #endif /* __STDINT_DECLS */
N
N  #ifdef __cplusplus
S    #ifndef __STDINT_NO_EXPORTS
S      using ::std::int8_t;
S      using ::std::int16_t;
S      using ::std::int32_t;
S      using ::std::int64_t;
S      using ::std::uint8_t;
S      using ::std::uint16_t;
S      using ::std::uint32_t;
S      using ::std::uint64_t;
S      using ::std::int_least8_t;
S      using ::std::int_least16_t;
S      using ::std::int_least32_t;
S      using ::std::int_least64_t;
S      using ::std::uint_least8_t;
S      using ::std::uint_least16_t;
S      using ::std::uint_least32_t;
S      using ::std::uint_least64_t;
S      using ::std::int_fast8_t;
S      using ::std::int_fast16_t;
S      using ::std::int_fast32_t;
S      using ::std::int_fast64_t;
S      using ::std::uint_fast8_t;
S      using ::std::uint_fast16_t;
S      using ::std::uint_fast32_t;
S      using ::std::uint_fast64_t;
S      using ::std::intptr_t;
S      using ::std::uintptr_t;
S      using ::std::intmax_t;
S      using ::std::uintmax_t;
S    #endif
N  #endif /* __cplusplus */
N
N#undef __INT64
N#undef __LONGLONG
N
N#endif /* __stdint_h */
N
N/* end of stdint.h */
L 188 "..\..\Libraries\CMSIS\Include\core_cm4.h" 2
N#include <core_cmInstr.h>                /* Core Instruction Access                         */
L 1 "..\..\Libraries\CMSIS\Include\core_cmInstr.h" 1
N/**************************************************************************//**
N * @file     core_cmInstr.h
N * @brief    CMSIS Cortex-M Core Instruction Access Header File
N * @version  V4.00
N * @date     28. August 2014
N *
N * @note
N *
N ******************************************************************************/
N/* Copyright (c) 2009 - 2014 ARM LIMITED
N
N   All rights reserved.
N   Redistribution and use in source and binary forms, with or without
N   modification, are permitted provided that the following conditions are met:
N   - Redistributions of source code must retain the above copyright
N     notice, this list of conditions and the following disclaimer.
N   - Redistributions in binary form must reproduce the above copyright
N     notice, this list of conditions and the following disclaimer in the
N     documentation and/or other materials provided with the distribution.
N   - Neither the name of ARM nor the names of its contributors may be used
N     to endorse or promote products derived from this software without
N     specific prior written permission.
N   *
N   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
N   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
N   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
N   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
N   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
N   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
N   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
N   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
N   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
N   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
N   POSSIBILITY OF SUCH DAMAGE.
N   ---------------------------------------------------------------------------*/
N
N
N#ifndef __CORE_CMINSTR_H
N#define __CORE_CMINSTR_H
N
N
N/* ##########################  Core Instruction Access  ######################### */
N/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
N  Access to dedicated instructions
N  @{
N*/
N
N#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
X#if   1L  
N/* ARM armcc specific functions */
N
N#if (__ARMCC_VERSION < 400677)
X#if (5060750 < 400677)
S  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
N#endif
N
N
N/** \brief  No Operation
N
N    No Operation does nothing. This instruction can be used for code alignment purposes.
N */
N#define __NOP                             __nop
N
N
N/** \brief  Wait For Interrupt
N
N    Wait For Interrupt is a hint instruction that suspends execution
N    until one of a number of events occurs.
N */
N#define __WFI                             __wfi
N
N
N/** \brief  Wait For Event
N
N    Wait For Event is a hint instruction that permits the processor to enter
N    a low-power state until one of a number of events occurs.
N */
N#define __WFE                             __wfe
N
N
N/** \brief  Send Event
N
N    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
N */
N#define __SEV                             __sev
N
N
N/** \brief  Instruction Synchronization Barrier
N
N    Instruction Synchronization Barrier flushes the pipeline in the processor,
N    so that all instructions following the ISB are fetched from cache or
N    memory, after the instruction has been completed.
N */
N#define __ISB()                           __isb(0xF)
N
N
N/** \brief  Data Synchronization Barrier
N
N    This function acts as a special kind of Data Memory Barrier.
N    It completes when all explicit memory accesses before this instruction complete.
N */
N#define __DSB()                           __dsb(0xF)
N
N
N/** \brief  Data Memory Barrier
N
N    This function ensures the apparent order of the explicit memory operations before
N    and after the instruction, without ensuring their completion.
N */
N#define __DMB()                           __dmb(0xF)
N
N
N/** \brief  Reverse byte order (32 bit)
N
N    This function reverses the byte order in integer value.
N
N    \param [in]    value  Value to reverse
N    \return               Reversed value
N */
N#define __REV                             __rev
N
N
N/** \brief  Reverse byte order (16 bit)
N
N    This function reverses the byte order in two unsigned short values.
N
N    \param [in]    value  Value to reverse
N    \return               Reversed value
N */
N#ifndef __NO_EMBEDDED_ASM
N__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
X__attribute__((section(".rev16_text"))) static __inline __asm uint32_t __REV16(uint32_t value)
N{
N  rev16 r0, r0
N  bx lr
N}
N#endif
N
N/** \brief  Reverse byte order in signed short value
N
N    This function reverses the byte order in a signed short value with sign extension to integer.
N
N    \param [in]    value  Value to reverse
N    \return               Reversed value
N */
N#ifndef __NO_EMBEDDED_ASM
N__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
X__attribute__((section(".revsh_text"))) static __inline __asm int32_t __REVSH(int32_t value)
N{
N  revsh r0, r0
N  bx lr
N}
N#endif
N
N
N/** \brief  Rotate Right in unsigned value (32 bit)
N
N    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
N
N    \param [in]    value  Value to rotate
N    \param [in]    value  Number of Bits to rotate
N    \return               Rotated value
N */
N#define __ROR                             __ror
N
N
N/** \brief  Breakpoint
N
N    This function causes the processor to enter Debug state.
N    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
N
N    \param [in]    value  is ignored by the processor.
N                   If required, a debugger can use it to store additional information about the breakpoint.
N */
N#define __BKPT(value)                       __breakpoint(value)
N
N
N#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
X#if       ((0x04) >= 0x03) || (__CORTEX_SC >= 300)
N
N/** \brief  Reverse bit order of value
N
N    This function reverses the bit order of the given value.
N
N    \param [in]    value  Value to reverse
N    \return               Reversed value
N */
N#define __RBIT                            __rbit
N
N
N/** \brief  LDR Exclusive (8 bit)
N
N    This function executes a exclusive LDR instruction for 8 bit value.
N
N    \param [in]    ptr  Pointer to data
N    \return             value of type uint8_t at (*ptr)
N */
N#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
N
N
N/** \brief  LDR Exclusive (16 bit)
N
N    This function executes a exclusive LDR instruction for 16 bit values.
N
N    \param [in]    ptr  Pointer to data
N    \return        value of type uint16_t at (*ptr)
N */
N#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
N
N
N/** \brief  LDR Exclusive (32 bit)
N
N    This function executes a exclusive LDR instruction for 32 bit values.
N
N    \param [in]    ptr  Pointer to data
N    \return        value of type uint32_t at (*ptr)
N */
N#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
N
N
N/** \brief  STR Exclusive (8 bit)
N
N    This function executes a exclusive STR instruction for 8 bit values.
N
N    \param [in]  value  Value to store
N    \param [in]    ptr  Pointer to location
N    \return          0  Function succeeded
N    \return          1  Function failed
N */
N#define __STREXB(value, ptr)              __strex(value, ptr)
N
N
N/** \brief  STR Exclusive (16 bit)
N
N    This function executes a exclusive STR instruction for 16 bit values.
N
N    \param [in]  value  Value to store
N    \param [in]    ptr  Pointer to location
N    \return          0  Function succeeded
N    \return          1  Function failed
N */
N#define __STREXH(value, ptr)              __strex(value, ptr)
N
N
N/** \brief  STR Exclusive (32 bit)
N
N    This function executes a exclusive STR instruction for 32 bit values.
N
N    \param [in]  value  Value to store
N    \param [in]    ptr  Pointer to location
N    \return          0  Function succeeded
N    \return          1  Function failed
N */
N#define __STREXW(value, ptr)              __strex(value, ptr)
N
N
N/** \brief  Remove the exclusive lock
N
N    This function removes the exclusive lock which is created by LDREX.
N
N */
N#define __CLREX                           __clrex
N
N
N/** \brief  Signed Saturate
N
N    This function saturates a signed value.
N
N    \param [in]  value  Value to be saturated
N    \param [in]    sat  Bit position to saturate to (1..32)
N    \return             Saturated value
N */
N#define __SSAT                            __ssat
N
N
N/** \brief  Unsigned Saturate
N
N    This function saturates an unsigned value.
N
N    \param [in]  value  Value to be saturated
N    \param [in]    sat  Bit position to saturate to (0..31)
N    \return             Saturated value
N */
N#define __USAT                            __usat
N
N
N/** \brief  Count leading zeros
N
N    This function counts the number of leading zeros of a data value.
N
N    \param [in]  value  Value to count the leading zeros
N    \return             number of leading zeros in value
N */
N#define __CLZ                             __clz
N
N
N/** \brief  Rotate Right with Extend (32 bit)
N
N    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
N
N    \param [in]    value  Value to rotate
N    \return               Rotated value
N */
N#ifndef __NO_EMBEDDED_ASM
N__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
X__attribute__((section(".rrx_text"))) static __inline __asm uint32_t __RRX(uint32_t value)
N{
N  rrx r0, r0
N  bx lr
N}
N#endif
N
N
N/** \brief  LDRT Unprivileged (8 bit)
N
N    This function executes a Unprivileged LDRT instruction for 8 bit value.
N
N    \param [in]    ptr  Pointer to data
N    \return             value of type uint8_t at (*ptr)
N */
N#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
N
N
N/** \brief  LDRT Unprivileged (16 bit)
N
N    This function executes a Unprivileged LDRT instruction for 16 bit values.
N
N    \param [in]    ptr  Pointer to data
N    \return        value of type uint16_t at (*ptr)
N */
N#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
N
N
N/** \brief  LDRT Unprivileged (32 bit)
N
N    This function executes a Unprivileged LDRT instruction for 32 bit values.
N
N    \param [in]    ptr  Pointer to data
N    \return        value of type uint32_t at (*ptr)
N */
N#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
N
N
N/** \brief  STRT Unprivileged (8 bit)
N
N    This function executes a Unprivileged STRT instruction for 8 bit values.
N
N    \param [in]  value  Value to store
N    \param [in]    ptr  Pointer to location
N */
N#define __STRBT(value, ptr)               __strt(value, ptr)
N
N
N/** \brief  STRT Unprivileged (16 bit)
N
N    This function executes a Unprivileged STRT instruction for 16 bit values.
N
N    \param [in]  value  Value to store
N    \param [in]    ptr  Pointer to location
N */
N#define __STRHT(value, ptr)               __strt(value, ptr)
N
N
N/** \brief  STRT Unprivileged (32 bit)
N
N    This function executes a Unprivileged STRT instruction for 32 bit values.
N
N    \param [in]  value  Value to store
N    \param [in]    ptr  Pointer to location
N */
N#define __STRT(value, ptr)                __strt(value, ptr)
N
N#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
N
N
N#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
S/* GNU gcc specific functions */
S
S/* Define macros for porting to both thumb1 and thumb2.
S * For thumb1, use low register (r0-r7), specified by constrant "l"
S * Otherwise, use general registers, specified by constrant "r" */
S#if defined (__thumb__) && !defined (__thumb2__)
S#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
S#define __CMSIS_GCC_USE_REG(r) "l" (r)
S#else
S#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
S#define __CMSIS_GCC_USE_REG(r) "r" (r)
S#endif
S
S/** \brief  No Operation
S
S    No Operation does nothing. This instruction can be used for code alignment purposes.
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
S{
S  __ASM volatile ("nop");
S}
S
S
S/** \brief  Wait For Interrupt
S
S    Wait For Interrupt is a hint instruction that suspends execution
S    until one of a number of events occurs.
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
S{
S  __ASM volatile ("wfi");
S}
S
S
S/** \brief  Wait For Event
S
S    Wait For Event is a hint instruction that permits the processor to enter
S    a low-power state until one of a number of events occurs.
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
S{
S  __ASM volatile ("wfe");
S}
S
S
S/** \brief  Send Event
S
S    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
S{
S  __ASM volatile ("sev");
S}
S
S
S/** \brief  Instruction Synchronization Barrier
S
S    Instruction Synchronization Barrier flushes the pipeline in the processor,
S    so that all instructions following the ISB are fetched from cache or
S    memory, after the instruction has been completed.
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
S{
S  __ASM volatile ("isb");
S}
S
S
S/** \brief  Data Synchronization Barrier
S
S    This function acts as a special kind of Data Memory Barrier.
S    It completes when all explicit memory accesses before this instruction complete.
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
S{
S  __ASM volatile ("dsb");
S}
S
S
S/** \brief  Data Memory Barrier
S
S    This function ensures the apparent order of the explicit memory operations before
S    and after the instruction, without ensuring their completion.
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
S{
S  __ASM volatile ("dmb");
S}
S
S
S/** \brief  Reverse byte order (32 bit)
S
S    This function reverses the byte order in integer value.
S
S    \param [in]    value  Value to reverse
S    \return               Reversed value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
S{
S#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
S  return __builtin_bswap32(value);
S#else
S  uint32_t result;
S
S  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
S  return(result);
S#endif
S}
S
S
S/** \brief  Reverse byte order (16 bit)
S
S    This function reverses the byte order in two unsigned short values.
S
S    \param [in]    value  Value to reverse
S    \return               Reversed value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
S{
S  uint32_t result;
S
S  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
S  return(result);
S}
S
S
S/** \brief  Reverse byte order in signed short value
S
S    This function reverses the byte order in a signed short value with sign extension to integer.
S
S    \param [in]    value  Value to reverse
S    \return               Reversed value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
S{
S#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
S  return (short)__builtin_bswap16(value);
S#else
S  uint32_t result;
S
S  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
S  return(result);
S#endif
S}
S
S
S/** \brief  Rotate Right in unsigned value (32 bit)
S
S    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
S
S    \param [in]    value  Value to rotate
S    \param [in]    value  Number of Bits to rotate
S    \return               Rotated value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
S{
S  return (op1 >> op2) | (op1 << (32 - op2)); 
S}
S
S
S/** \brief  Breakpoint
S
S    This function causes the processor to enter Debug state.
S    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
S
S    \param [in]    value  is ignored by the processor.
S                   If required, a debugger can use it to store additional information about the breakpoint.
S */
S#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
S
S
S#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
S
S/** \brief  Reverse bit order of value
S
S    This function reverses the bit order of the given value.
S
S    \param [in]    value  Value to reverse
S    \return               Reversed value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
S{
S  uint32_t result;
S
S   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
S   return(result);
S}
S
S
S/** \brief  LDR Exclusive (8 bit)
S
S    This function executes a exclusive LDR instruction for 8 bit value.
S
S    \param [in]    ptr  Pointer to data
S    \return             value of type uint8_t at (*ptr)
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
S{
S    uint32_t result;
S
S#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
S   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
S#else
S    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
S       accepted by assembler. So has to use following less efficient pattern.
S    */
S   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
S#endif
S   return ((uint8_t) result);    /* Add explicit type cast here */
S}
S
S
S/** \brief  LDR Exclusive (16 bit)
S
S    This function executes a exclusive LDR instruction for 16 bit values.
S
S    \param [in]    ptr  Pointer to data
S    \return        value of type uint16_t at (*ptr)
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
S{
S    uint32_t result;
S
S#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
S   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
S#else
S    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
S       accepted by assembler. So has to use following less efficient pattern.
S    */
S   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
S#endif
S   return ((uint16_t) result);    /* Add explicit type cast here */
S}
S
S
S/** \brief  LDR Exclusive (32 bit)
S
S    This function executes a exclusive LDR instruction for 32 bit values.
S
S    \param [in]    ptr  Pointer to data
S    \return        value of type uint32_t at (*ptr)
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
S{
S    uint32_t result;
S
S   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
S   return(result);
S}
S
S
S/** \brief  STR Exclusive (8 bit)
S
S    This function executes a exclusive STR instruction for 8 bit values.
S
S    \param [in]  value  Value to store
S    \param [in]    ptr  Pointer to location
S    \return          0  Function succeeded
S    \return          1  Function failed
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
S{
S   uint32_t result;
S
S   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
S   return(result);
S}
S
S
S/** \brief  STR Exclusive (16 bit)
S
S    This function executes a exclusive STR instruction for 16 bit values.
S
S    \param [in]  value  Value to store
S    \param [in]    ptr  Pointer to location
S    \return          0  Function succeeded
S    \return          1  Function failed
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
S{
S   uint32_t result;
S
S   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
S   return(result);
S}
S
S
S/** \brief  STR Exclusive (32 bit)
S
S    This function executes a exclusive STR instruction for 32 bit values.
S
S    \param [in]  value  Value to store
S    \param [in]    ptr  Pointer to location
S    \return          0  Function succeeded
S    \return          1  Function failed
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
S{
S   uint32_t result;
S
S   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
S   return(result);
S}
S
S
S/** \brief  Remove the exclusive lock
S
S    This function removes the exclusive lock which is created by LDREX.
S
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
S{
S  __ASM volatile ("clrex" ::: "memory");
S}
S
S
S/** \brief  Signed Saturate
S
S    This function saturates a signed value.
S
S    \param [in]  value  Value to be saturated
S    \param [in]    sat  Bit position to saturate to (1..32)
S    \return             Saturated value
S */
S#define __SSAT(ARG1,ARG2) \
S({                          \
S  uint32_t __RES, __ARG1 = (ARG1); \
S  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
S  __RES; \
S })
X#define __SSAT(ARG1,ARG2) ({                            uint32_t __RES, __ARG1 = (ARG1);   __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) );   __RES;  })
S
S
S/** \brief  Unsigned Saturate
S
S    This function saturates an unsigned value.
S
S    \param [in]  value  Value to be saturated
S    \param [in]    sat  Bit position to saturate to (0..31)
S    \return             Saturated value
S */
S#define __USAT(ARG1,ARG2) \
S({                          \
S  uint32_t __RES, __ARG1 = (ARG1); \
S  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
S  __RES; \
S })
X#define __USAT(ARG1,ARG2) ({                            uint32_t __RES, __ARG1 = (ARG1);   __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) );   __RES;  })
S
S
S/** \brief  Count leading zeros
S
S    This function counts the number of leading zeros of a data value.
S
S    \param [in]  value  Value to count the leading zeros
S    \return             number of leading zeros in value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
S{
S  uint32_t result;
S
S  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
S   return ((uint8_t) result);    /* Add explicit type cast here */
S}
S
S
S/** \brief  Rotate Right with Extend (32 bit)
S
S    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
S
S    \param [in]    value  Value to rotate
S    \return               Rotated value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
S{
S  uint32_t result;
S
S  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
S  return(result);
S}
S
S
S/** \brief  LDRT Unprivileged (8 bit)
S
S    This function executes a Unprivileged LDRT instruction for 8 bit value.
S
S    \param [in]    ptr  Pointer to data
S    \return             value of type uint8_t at (*ptr)
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
S{
S    uint32_t result;
S
S#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
S   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
S#else
S    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
S       accepted by assembler. So has to use following less efficient pattern.
S    */
S   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
S#endif
S   return ((uint8_t) result);    /* Add explicit type cast here */
S}
S
S
S/** \brief  LDRT Unprivileged (16 bit)
S
S    This function executes a Unprivileged LDRT instruction for 16 bit values.
S
S    \param [in]    ptr  Pointer to data
S    \return        value of type uint16_t at (*ptr)
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
S{
S    uint32_t result;
S
S#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
S   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
S#else
S    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
S       accepted by assembler. So has to use following less efficient pattern.
S    */
S   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
S#endif
S   return ((uint16_t) result);    /* Add explicit type cast here */
S}
S
S
S/** \brief  LDRT Unprivileged (32 bit)
S
S    This function executes a Unprivileged LDRT instruction for 32 bit values.
S
S    \param [in]    ptr  Pointer to data
S    \return        value of type uint32_t at (*ptr)
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
S{
S    uint32_t result;
S
S   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
S   return(result);
S}
S
S
S/** \brief  STRT Unprivileged (8 bit)
S
S    This function executes a Unprivileged STRT instruction for 8 bit values.
S
S    \param [in]  value  Value to store
S    \param [in]    ptr  Pointer to location
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
S{
S   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
S}
S
S
S/** \brief  STRT Unprivileged (16 bit)
S
S    This function executes a Unprivileged STRT instruction for 16 bit values.
S
S    \param [in]  value  Value to store
S    \param [in]    ptr  Pointer to location
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
S{
S   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
S}
S
S
S/** \brief  STRT Unprivileged (32 bit)
S
S    This function executes a Unprivileged STRT instruction for 32 bit values.
S
S    \param [in]  value  Value to store
S    \param [in]    ptr  Pointer to location
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
S{
S   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
S}
S
S#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
S
S
S#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
S/* IAR iccarm specific functions */
S#include <cmsis_iar.h>
S
S
S#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
S/* TI CCS specific functions */
S#include <cmsis_ccs.h>
S
S
S#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
S/* TASKING carm specific functions */
S/*
S * The CMSIS functions have been implemented as intrinsics in the compiler.
S * Please use "carm -?i" to get an up to date list of all intrinsics,
S * Including the CMSIS ones.
S */
S
S
S#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
S/* Cosmic specific functions */
S#include <cmsis_csm.h>
S
N#endif
N
N/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
N
N#endif /* __CORE_CMINSTR_H */
L 189 "..\..\Libraries\CMSIS\Include\core_cm4.h" 2
N#include <core_cmFunc.h>                 /* Core Function Access                            */
L 1 "..\..\Libraries\CMSIS\Include\core_cmFunc.h" 1
N/**************************************************************************//**
N * @file     core_cmFunc.h
N * @brief    CMSIS Cortex-M Core Function Access Header File
N * @version  V4.00
N * @date     28. August 2014
N *
N * @note
N *
N ******************************************************************************/
N/* Copyright (c) 2009 - 2014 ARM LIMITED
N
N   All rights reserved.
N   Redistribution and use in source and binary forms, with or without
N   modification, are permitted provided that the following conditions are met:
N   - Redistributions of source code must retain the above copyright
N     notice, this list of conditions and the following disclaimer.
N   - Redistributions in binary form must reproduce the above copyright
N     notice, this list of conditions and the following disclaimer in the
N     documentation and/or other materials provided with the distribution.
N   - Neither the name of ARM nor the names of its contributors may be used
N     to endorse or promote products derived from this software without
N     specific prior written permission.
N   *
N   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
N   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
N   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
N   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
N   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
N   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
N   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
N   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
N   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
N   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
N   POSSIBILITY OF SUCH DAMAGE.
N   ---------------------------------------------------------------------------*/
N
N
N#ifndef __CORE_CMFUNC_H
N#define __CORE_CMFUNC_H
N
N
N/* ###########################  Core Function Access  ########################### */
N/** \ingroup  CMSIS_Core_FunctionInterface
N    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
N  @{
N */
N
N#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
X#if   1L  
N/* ARM armcc specific functions */
N
N#if (__ARMCC_VERSION < 400677)
X#if (5060750 < 400677)
S  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
N#endif
N
N/* intrinsic void __enable_irq();     */
N/* intrinsic void __disable_irq();    */
N
N/** \brief  Get Control Register
N
N    This function returns the content of the Control Register.
N
N    \return               Control Register value
N */
N__STATIC_INLINE uint32_t __get_CONTROL(void)
Xstatic __inline uint32_t __get_CONTROL(void)
N{
N  register uint32_t __regControl         __ASM("control");
X  register uint32_t __regControl         __asm("control");
N  return(__regControl);
N}
N
N
N/** \brief  Set Control Register
N
N    This function writes the given value to the Control Register.
N
N    \param [in]    control  Control Register value to set
N */
N__STATIC_INLINE void __set_CONTROL(uint32_t control)
Xstatic __inline void __set_CONTROL(uint32_t control)
N{
N  register uint32_t __regControl         __ASM("control");
X  register uint32_t __regControl         __asm("control");
N  __regControl = control;
N}
N
N
N/** \brief  Get IPSR Register
N
N    This function returns the content of the IPSR Register.
N
N    \return               IPSR Register value
N */
N__STATIC_INLINE uint32_t __get_IPSR(void)
Xstatic __inline uint32_t __get_IPSR(void)
N{
N  register uint32_t __regIPSR          __ASM("ipsr");
X  register uint32_t __regIPSR          __asm("ipsr");
N  return(__regIPSR);
N}
N
N
N/** \brief  Get APSR Register
N
N    This function returns the content of the APSR Register.
N
N    \return               APSR Register value
N */
N__STATIC_INLINE uint32_t __get_APSR(void)
Xstatic __inline uint32_t __get_APSR(void)
N{
N  register uint32_t __regAPSR          __ASM("apsr");
X  register uint32_t __regAPSR          __asm("apsr");
N  return(__regAPSR);
N}
N
N
N/** \brief  Get xPSR Register
N
N    This function returns the content of the xPSR Register.
N
N    \return               xPSR Register value
N */
N__STATIC_INLINE uint32_t __get_xPSR(void)
Xstatic __inline uint32_t __get_xPSR(void)
N{
N  register uint32_t __regXPSR          __ASM("xpsr");
X  register uint32_t __regXPSR          __asm("xpsr");
N  return(__regXPSR);
N}
N
N
N/** \brief  Get Process Stack Pointer
N
N    This function returns the current value of the Process Stack Pointer (PSP).
N
N    \return               PSP Register value
N */
N__STATIC_INLINE uint32_t __get_PSP(void)
Xstatic __inline uint32_t __get_PSP(void)
N{
N  register uint32_t __regProcessStackPointer  __ASM("psp");
X  register uint32_t __regProcessStackPointer  __asm("psp");
N  return(__regProcessStackPointer);
N}
N
N
N/** \brief  Set Process Stack Pointer
N
N    This function assigns the given value to the Process Stack Pointer (PSP).
N
N    \param [in]    topOfProcStack  Process Stack Pointer value to set
N */
N__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Xstatic __inline void __set_PSP(uint32_t topOfProcStack)
N{
N  register uint32_t __regProcessStackPointer  __ASM("psp");
X  register uint32_t __regProcessStackPointer  __asm("psp");
N  __regProcessStackPointer = topOfProcStack;
N}
N
N
N/** \brief  Get Main Stack Pointer
N
N    This function returns the current value of the Main Stack Pointer (MSP).
N
N    \return               MSP Register value
N */
N__STATIC_INLINE uint32_t __get_MSP(void)
Xstatic __inline uint32_t __get_MSP(void)
N{
N  register uint32_t __regMainStackPointer     __ASM("msp");
X  register uint32_t __regMainStackPointer     __asm("msp");
N  return(__regMainStackPointer);
N}
N
N
N/** \brief  Set Main Stack Pointer
N
N    This function assigns the given value to the Main Stack Pointer (MSP).
N
N    \param [in]    topOfMainStack  Main Stack Pointer value to set
N */
N__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Xstatic __inline void __set_MSP(uint32_t topOfMainStack)
N{
N  register uint32_t __regMainStackPointer     __ASM("msp");
X  register uint32_t __regMainStackPointer     __asm("msp");
N  __regMainStackPointer = topOfMainStack;
N}
N
N
N/** \brief  Get Priority Mask
N
N    This function returns the current state of the priority mask bit from the Priority Mask Register.
N
N    \return               Priority Mask value
N */
N__STATIC_INLINE uint32_t __get_PRIMASK(void)
Xstatic __inline uint32_t __get_PRIMASK(void)
N{
N  register uint32_t __regPriMask         __ASM("primask");
X  register uint32_t __regPriMask         __asm("primask");
N  return(__regPriMask);
N}
N
N
N/** \brief  Set Priority Mask
N
N    This function assigns the given value to the Priority Mask Register.
N
N    \param [in]    priMask  Priority Mask
N */
N__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Xstatic __inline void __set_PRIMASK(uint32_t priMask)
N{
N  register uint32_t __regPriMask         __ASM("primask");
X  register uint32_t __regPriMask         __asm("primask");
N  __regPriMask = (priMask);
N}
N
N
N#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
X#if       ((0x04) >= 0x03) || (__CORTEX_SC >= 300)
N
N/** \brief  Enable FIQ
N
N    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
N    Can only be executed in Privileged modes.
N */
N#define __enable_fault_irq                __enable_fiq
N
N
N/** \brief  Disable FIQ
N
N    This function disables FIQ interrupts by setting the F-bit in the CPSR.
N    Can only be executed in Privileged modes.
N */
N#define __disable_fault_irq               __disable_fiq
N
N
N/** \brief  Get Base Priority
N
N    This function returns the current value of the Base Priority register.
N
N    \return               Base Priority register value
N */
N__STATIC_INLINE uint32_t  __get_BASEPRI(void)
Xstatic __inline uint32_t  __get_BASEPRI(void)
N{
N  register uint32_t __regBasePri         __ASM("basepri");
X  register uint32_t __regBasePri         __asm("basepri");
N  return(__regBasePri);
N}
N
N
N/** \brief  Set Base Priority
N
N    This function assigns the given value to the Base Priority register.
N
N    \param [in]    basePri  Base Priority value to set
N */
N__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
Xstatic __inline void __set_BASEPRI(uint32_t basePri)
N{
N  register uint32_t __regBasePri         __ASM("basepri");
X  register uint32_t __regBasePri         __asm("basepri");
N  __regBasePri = (basePri & 0xff);
N}
N
N
N/** \brief  Get Fault Mask
N
N    This function returns the current value of the Fault Mask register.
N
N    \return               Fault Mask register value
N */
N__STATIC_INLINE uint32_t __get_FAULTMASK(void)
Xstatic __inline uint32_t __get_FAULTMASK(void)
N{
N  register uint32_t __regFaultMask       __ASM("faultmask");
X  register uint32_t __regFaultMask       __asm("faultmask");
N  return(__regFaultMask);
N}
N
N
N/** \brief  Set Fault Mask
N
N    This function assigns the given value to the Fault Mask register.
N
N    \param [in]    faultMask  Fault Mask value to set
N */
N__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
Xstatic __inline void __set_FAULTMASK(uint32_t faultMask)
N{
N  register uint32_t __regFaultMask       __ASM("faultmask");
X  register uint32_t __regFaultMask       __asm("faultmask");
N  __regFaultMask = (faultMask & (uint32_t)1);
N}
N
N#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
N
N
N#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
X#if       ((0x04) == 0x04) || ((0x04) == 0x07)
N
N/** \brief  Get FPSCR
N
N    This function returns the current value of the Floating Point Status/Control register.
N
N    \return               Floating Point Status/Control register value
N */
N__STATIC_INLINE uint32_t __get_FPSCR(void)
Xstatic __inline uint32_t __get_FPSCR(void)
N{
N#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
X#if (1 == 1) && (1 == 1)
N  register uint32_t __regfpscr         __ASM("fpscr");
X  register uint32_t __regfpscr         __asm("fpscr");
N  return(__regfpscr);
N#else
S   return(0);
N#endif
N}
N
N
N/** \brief  Set FPSCR
N
N    This function assigns the given value to the Floating Point Status/Control register.
N
N    \param [in]    fpscr  Floating Point Status/Control value to set
N */
N__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Xstatic __inline void __set_FPSCR(uint32_t fpscr)
N{
N#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
X#if (1 == 1) && (1 == 1)
N  register uint32_t __regfpscr         __ASM("fpscr");
X  register uint32_t __regfpscr         __asm("fpscr");
N  __regfpscr = (fpscr);
N#endif
N}
N
N#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
N
N
N#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
S/* GNU gcc specific functions */
S
S/** \brief  Enable IRQ Interrupts
S
S  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
S  Can only be executed in Privileged modes.
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
S{
S  __ASM volatile ("cpsie i" : : : "memory");
S}
S
S
S/** \brief  Disable IRQ Interrupts
S
S  This function disables IRQ interrupts by setting the I-bit in the CPSR.
S  Can only be executed in Privileged modes.
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
S{
S  __ASM volatile ("cpsid i" : : : "memory");
S}
S
S
S/** \brief  Get Control Register
S
S    This function returns the content of the Control Register.
S
S    \return               Control Register value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
S{
S  uint32_t result;
S
S  __ASM volatile ("MRS %0, control" : "=r" (result) );
S  return(result);
S}
S
S
S/** \brief  Set Control Register
S
S    This function writes the given value to the Control Register.
S
S    \param [in]    control  Control Register value to set
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
S{
S  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
S}
S
S
S/** \brief  Get IPSR Register
S
S    This function returns the content of the IPSR Register.
S
S    \return               IPSR Register value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
S{
S  uint32_t result;
S
S  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
S  return(result);
S}
S
S
S/** \brief  Get APSR Register
S
S    This function returns the content of the APSR Register.
S
S    \return               APSR Register value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
S{
S  uint32_t result;
S
S  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
S  return(result);
S}
S
S
S/** \brief  Get xPSR Register
S
S    This function returns the content of the xPSR Register.
S
S    \return               xPSR Register value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
S{
S  uint32_t result;
S
S  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
S  return(result);
S}
S
S
S/** \brief  Get Process Stack Pointer
S
S    This function returns the current value of the Process Stack Pointer (PSP).
S
S    \return               PSP Register value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
S{
S  register uint32_t result;
S
S  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
S  return(result);
S}
S
S
S/** \brief  Set Process Stack Pointer
S
S    This function assigns the given value to the Process Stack Pointer (PSP).
S
S    \param [in]    topOfProcStack  Process Stack Pointer value to set
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
S{
S  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
S}
S
S
S/** \brief  Get Main Stack Pointer
S
S    This function returns the current value of the Main Stack Pointer (MSP).
S
S    \return               MSP Register value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
S{
S  register uint32_t result;
S
S  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
S  return(result);
S}
S
S
S/** \brief  Set Main Stack Pointer
S
S    This function assigns the given value to the Main Stack Pointer (MSP).
S
S    \param [in]    topOfMainStack  Main Stack Pointer value to set
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
S{
S  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
S}
S
S
S/** \brief  Get Priority Mask
S
S    This function returns the current state of the priority mask bit from the Priority Mask Register.
S
S    \return               Priority Mask value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
S{
S  uint32_t result;
S
S  __ASM volatile ("MRS %0, primask" : "=r" (result) );
S  return(result);
S}
S
S
S/** \brief  Set Priority Mask
S
S    This function assigns the given value to the Priority Mask Register.
S
S    \param [in]    priMask  Priority Mask
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
S{
S  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
S}
S
S
S#if       (__CORTEX_M >= 0x03)
S
S/** \brief  Enable FIQ
S
S    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
S    Can only be executed in Privileged modes.
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
S{
S  __ASM volatile ("cpsie f" : : : "memory");
S}
S
S
S/** \brief  Disable FIQ
S
S    This function disables FIQ interrupts by setting the F-bit in the CPSR.
S    Can only be executed in Privileged modes.
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
S{
S  __ASM volatile ("cpsid f" : : : "memory");
S}
S
S
S/** \brief  Get Base Priority
S
S    This function returns the current value of the Base Priority register.
S
S    \return               Base Priority register value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
S{
S  uint32_t result;
S
S  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
S  return(result);
S}
S
S
S/** \brief  Set Base Priority
S
S    This function assigns the given value to the Base Priority register.
S
S    \param [in]    basePri  Base Priority value to set
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
S{
S  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
S}
S
S
S/** \brief  Get Fault Mask
S
S    This function returns the current value of the Fault Mask register.
S
S    \return               Fault Mask register value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
S{
S  uint32_t result;
S
S  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
S  return(result);
S}
S
S
S/** \brief  Set Fault Mask
S
S    This function assigns the given value to the Fault Mask register.
S
S    \param [in]    faultMask  Fault Mask value to set
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
S{
S  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
S}
S
S#endif /* (__CORTEX_M >= 0x03) */
S
S
S#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
S
S/** \brief  Get FPSCR
S
S    This function returns the current value of the Floating Point Status/Control register.
S
S    \return               Floating Point Status/Control register value
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
S{
S#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
S  uint32_t result;
S
S  /* Empty asm statement works as a scheduling barrier */
S  __ASM volatile ("");
S  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
S  __ASM volatile ("");
S  return(result);
S#else
S   return(0);
S#endif
S}
S
S
S/** \brief  Set FPSCR
S
S    This function assigns the given value to the Floating Point Status/Control register.
S
S    \param [in]    fpscr  Floating Point Status/Control value to set
S */
S__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
S{
S#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
S  /* Empty asm statement works as a scheduling barrier */
S  __ASM volatile ("");
S  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
S  __ASM volatile ("");
S#endif
S}
S
S#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
S
S
S#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
S/* IAR iccarm specific functions */
S#include <cmsis_iar.h>
S
S
S#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
S/* TI CCS specific functions */
S#include <cmsis_ccs.h>
S
S
S#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
S/* TASKING carm specific functions */
S/*
S * The CMSIS functions have been implemented as intrinsics in the compiler.
S * Please use "carm -?i" to get an up to date list of all intrinsics,
S * Including the CMSIS ones.
S */
S
S
S#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
S/* Cosmic specific functions */
S#include <cmsis_csm.h>
S
N#endif
N
N/*@} end of CMSIS_Core_RegAccFunctions */
N
N#endif /* __CORE_CMFUNC_H */
L 190 "..\..\Libraries\CMSIS\Include\core_cm4.h" 2
N#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
L 1 "..\..\Libraries\CMSIS\Include\core_cmSimd.h" 1
N/**************************************************************************//**
N * @file     core_cmSimd.h
N * @brief    CMSIS Cortex-M SIMD Header File
N * @version  V4.00
N * @date     22. August 2014
N *
N * @note
N *
N ******************************************************************************/
N/* Copyright (c) 2009 - 2014 ARM LIMITED
N
N   All rights reserved.
N   Redistribution and use in source and binary forms, with or without
N   modification, are permitted provided that the following conditions are met:
N   - Redistributions of source code must retain the above copyright
N     notice, this list of conditions and the following disclaimer.
N   - Redistributions in binary form must reproduce the above copyright
N     notice, this list of conditions and the following disclaimer in the
N     documentation and/or other materials provided with the distribution.
N   - Neither the name of ARM nor the names of its contributors may be used
N     to endorse or promote products derived from this software without
N     specific prior written permission.
N   *
N   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
N   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
N   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
N   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
N   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
N   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
N   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
N   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
N   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
N   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
N   POSSIBILITY OF SUCH DAMAGE.
N   ---------------------------------------------------------------------------*/
N
N
N#if defined ( __ICCARM__ )
X#if 0L
S #pragma system_include  /* treat file as system include file for MISRA check */
N#endif
N
N#ifndef __CORE_CMSIMD_H
N#define __CORE_CMSIMD_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N
N/*******************************************************************************
N *                Hardware Abstraction Layer
N ******************************************************************************/
N
N
N/* ###################  Compiler specific Intrinsics  ########################### */
N/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
N  Access to dedicated SIMD instructions
N  @{
N*/
N
N#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
X#if   1L  
N/* ARM armcc specific functions */
N#define __SADD8                           __sadd8
N#define __QADD8                           __qadd8
N#define __SHADD8                          __shadd8
N#define __UADD8                           __uadd8
N#define __UQADD8                          __uqadd8
N#define __UHADD8                          __uhadd8
N#define __SSUB8                           __ssub8
N#define __QSUB8                           __qsub8
N#define __SHSUB8                          __shsub8
N#define __USUB8                           __usub8
N#define __UQSUB8                          __uqsub8
N#define __UHSUB8                          __uhsub8
N#define __SADD16                          __sadd16
N#define __QADD16                          __qadd16
N#define __SHADD16                         __shadd16
N#define __UADD16                          __uadd16
N#define __UQADD16                         __uqadd16
N#define __UHADD16                         __uhadd16
N#define __SSUB16                          __ssub16
N#define __QSUB16                          __qsub16
N#define __SHSUB16                         __shsub16
N#define __USUB16                          __usub16
N#define __UQSUB16                         __uqsub16
N#define __UHSUB16                         __uhsub16
N#define __SASX                            __sasx
N#define __QASX                            __qasx
N#define __SHASX                           __shasx
N#define __UASX                            __uasx
N#define __UQASX                           __uqasx
N#define __UHASX                           __uhasx
N#define __SSAX                            __ssax
N#define __QSAX                            __qsax
N#define __SHSAX                           __shsax
N#define __USAX                            __usax
N#define __UQSAX                           __uqsax
N#define __UHSAX                           __uhsax
N#define __USAD8                           __usad8
N#define __USADA8                          __usada8
N#define __SSAT16                          __ssat16
N#define __USAT16                          __usat16
N#define __UXTB16                          __uxtb16
N#define __UXTAB16                         __uxtab16
N#define __SXTB16                          __sxtb16
N#define __SXTAB16                         __sxtab16
N#define __SMUAD                           __smuad
N#define __SMUADX                          __smuadx
N#define __SMLAD                           __smlad
N#define __SMLADX                          __smladx
N#define __SMLALD                          __smlald
N#define __SMLALDX                         __smlaldx
N#define __SMUSD                           __smusd
N#define __SMUSDX                          __smusdx
N#define __SMLSD                           __smlsd
N#define __SMLSDX                          __smlsdx
N#define __SMLSLD                          __smlsld
N#define __SMLSLDX                         __smlsldx
N#define __SEL                             __sel
N#define __QADD                            __qadd
N#define __QSUB                            __qsub
N
N#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
N                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
X#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |                                             ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
N
N#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
N                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
X#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |                                             ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
N
N#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
N                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
X#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) +                                                       ((int64_t)(ARG3) << 32)      ) >> 32))
N
N
N#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
S/* GNU gcc specific functions */
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
S{
S  uint32_t result;
S
S  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
S  return(result);
S}
S
S#define __SSAT16(ARG1,ARG2) \
S({                          \
S  uint32_t __RES, __ARG1 = (ARG1); \
S  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
S  __RES; \
S })
X#define __SSAT16(ARG1,ARG2) ({                            uint32_t __RES, __ARG1 = (ARG1);   __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) );   __RES;  })
S
S#define __USAT16(ARG1,ARG2) \
S({                          \
S  uint32_t __RES, __ARG1 = (ARG1); \
S  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
S  __RES; \
S })
X#define __USAT16(ARG1,ARG2) ({                            uint32_t __RES, __ARG1 = (ARG1);   __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) );   __RES;  })
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
S{
S  uint32_t result;
S
S  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
S{
S  uint32_t result;
S
S  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
S{
S  uint32_t result;
S
S  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
S{
S  uint32_t result;
S
S  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
S{
S  union llreg_u{
S    uint32_t w32[2];
S    uint64_t w64;
S  } llr;
S  llr.w64 = acc;
S
S#ifndef __ARMEB__   // Little endian
S  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
S#else               // Big endian
S  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
S#endif
S
S  return(llr.w64);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
S{
S  union llreg_u{
S    uint32_t w32[2];
S    uint64_t w64;
S  } llr;
S  llr.w64 = acc;
S
S#ifndef __ARMEB__   // Little endian
S  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
S#else               // Big endian
S  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
S#endif
S
S  return(llr.w64);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
S{
S  uint32_t result;
S
S  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
S{
S  uint32_t result;
S
S  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
S{
S  union llreg_u{
S    uint32_t w32[2];
S    uint64_t w64;
S  } llr;
S  llr.w64 = acc;
S
S#ifndef __ARMEB__   // Little endian
S  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
S#else               // Big endian
S  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
S#endif
S
S  return(llr.w64);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
S{
S  union llreg_u{
S    uint32_t w32[2];
S    uint64_t w64;
S  } llr;
S  llr.w64 = acc;
S
S#ifndef __ARMEB__   // Little endian
S  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
S#else               // Big endian
S  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
S#endif
S
S  return(llr.w64);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
S{
S  uint32_t result;
S
S  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
S  return(result);
S}
S
S#define __PKHBT(ARG1,ARG2,ARG3) \
S({                          \
S  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
S  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
S  __RES; \
S })
X#define __PKHBT(ARG1,ARG2,ARG3) ({                            uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2);   __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  );   __RES;  })
S
S#define __PKHTB(ARG1,ARG2,ARG3) \
S({                          \
S  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
S  if (ARG3 == 0) \
S    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
S  else \
S    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
S  __RES; \
S })
X#define __PKHTB(ARG1,ARG2,ARG3) ({                            uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2);   if (ARG3 == 0)     __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  );   else     __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  );   __RES;  })
S
S__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
S{
S int32_t result;
S
S __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
S return(result);
S}
S
S
S#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
S/* IAR iccarm specific functions */
S#include <cmsis_iar.h>
S
S
S#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
S/* TI CCS specific functions */
S#include <cmsis_ccs.h>
S
S
S#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
S/* TASKING carm specific functions */
S/* not yet supported */
S
S
S#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
S/* Cosmic specific functions */
S#include <cmsis_csm.h>
S
N#endif
N
N/*@} end of group CMSIS_SIMD_intrinsics */
N
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __CORE_CMSIMD_H */
L 191 "..\..\Libraries\CMSIS\Include\core_cm4.h" 2
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __CORE_CM4_H_GENERIC */
N
N#ifndef __CMSIS_GENERIC
N
N#ifndef __CORE_CM4_H_DEPENDANT
N#define __CORE_CM4_H_DEPENDANT
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* check device defines and use defaults */
N#if defined __CHECK_DEVICE_DEFINES
X#if 0L
S  #ifndef __CM4_REV
S    #define __CM4_REV               0x0000
S    #warning "__CM4_REV not defined in device header file; using default!"
S  #endif
S
S  #ifndef __FPU_PRESENT
S    #define __FPU_PRESENT             0
S    #warning "__FPU_PRESENT not defined in device header file; using default!"
S  #endif
S
S  #ifndef __MPU_PRESENT
S    #define __MPU_PRESENT             0
S    #warning "__MPU_PRESENT not defined in device header file; using default!"
S  #endif
S
S  #ifndef __NVIC_PRIO_BITS
S    #define __NVIC_PRIO_BITS          4
S    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
S  #endif
S
S  #ifndef __Vendor_SysTickConfig
S    #define __Vendor_SysTickConfig    0
S    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
S  #endif
N#endif
N
N/* IO definitions (access restrictions to peripheral registers) */
N/**
N    \defgroup CMSIS_glob_defs CMSIS Global Defines
N
N    <strong>IO Type Qualifiers</strong> are used
N    \li to specify the access to peripheral variables.
N    \li for automatic generation of peripheral register debug information.
N*/
N#ifdef __cplusplus
S  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
N#else
N  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
N#endif
N#define     __O     volatile             /*!< Defines 'write only' permissions                */
N#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
N
N/*@} end of group Cortex_M4 */
N
N
N
N/*******************************************************************************
N *                 Register Abstraction
N  Core Register contain:
N  - Core Register
N  - Core NVIC Register
N  - Core SCB Register
N  - Core SysTick Register
N  - Core Debug Register
N  - Core MPU Register
N  - Core FPU Register
N ******************************************************************************/
N/** \defgroup CMSIS_core_register Defines and Type Definitions
N    \brief Type definitions and defines for Cortex-M processor based devices.
N*/
N
N/** \ingroup    CMSIS_core_register
N    \defgroup   CMSIS_CORE  Status and Control Registers
N    \brief  Core Register type definitions.
N  @{
N */
N
N/** \brief  Union type to access the Application Program Status Register (APSR).
N */
Ntypedef union
N{
N  struct
N  {
N#if (__CORTEX_M != 0x04)
X#if ((0x04) != 0x04)
S    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
N#else
N    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
N    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
N    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
N#endif
N    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
N    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
N    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
N    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
N    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
N  } b;                                   /*!< Structure used for bit  access                  */
N  uint32_t w;                            /*!< Type      used for word access                  */
N} APSR_Type;
N
N
N/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
N */
Ntypedef union
N{
N  struct
N  {
N    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
N    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
N  } b;                                   /*!< Structure used for bit  access                  */
N  uint32_t w;                            /*!< Type      used for word access                  */
N} IPSR_Type;
N
N
N/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
N */
Ntypedef union
N{
N  struct
N  {
N    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
N#if (__CORTEX_M != 0x04)
X#if ((0x04) != 0x04)
S    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
N#else
N    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
N    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
N    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
N#endif
N    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
N    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
N    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
N    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
N    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
N    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
N    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
N  } b;                                   /*!< Structure used for bit  access                  */
N  uint32_t w;                            /*!< Type      used for word access                  */
N} xPSR_Type;
N
N
N/** \brief  Union type to access the Control Registers (CONTROL).
N */
Ntypedef union
N{
N  struct
N  {
N    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
N    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
N    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
N    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
N  } b;                                   /*!< Structure used for bit  access                  */
N  uint32_t w;                            /*!< Type      used for word access                  */
N} CONTROL_Type;
N
N/*@} end of group CMSIS_CORE */
N
N
N/** \ingroup    CMSIS_core_register
N    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
N    \brief      Type definitions for the NVIC Registers
N  @{
N */
N
N/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
N */
Ntypedef struct
N{
N  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
X  volatile uint32_t ISER[8];                  
N       uint32_t RESERVED0[24];
N  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
X  volatile uint32_t ICER[8];                  
N       uint32_t RSERVED1[24];
N  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
X  volatile uint32_t ISPR[8];                  
N       uint32_t RESERVED2[24];
N  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
X  volatile uint32_t ICPR[8];                  
N       uint32_t RESERVED3[24];
N  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
X  volatile uint32_t IABR[8];                  
N       uint32_t RESERVED4[56];
N  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
X  volatile uint8_t  IP[240];                  
N       uint32_t RESERVED5[644];
N  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
X  volatile  uint32_t STIR;                     
N}  NVIC_Type;
N
N/* Software Triggered Interrupt Register Definitions */
N#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
N#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
N
N/*@} end of group CMSIS_NVIC */
N
N
N/** \ingroup  CMSIS_core_register
N    \defgroup CMSIS_SCB     System Control Block (SCB)
N    \brief      Type definitions for the System Control Block Registers
N  @{
N */
N
N/** \brief  Structure type to access the System Control Block (SCB).
N */
Ntypedef struct
N{
N  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
X  volatile const  uint32_t CPUID;                    
N  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
X  volatile uint32_t ICSR;                     
N  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
X  volatile uint32_t VTOR;                     
N  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
X  volatile uint32_t AIRCR;                    
N  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
X  volatile uint32_t SCR;                      
N  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
X  volatile uint32_t CCR;                      
N  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
X  volatile uint8_t  SHP[12];                  
N  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
X  volatile uint32_t SHCSR;                    
N  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
X  volatile uint32_t CFSR;                     
N  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
X  volatile uint32_t HFSR;                     
N  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
X  volatile uint32_t DFSR;                     
N  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
X  volatile uint32_t MMFAR;                    
N  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
X  volatile uint32_t BFAR;                     
N  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
X  volatile uint32_t AFSR;                     
N  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
X  volatile const  uint32_t PFR[2];                   
N  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
X  volatile const  uint32_t DFR;                      
N  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
X  volatile const  uint32_t ADR;                      
N  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
X  volatile const  uint32_t MMFR[4];                  
N  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
X  volatile const  uint32_t ISAR[5];                  
N       uint32_t RESERVED0[5];
N  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
X  volatile uint32_t CPACR;                    
N} SCB_Type;
N
N/* SCB CPUID Register Definitions */
N#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
N#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
N
N#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
N#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
N
N#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
N#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
N
N#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
N#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
N
N#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
N#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
N
N/* SCB Interrupt Control State Register Definitions */
N#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
N#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
N
N#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
N#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
N
N#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
N#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
N
N#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
N#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
N
N#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
N#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
N
N#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
N#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
N
N#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
N#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
N
N#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
N#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
N
N#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
N#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
N
N#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
N#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
N
N/* SCB Vector Table Offset Register Definitions */
N#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
N#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
N
N/* SCB Application Interrupt and Reset Control Register Definitions */
N#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
N#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
N
N#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
N#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
N
N#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
N#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
N
N#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
N#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
N
N#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
N#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
N
N#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
N#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
N
N#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
N#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
N
N/* SCB System Control Register Definitions */
N#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
N#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
N
N#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
N#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
N
N#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
N#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
N
N/* SCB Configuration Control Register Definitions */
N#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
N#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
N
N#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
N#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
N
N#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
N#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
N
N#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
N#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
N
N#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
N#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
N
N#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
N#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
N
N/* SCB System Handler Control and State Register Definitions */
N#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
N#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
N
N#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
N#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
N
N#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
N#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
N
N#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
N#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
N
N#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
N#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
N
N#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
N#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
N
N#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
N#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
N
N#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
N#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
N
N#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
N#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
N
N#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
N#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
N
N#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
N#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
N
N#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
N#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
N
N#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
N#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
N
N#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
N#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
N
N/* SCB Configurable Fault Status Registers Definitions */
N#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
N#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
N
N#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
N#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
N
N#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
N#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
N
N/* SCB Hard Fault Status Registers Definitions */
N#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
N#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
N
N#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
N#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
N
N#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
N#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
N
N/* SCB Debug Fault Status Register Definitions */
N#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
N#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
N
N#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
N#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
N
N#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
N#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
N
N#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
N#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
N
N#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
N#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
N
N/*@} end of group CMSIS_SCB */
N
N
N/** \ingroup  CMSIS_core_register
N    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
N    \brief      Type definitions for the System Control and ID Register not in the SCB
N  @{
N */
N
N/** \brief  Structure type to access the System Control and ID Register not in the SCB.
N */
Ntypedef struct
N{
N       uint32_t RESERVED0[1];
N  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
X  volatile const  uint32_t ICTR;                     
N  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
X  volatile uint32_t ACTLR;                    
N} SCnSCB_Type;
N
N/* Interrupt Controller Type Register Definitions */
N#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
N#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
N
N/* Auxiliary Control Register Definitions */
N#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
N#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
N
N#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
N#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
N
N#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
N#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
N
N#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
N#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
N
N#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
N#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
N
N/*@} end of group CMSIS_SCnotSCB */
N
N
N/** \ingroup  CMSIS_core_register
N    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
N    \brief      Type definitions for the System Timer Registers.
N  @{
N */
N
N/** \brief  Structure type to access the System Timer (SysTick).
N */
Ntypedef struct
N{
N  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
X  volatile uint32_t CTRL;                     
N  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
X  volatile uint32_t LOAD;                     
N  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
X  volatile uint32_t VAL;                      
N  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
X  volatile const  uint32_t CALIB;                    
N} SysTick_Type;
N
N/* SysTick Control / Status Register Definitions */
N#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
N#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
N
N#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
N#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
N
N#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
N#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
N
N#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
N#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
N
N/* SysTick Reload Register Definitions */
N#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
N#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
N
N/* SysTick Current Register Definitions */
N#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
N#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
N
N/* SysTick Calibration Register Definitions */
N#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
N#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
N
N#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
N#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
N
N#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
N#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
N
N/*@} end of group CMSIS_SysTick */
N
N
N/** \ingroup  CMSIS_core_register
N    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
N    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
N  @{
N */
N
N/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
N */
Ntypedef struct
N{
N  __O  union
X  volatile  union
N  {
N    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
X    volatile  uint8_t    u8;                   
N    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
X    volatile  uint16_t   u16;                  
N    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
X    volatile  uint32_t   u32;                  
N  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
N       uint32_t RESERVED0[864];
N  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
X  volatile uint32_t TER;                      
N       uint32_t RESERVED1[15];
N  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
X  volatile uint32_t TPR;                      
N       uint32_t RESERVED2[15];
N  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
X  volatile uint32_t TCR;                      
N       uint32_t RESERVED3[29];
N  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
X  volatile  uint32_t IWR;                      
N  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
X  volatile const  uint32_t IRR;                      
N  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
X  volatile uint32_t IMCR;                     
N       uint32_t RESERVED4[43];
N  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
X  volatile  uint32_t LAR;                      
N  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
X  volatile const  uint32_t LSR;                      
N       uint32_t RESERVED5[6];
N  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
X  volatile const  uint32_t PID4;                     
N  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
X  volatile const  uint32_t PID5;                     
N  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
X  volatile const  uint32_t PID6;                     
N  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
X  volatile const  uint32_t PID7;                     
N  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
X  volatile const  uint32_t PID0;                     
N  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
X  volatile const  uint32_t PID1;                     
N  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
X  volatile const  uint32_t PID2;                     
N  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
X  volatile const  uint32_t PID3;                     
N  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
X  volatile const  uint32_t CID0;                     
N  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
X  volatile const  uint32_t CID1;                     
N  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
X  volatile const  uint32_t CID2;                     
N  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
X  volatile const  uint32_t CID3;                     
N} ITM_Type;
N
N/* ITM Trace Privilege Register Definitions */
N#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
N#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
N
N/* ITM Trace Control Register Definitions */
N#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
N#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
N
N#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
N#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
N
N#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
N#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
N
N#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
N#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
N
N#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
N#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
N
N#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
N#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
N
N#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
N#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
N
N#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
N#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
N
N#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
N#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
N
N/* ITM Integration Write Register Definitions */
N#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
N#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
N
N/* ITM Integration Read Register Definitions */
N#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
N#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
N
N/* ITM Integration Mode Control Register Definitions */
N#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
N#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
N
N/* ITM Lock Status Register Definitions */
N#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
N#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
N
N#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
N#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
N
N#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
N#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
N
N/*@}*/ /* end of group CMSIS_ITM */
N
N
N/** \ingroup  CMSIS_core_register
N    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
N    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
N  @{
N */
N
N/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
N */
Ntypedef struct
N{
N  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
X  volatile uint32_t CTRL;                     
N  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
X  volatile uint32_t CYCCNT;                   
N  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
X  volatile uint32_t CPICNT;                   
N  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
X  volatile uint32_t EXCCNT;                   
N  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
X  volatile uint32_t SLEEPCNT;                 
N  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
X  volatile uint32_t LSUCNT;                   
N  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
X  volatile uint32_t FOLDCNT;                  
N  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
X  volatile const  uint32_t PCSR;                     
N  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
X  volatile uint32_t COMP0;                    
N  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
X  volatile uint32_t MASK0;                    
N  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
X  volatile uint32_t FUNCTION0;                
N       uint32_t RESERVED0[1];
N  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
X  volatile uint32_t COMP1;                    
N  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
X  volatile uint32_t MASK1;                    
N  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
X  volatile uint32_t FUNCTION1;                
N       uint32_t RESERVED1[1];
N  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
X  volatile uint32_t COMP2;                    
N  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
X  volatile uint32_t MASK2;                    
N  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
X  volatile uint32_t FUNCTION2;                
N       uint32_t RESERVED2[1];
N  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
X  volatile uint32_t COMP3;                    
N  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
X  volatile uint32_t MASK3;                    
N  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
X  volatile uint32_t FUNCTION3;                
N} DWT_Type;
N
N/* DWT Control Register Definitions */
N#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
N#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
N
N#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
N#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
N
N#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
N#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
N
N#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
N#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
N
N#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
N#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
N
N#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
N#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
N
N#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
N#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
N
N#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
N#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
N
N#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
N#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
N
N#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
N#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
N
N#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
N#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
N
N#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
N#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
N
N#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
N#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
N
N#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
N#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
N
N#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
N#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
N
N#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
N#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
N
N#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
N#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
N
N#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
N#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
N
N/* DWT CPI Count Register Definitions */
N#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
N#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
N
N/* DWT Exception Overhead Count Register Definitions */
N#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
N#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
N
N/* DWT Sleep Count Register Definitions */
N#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
N#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
N
N/* DWT LSU Count Register Definitions */
N#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
N#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
N
N/* DWT Folded-instruction Count Register Definitions */
N#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
N#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
N
N/* DWT Comparator Mask Register Definitions */
N#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
N#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
N
N/* DWT Comparator Function Register Definitions */
N#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
N#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
N
N#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
N#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
N
N#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
N#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
N
N#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
N#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
N
N#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
N#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
N
N#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
N#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
N
N#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
N#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
N
N#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
N#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
N
N#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
N#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
N
N/*@}*/ /* end of group CMSIS_DWT */
N
N
N/** \ingroup  CMSIS_core_register
N    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
N    \brief      Type definitions for the Trace Port Interface (TPI)
N  @{
N */
N
N/** \brief  Structure type to access the Trace Port Interface Register (TPI).
N */
Ntypedef struct
N{
N  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
X  volatile uint32_t SSPSR;                    
N  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
X  volatile uint32_t CSPSR;                    
N       uint32_t RESERVED0[2];
N  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
X  volatile uint32_t ACPR;                     
N       uint32_t RESERVED1[55];
N  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
X  volatile uint32_t SPPR;                     
N       uint32_t RESERVED2[131];
N  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
X  volatile const  uint32_t FFSR;                     
N  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
X  volatile uint32_t FFCR;                     
N  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
X  volatile const  uint32_t FSCR;                     
N       uint32_t RESERVED3[759];
N  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
X  volatile const  uint32_t TRIGGER;                  
N  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
X  volatile const  uint32_t FIFO0;                    
N  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
X  volatile const  uint32_t ITATBCTR2;                
N       uint32_t RESERVED4[1];
N  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
X  volatile const  uint32_t ITATBCTR0;                
N  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
X  volatile const  uint32_t FIFO1;                    
N  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
X  volatile uint32_t ITCTRL;                   
N       uint32_t RESERVED5[39];
N  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
X  volatile uint32_t CLAIMSET;                 
N  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
X  volatile uint32_t CLAIMCLR;                 
N       uint32_t RESERVED7[8];
N  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
X  volatile const  uint32_t DEVID;                    
N  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
X  volatile const  uint32_t DEVTYPE;                  
N} TPI_Type;
N
N/* TPI Asynchronous Clock Prescaler Register Definitions */
N#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
N#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
N
N/* TPI Selected Pin Protocol Register Definitions */
N#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
N#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
N
N/* TPI Formatter and Flush Status Register Definitions */
N#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
N#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
N
N#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
N#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
N
N#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
N#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
N
N#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
N#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
N
N/* TPI Formatter and Flush Control Register Definitions */
N#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
N#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
N
N#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
N#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
N
N/* TPI TRIGGER Register Definitions */
N#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
N#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
N
N/* TPI Integration ETM Data Register Definitions (FIFO0) */
N#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
N#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
N
N#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
N#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
N
N#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
N#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
N
N#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
N#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
N
N#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
N#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
N
N#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
N#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
N
N#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
N#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
N
N/* TPI ITATBCTR2 Register Definitions */
N#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
N#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
N
N/* TPI Integration ITM Data Register Definitions (FIFO1) */
N#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
N#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
N
N#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
N#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
N
N#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
N#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
N
N#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
N#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
N
N#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
N#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
N
N#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
N#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
N
N#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
N#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
N
N/* TPI ITATBCTR0 Register Definitions */
N#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
N#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
N
N/* TPI Integration Mode Control Register Definitions */
N#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
N#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
N
N/* TPI DEVID Register Definitions */
N#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
N#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
N
N#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
N#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
N
N#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
N#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
N
N#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
N#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
N
N#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
N#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
N
N#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
N#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
N
N/* TPI DEVTYPE Register Definitions */
N#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
N#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
N
N#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
N#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
N
N/*@}*/ /* end of group CMSIS_TPI */
N
N
N#if (__MPU_PRESENT == 1)
X#if (1 == 1)
N/** \ingroup  CMSIS_core_register
N    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
N    \brief      Type definitions for the Memory Protection Unit (MPU)
N  @{
N */
N
N/** \brief  Structure type to access the Memory Protection Unit (MPU).
N */
Ntypedef struct
N{
N  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
X  volatile const  uint32_t TYPE;                     
N  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
X  volatile uint32_t CTRL;                     
N  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
X  volatile uint32_t RNR;                      
N  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
X  volatile uint32_t RBAR;                     
N  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
X  volatile uint32_t RASR;                     
N  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
X  volatile uint32_t RBAR_A1;                  
N  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
X  volatile uint32_t RASR_A1;                  
N  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
X  volatile uint32_t RBAR_A2;                  
N  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
X  volatile uint32_t RASR_A2;                  
N  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
X  volatile uint32_t RBAR_A3;                  
N  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
X  volatile uint32_t RASR_A3;                  
N} MPU_Type;
N
N/* MPU Type Register */
N#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
N#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
N
N#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
N#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
N
N#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
N#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
N
N/* MPU Control Register */
N#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
N#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
N
N#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
N#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
N
N#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
N#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
N
N/* MPU Region Number Register */
N#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
N#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
N
N/* MPU Region Base Address Register */
N#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
N#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
N
N#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
N#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
N
N#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
N#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
N
N/* MPU Region Attribute and Size Register */
N#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
N#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
N
N#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
N#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
N
N#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
N#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
N
N#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
N#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
N
N#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
N#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
N
N#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
N#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
N
N#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
N#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
N
N#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
N#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
N
N#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
N#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
N
N#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
N#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
N
N/*@} end of group CMSIS_MPU */
N#endif
N
N
N#if (__FPU_PRESENT == 1)
X#if (1 == 1)
N/** \ingroup  CMSIS_core_register
N    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
N    \brief      Type definitions for the Floating Point Unit (FPU)
N  @{
N */
N
N/** \brief  Structure type to access the Floating Point Unit (FPU).
N */
Ntypedef struct
N{
N       uint32_t RESERVED0[1];
N  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
X  volatile uint32_t FPCCR;                    
N  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
X  volatile uint32_t FPCAR;                    
N  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
X  volatile uint32_t FPDSCR;                   
N  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
X  volatile const  uint32_t MVFR0;                    
N  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
X  volatile const  uint32_t MVFR1;                    
N} FPU_Type;
N
N/* Floating-Point Context Control Register */
N#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
N#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
N
N#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
N#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
N
N#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
N#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
N
N#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
N#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
N
N#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
N#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
N
N#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
N#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
N
N#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
N#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
N
N#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
N#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
N
N#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
N#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
N
N/* Floating-Point Context Address Register */
N#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
N#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
N
N/* Floating-Point Default Status Control Register */
N#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
N#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
N
N#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
N#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
N
N#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
N#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
N
N#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
N#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
N
N/* Media and FP Feature Register 0 */
N#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
N#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
N
N#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
N#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
N
N#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
N#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
N
N#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
N#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
N
N#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
N#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
N
N#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
N#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
N
N#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
N#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
N
N#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
N#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
N
N/* Media and FP Feature Register 1 */
N#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
N#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
N
N#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
N#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
N
N#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
N#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
N
N#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
N#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
N
N/*@} end of group CMSIS_FPU */
N#endif
N
N
N/** \ingroup  CMSIS_core_register
N    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
N    \brief      Type definitions for the Core Debug Registers
N  @{
N */
N
N/** \brief  Structure type to access the Core Debug Register (CoreDebug).
N */
Ntypedef struct
N{
N  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
X  volatile uint32_t DHCSR;                    
N  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
X  volatile  uint32_t DCRSR;                    
N  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
X  volatile uint32_t DCRDR;                    
N  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
X  volatile uint32_t DEMCR;                    
N} CoreDebug_Type;
N
N/* Debug Halting Control and Status Register */
N#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
N#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
N
N#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
N#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
N
N#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
N#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
N
N#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
N#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
N
N#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
N#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
N
N#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
N#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
N
N#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
N#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
N
N#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
N#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
N
N#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
N#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
N
N#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
N#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
N
N#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
N#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
N
N#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
N#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
N
N/* Debug Core Register Selector Register */
N#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
N#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
N
N#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
N#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
N
N/* Debug Exception and Monitor Control Register */
N#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
N#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
N
N#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
N#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
N
N#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
N#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
N
N#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
N#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
N
N#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
N#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
N
N#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
N#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
N
N#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
N#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
N
N#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
N#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
N
N#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
N#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
N
N#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
N#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
N
N#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
N#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
N
N#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
N#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
N
N#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
N#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
N
N/*@} end of group CMSIS_CoreDebug */
N
N
N/** \ingroup    CMSIS_core_register
N    \defgroup   CMSIS_core_base     Core Definitions
N    \brief      Definitions for base addresses, unions, and structures.
N  @{
N */
N
N/* Memory mapping of Cortex-M4 Hardware */
N#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
N#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
N#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
N#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
N#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
N#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
N#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
N#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
N
N#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
N#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
N#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
N#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
N#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
N#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
N#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
N#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
N
N#if (__MPU_PRESENT == 1)
X#if (1 == 1)
N  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
N  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
N#endif
N
N#if (__FPU_PRESENT == 1)
X#if (1 == 1)
N  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
N  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
N#endif
N
N/*@} */
N
N
N
N/*******************************************************************************
N *                Hardware Abstraction Layer
N  Core Function Interface contains:
N  - Core NVIC Functions
N  - Core SysTick Functions
N  - Core Debug Functions
N  - Core Register Access Functions
N ******************************************************************************/
N/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
N*/
N
N
N
N/* ##########################   NVIC functions  #################################### */
N/** \ingroup  CMSIS_Core_FunctionInterface
N    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
N    \brief      Functions that manage interrupts and exceptions via the NVIC.
N    @{
N */
N
N/** \brief  Set Priority Grouping
N
N  The function sets the priority grouping field using the required unlock sequence.
N  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
N  Only values from 0..7 are used.
N  In case of a conflict between priority grouping and available
N  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
N
N    \param [in]      PriorityGroup  Priority grouping field.
N */
N__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Xstatic __inline void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
N{
N  uint32_t reg_value;
N  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
N
N  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
X  reg_value  =  ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR;                                                    
N  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
X  reg_value &= ~((0xFFFFUL << 16) | (7UL << 8));              
N  reg_value  =  (reg_value                                 |
N                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
X                ((uint32_t)0x5FA << 16) |
N                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
N  SCB->AIRCR =  reg_value;
X  ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR =  reg_value;
N}
N
N
N/** \brief  Get Priority Grouping
N
N  The function reads the priority grouping field from the NVIC Interrupt Controller.
N
N    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
N */
N__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Xstatic __inline uint32_t NVIC_GetPriorityGrouping(void)
N{
N  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
X  return ((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR & (7UL << 8)) >> 8);    
N}
N
N
N/** \brief  Enable External Interrupt
N
N    The function enables a device-specific interrupt in the NVIC interrupt controller.
N
N    \param [in]      IRQn  External interrupt number. Value cannot be negative.
N */
N__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Xstatic __inline void NVIC_EnableIRQ(IRQn_Type IRQn)
N{
N/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
N  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
X  ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F));  
N}
N
N
N/** \brief  Disable External Interrupt
N
N    The function disables a device-specific interrupt in the NVIC interrupt controller.
N
N    \param [in]      IRQn  External interrupt number. Value cannot be negative.
N */
N__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Xstatic __inline void NVIC_DisableIRQ(IRQn_Type IRQn)
N{
N  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
X  ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  
N}
N
N
N/** \brief  Get Pending Interrupt
N
N    The function reads the pending register in the NVIC and returns the pending bit
N    for the specified interrupt.
N
N    \param [in]      IRQn  Interrupt number.
N
N    \return             0  Interrupt status is not pending.
N    \return             1  Interrupt status is pending.
N */
N__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Xstatic __inline uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
N{
N  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
X  return((uint32_t) ((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));  
N}
N
N
N/** \brief  Set Pending Interrupt
N
N    The function sets the pending bit of an external interrupt.
N
N    \param [in]      IRQn  Interrupt number. Value cannot be negative.
N */
N__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Xstatic __inline void NVIC_SetPendingIRQ(IRQn_Type IRQn)
N{
N  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
X  ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  
N}
N
N
N/** \brief  Clear Pending Interrupt
N
N    The function clears the pending bit of an external interrupt.
N
N    \param [in]      IRQn  External interrupt number. Value cannot be negative.
N */
N__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Xstatic __inline void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
N{
N  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
X  ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  
N}
N
N
N/** \brief  Get Active Interrupt
N
N    The function reads the active register in NVIC and returns the active bit.
N
N    \param [in]      IRQn  Interrupt number.
N
N    \return             0  Interrupt status is not active.
N    \return             1  Interrupt status is active.
N */
N__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Xstatic __inline uint32_t NVIC_GetActive(IRQn_Type IRQn)
N{
N  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
X  return((uint32_t)((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));  
N}
N
N
N/** \brief  Set Interrupt Priority
N
N    The function sets the priority of an interrupt.
N
N    \note The priority cannot be set for every core interrupt.
N
N    \param [in]      IRQn  Interrupt number.
N    \param [in]  priority  Priority to set.
N */
N__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Xstatic __inline void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
N{
N  if(IRQn < 0) {
N    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
X    ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - 4)) & 0xff); }  
N  else {
N    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
X    ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[(uint32_t)(IRQn)] = ((priority << (8 - 4)) & 0xff);    }         
N}
N
N
N/** \brief  Get Interrupt Priority
N
N    The function reads the priority of an interrupt. The interrupt
N    number can be positive to specify an external (device specific)
N    interrupt, or negative to specify an internal (core) interrupt.
N
N
N    \param [in]   IRQn  Interrupt number.
N    \return             Interrupt Priority. Value is aligned automatically to the implemented
N                        priority bits of the microcontroller.
N */
N__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Xstatic __inline uint32_t NVIC_GetPriority(IRQn_Type IRQn)
N{
N
N  if(IRQn < 0) {
N    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
X    return((uint32_t)(((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - 4)));  }  
N  else {
N    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
X    return((uint32_t)(((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[(uint32_t)(IRQn)]           >> (8 - 4)));  }  
N}
N
N
N/** \brief  Encode Priority
N
N    The function encodes the priority for an interrupt with the given priority group,
N    preemptive priority value, and subpriority value.
N    In case of a conflict between priority grouping and available
N    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
N
N    \param [in]     PriorityGroup  Used priority group.
N    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
N    \param [in]       SubPriority  Subpriority value (starting from 0).
N    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
N */
N__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Xstatic __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
N{
N  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
N  uint32_t PreemptPriorityBits;
N  uint32_t SubPriorityBits;
N
N  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
X  PreemptPriorityBits = ((7 - PriorityGroupTmp) > 4) ? 4 : 7 - PriorityGroupTmp;
N  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
X  SubPriorityBits     = ((PriorityGroupTmp + 4) < 7) ? 0 : PriorityGroupTmp - 7 + 4;
N
N  return (
N           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
N           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
N         );
N}
N
N
N/** \brief  Decode Priority
N
N    The function decodes an interrupt priority value with a given priority group to
N    preemptive priority value and subpriority value.
N    In case of a conflict between priority grouping and available
N    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
N
N    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
N    \param [in]     PriorityGroup  Used priority group.
N    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
N    \param [out]     pSubPriority  Subpriority value (starting from 0).
N */
N__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Xstatic __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
N{
N  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
N  uint32_t PreemptPriorityBits;
N  uint32_t SubPriorityBits;
N
N  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
X  PreemptPriorityBits = ((7 - PriorityGroupTmp) > 4) ? 4 : 7 - PriorityGroupTmp;
N  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
X  SubPriorityBits     = ((PriorityGroupTmp + 4) < 7) ? 0 : PriorityGroupTmp - 7 + 4;
N
N  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
N  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
N}
N
N
N/** \brief  System Reset
N
N    The function initiates a system reset request to reset the MCU.
N */
N__STATIC_INLINE void NVIC_SystemReset(void)
Xstatic __inline void NVIC_SystemReset(void)
N{
N  __DSB();                                                     /* Ensure all outstanding memory accesses included
X  __dsb(0xF);                                                     
N                                                                  buffered write are completed before reset */
N  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
X  ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR  = ((0x5FA << 16)      |
N                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
X                 (((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR & (7UL << 8)) |
N                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
X                 (1UL << 2));                    
N  __DSB();                                                     /* Ensure completion of memory access */
X  __dsb(0xF);                                                      
N  while(1);                                                    /* wait until reset */
N}
N
N/*@} end of CMSIS_Core_NVICFunctions */
N
N
N
N/* ##################################    SysTick function  ############################################ */
N/** \ingroup  CMSIS_Core_FunctionInterface
N    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
N    \brief      Functions that configure the System.
N  @{
N */
N
N#if (__Vendor_SysTickConfig == 0)
X#if (0 == 0)
N
N/** \brief  System Tick Configuration
N
N    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
N    Counter is in free running mode to generate periodic interrupts.
N
N    \param [in]  ticks  Number of ticks between two interrupts.
N
N    \return          0  Function succeeded.
N    \return          1  Function failed.
N
N    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
N    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
N    must contain a vendor-specific implementation of this function.
N
N */
N__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Xstatic __inline uint32_t SysTick_Config(uint32_t ticks)
N{
N  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
X  if ((ticks - 1) > (0xFFFFFFUL << 0))  return (1);       
N
N  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
X  ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD  = ticks - 1;                                   
N  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
X  NVIC_SetPriority (SysTick_IRQn, (1<<4) - 1);   
N  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
X  ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL   = 0;                                           
N  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
X  ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL  = (1UL << 2) |
N                   SysTick_CTRL_TICKINT_Msk   |
X                   (1UL << 1)   |
N                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
X                   (1UL << 0);                     
N  return (0);                                                  /* Function successful */
N}
N
N#endif
N
N/*@} end of CMSIS_Core_SysTickFunctions */
N
N
N
N/* ##################################### Debug In/Output function ########################################### */
N/** \ingroup  CMSIS_Core_FunctionInterface
N    \defgroup CMSIS_core_DebugFunctions ITM Functions
N    \brief   Functions that access the ITM debug interface.
N  @{
N */
N
Nextern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
N#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
N
N
N/** \brief  ITM Send Character
N
N    The function transmits a character via the ITM channel 0, and
N    \li Just returns when no debugger is connected that has booked the output.
N    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
N
N    \param [in]     ch  Character to transmit.
N
N    \returns            Character to transmit.
N */
N__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Xstatic __inline uint32_t ITM_SendChar (uint32_t ch)
N{
N  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
X  if ((((ITM_Type *) (0xE0000000UL) )->TCR & (1UL << 0))                  &&       
N      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
X      (((ITM_Type *) (0xE0000000UL) )->TER & (1UL << 0)        )                    )      
N  {
N    while (ITM->PORT[0].u32 == 0);
X    while (((ITM_Type *) (0xE0000000UL) )->PORT[0].u32 == 0);
N    ITM->PORT[0].u8 = (uint8_t) ch;
X    ((ITM_Type *) (0xE0000000UL) )->PORT[0].u8 = (uint8_t) ch;
N  }
N  return (ch);
N}
N
N
N/** \brief  ITM Receive Character
N
N    The function inputs a character via the external variable \ref ITM_RxBuffer.
N
N    \return             Received character.
N    \return         -1  No character pending.
N */
N__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Xstatic __inline int32_t ITM_ReceiveChar (void) {
N  int32_t ch = -1;                           /* no character available */
N
N  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
X  if (ITM_RxBuffer != 0x5AA55AA5) {
N    ch = ITM_RxBuffer;
N    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
X    ITM_RxBuffer = 0x5AA55AA5;        
N  }
N
N  return (ch);
N}
N
N
N/** \brief  ITM Check Character
N
N    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
N
N    \return          0  No character available.
N    \return          1  Character available.
N */
N__STATIC_INLINE int32_t ITM_CheckChar (void) {
Xstatic __inline int32_t ITM_CheckChar (void) {
N
N  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
X  if (ITM_RxBuffer == 0x5AA55AA5) {
N    return (0);                                 /* no character available */
N  } else {
N    return (1);                                 /*    character available */
N  }
N}
N
N/*@} end of CMSIS_core_DebugFunctions */
N
N
N
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __CORE_CM4_H_DEPENDANT */
N
N#endif /* __CMSIS_GENERIC */
L 470 "..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h" 2
N#include "system_stm32f4xx.h"
L 1 "..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h" 1
N/**
N  ******************************************************************************
N  * @file    system_stm32f4xx.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
N  ******************************************************************************  
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************  
N  */ 
N
N/** @addtogroup CMSIS
N  * @{
N  */
N
N/** @addtogroup stm32f4xx_system
N  * @{
N  */  
N  
N/**
N  * @brief Define to prevent recursive inclusion
N  */
N#ifndef __SYSTEM_STM32F4XX_H
N#define __SYSTEM_STM32F4XX_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif 
N
N/** @addtogroup STM32F4xx_System_Includes
N  * @{
N  */
N
N/**
N  * @}
N  */
N
N
N/** @addtogroup STM32F4xx_System_Exported_types
N  * @{
N  */
N
Nextern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
N
N
N/**
N  * @}
N  */
N
N/** @addtogroup STM32F4xx_System_Exported_Constants
N  * @{
N  */
N
N/**
N  * @}
N  */
N
N/** @addtogroup STM32F4xx_System_Exported_Macros
N  * @{
N  */
N
N/**
N  * @}
N  */
N
N/** @addtogroup STM32F4xx_System_Exported_Functions
N  * @{
N  */
N  
Nextern void SystemInit(void);
Nextern void SystemCoreClockUpdate(void);
N/**
N  * @}
N  */
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__SYSTEM_STM32F4XX_H */
N
N/**
N  * @}
N  */
N  
N/**
N  * @}
N  */  
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 471 "..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h" 2
N#include <stdint.h>
N
N/** @addtogroup Exported_types
N  * @{
N  */  
N/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
Ntypedef int32_t  s32;
Ntypedef int16_t s16;
Ntypedef int8_t  s8;
N
Ntypedef const int32_t sc32;  /*!< Read Only */
Ntypedef const int16_t sc16;  /*!< Read Only */
Ntypedef const int8_t sc8;   /*!< Read Only */
N
Ntypedef __IO int32_t  vs32;
Xtypedef volatile int32_t  vs32;
Ntypedef __IO int16_t  vs16;
Xtypedef volatile int16_t  vs16;
Ntypedef __IO int8_t   vs8;
Xtypedef volatile int8_t   vs8;
N
Ntypedef __I int32_t vsc32;  /*!< Read Only */
Xtypedef volatile const int32_t vsc32;   
Ntypedef __I int16_t vsc16;  /*!< Read Only */
Xtypedef volatile const int16_t vsc16;   
Ntypedef __I int8_t vsc8;   /*!< Read Only */
Xtypedef volatile const int8_t vsc8;    
N
Ntypedef uint32_t  u32;
Ntypedef uint16_t u16;
Ntypedef uint8_t  u8;
N
Ntypedef const uint32_t uc32;  /*!< Read Only */
Ntypedef const uint16_t uc16;  /*!< Read Only */
Ntypedef const uint8_t uc8;   /*!< Read Only */
N
Ntypedef __IO uint32_t  vu32;
Xtypedef volatile uint32_t  vu32;
Ntypedef __IO uint16_t vu16;
Xtypedef volatile uint16_t vu16;
Ntypedef __IO uint8_t  vu8;
Xtypedef volatile uint8_t  vu8;
N
Ntypedef __I uint32_t vuc32;  /*!< Read Only */
Xtypedef volatile const uint32_t vuc32;   
Ntypedef __I uint16_t vuc16;  /*!< Read Only */
Xtypedef volatile const uint16_t vuc16;   
Ntypedef __I uint8_t vuc8;   /*!< Read Only */
Xtypedef volatile const uint8_t vuc8;    
N
Ntypedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
N
Ntypedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
N#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
N
Ntypedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
N
N/**
N  * @}
N  */
N
N/** @addtogroup Peripheral_registers_structures
N  * @{
N  */   
N
N/** 
N  * @brief Analog to Digital Converter  
N  */
N
Ntypedef struct
N{
N  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
X  volatile uint32_t SR;      
N  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
X  volatile uint32_t CR1;           
N  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
X  volatile uint32_t CR2;     
N  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
X  volatile uint32_t SMPR1;   
N  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
X  volatile uint32_t SMPR2;   
N  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
X  volatile uint32_t JOFR1;   
N  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
X  volatile uint32_t JOFR2;   
N  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
X  volatile uint32_t JOFR3;   
N  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
X  volatile uint32_t JOFR4;   
N  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
X  volatile uint32_t HTR;     
N  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
X  volatile uint32_t LTR;     
N  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
X  volatile uint32_t SQR1;    
N  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
X  volatile uint32_t SQR2;    
N  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
X  volatile uint32_t SQR3;    
N  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
X  volatile uint32_t JSQR;    
N  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
X  volatile uint32_t JDR1;    
N  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
X  volatile uint32_t JDR2;    
N  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
X  volatile uint32_t JDR3;    
N  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
X  volatile uint32_t JDR4;    
N  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
X  volatile uint32_t DR;      
N} ADC_TypeDef;
N
Ntypedef struct
N{
N  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
X  volatile uint32_t CSR;     
N  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
X  volatile uint32_t CCR;     
N  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
X  volatile uint32_t CDR;    
N                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
N} ADC_Common_TypeDef;
N
N
N/** 
N  * @brief Controller Area Network TxMailBox 
N  */
N
Ntypedef struct
N{
N  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
X  volatile uint32_t TIR;   
N  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
X  volatile uint32_t TDTR;  
N  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
X  volatile uint32_t TDLR;  
N  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
X  volatile uint32_t TDHR;  
N} CAN_TxMailBox_TypeDef;
N
N/** 
N  * @brief Controller Area Network FIFOMailBox 
N  */
N  
Ntypedef struct
N{
N  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
X  volatile uint32_t RIR;   
N  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
X  volatile uint32_t RDTR;  
N  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
X  volatile uint32_t RDLR;  
N  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
X  volatile uint32_t RDHR;  
N} CAN_FIFOMailBox_TypeDef;
N
N/** 
N  * @brief Controller Area Network FilterRegister 
N  */
N  
Ntypedef struct
N{
N  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
X  volatile uint32_t FR1;  
N  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
X  volatile uint32_t FR2;  
N} CAN_FilterRegister_TypeDef;
N
N/** 
N  * @brief Controller Area Network 
N  */
N  
Ntypedef struct
N{
N  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
X  volatile uint32_t              MCR;                  
N  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
X  volatile uint32_t              MSR;                  
N  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
X  volatile uint32_t              TSR;                  
N  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
X  volatile uint32_t              RF0R;                 
N  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
X  volatile uint32_t              RF1R;                 
N  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
X  volatile uint32_t              IER;                  
N  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
X  volatile uint32_t              ESR;                  
N  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
X  volatile uint32_t              BTR;                  
N  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
N  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
N  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
N  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
N  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
X  volatile uint32_t              FMR;                  
N  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
X  volatile uint32_t              FM1R;                 
N  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
N  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
X  volatile uint32_t              FS1R;                 
N  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
N  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
X  volatile uint32_t              FFA1R;                
N  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
N  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
X  volatile uint32_t              FA1R;                 
N  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
N  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
N} CAN_TypeDef;
N
N/** 
N  * @brief CRC calculation unit 
N  */
N
Ntypedef struct
N{
N  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
X  volatile uint32_t DR;          
N  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
X  volatile uint8_t  IDR;         
N  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
N  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
N  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
X  volatile uint32_t CR;          
N} CRC_TypeDef;
N
N/** 
N  * @brief Digital to Analog Converter
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
X  volatile uint32_t CR;        
N  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
X  volatile uint32_t SWTRIGR;   
N  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
X  volatile uint32_t DHR12R1;   
N  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
X  volatile uint32_t DHR12L1;   
N  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
X  volatile uint32_t DHR8R1;    
N  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
X  volatile uint32_t DHR12R2;   
N  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
X  volatile uint32_t DHR12L2;   
N  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
X  volatile uint32_t DHR8R2;    
N  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
X  volatile uint32_t DHR12RD;   
N  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
X  volatile uint32_t DHR12LD;   
N  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
X  volatile uint32_t DHR8RD;    
N  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
X  volatile uint32_t DOR1;      
N  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
X  volatile uint32_t DOR2;      
N  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
X  volatile uint32_t SR;        
N} DAC_TypeDef;
N
N/** 
N  * @brief Debug MCU
N  */
N
Ntypedef struct
N{
N  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
X  volatile uint32_t IDCODE;   
N  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
X  volatile uint32_t CR;       
N  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
X  volatile uint32_t APB1FZ;   
N  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
X  volatile uint32_t APB2FZ;   
N}DBGMCU_TypeDef;
N
N/** 
N  * @brief DCMI
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
X  volatile uint32_t CR;        
N  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
X  volatile uint32_t SR;        
N  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
X  volatile uint32_t RISR;      
N  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
X  volatile uint32_t IER;       
N  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
X  volatile uint32_t MISR;      
N  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
X  volatile uint32_t ICR;       
N  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
X  volatile uint32_t ESCR;      
N  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
X  volatile uint32_t ESUR;      
N  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
X  volatile uint32_t CWSTRTR;   
N  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
X  volatile uint32_t CWSIZER;   
N  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
X  volatile uint32_t DR;        
N} DCMI_TypeDef;
N
N/** 
N  * @brief DMA Controller
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
X  volatile uint32_t CR;      
N  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
X  volatile uint32_t NDTR;    
N  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
X  volatile uint32_t PAR;     
N  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
X  volatile uint32_t M0AR;    
N  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
X  volatile uint32_t M1AR;    
N  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
X  volatile uint32_t FCR;     
N} DMA_Stream_TypeDef;
N
Ntypedef struct
N{
N  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
X  volatile uint32_t LISR;    
N  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
X  volatile uint32_t HISR;    
N  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
X  volatile uint32_t LIFCR;   
N  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
X  volatile uint32_t HIFCR;   
N} DMA_TypeDef;
N 
N/** 
N  * @brief DMA2D Controller
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
X  volatile uint32_t CR;             
N  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
X  volatile uint32_t ISR;            
N  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
X  volatile uint32_t IFCR;           
N  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
X  volatile uint32_t FGMAR;          
N  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
X  volatile uint32_t FGOR;           
N  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
X  volatile uint32_t BGMAR;          
N  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
X  volatile uint32_t BGOR;           
N  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
X  volatile uint32_t FGPFCCR;        
N  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
X  volatile uint32_t FGCOLR;         
N  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
X  volatile uint32_t BGPFCCR;        
N  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
X  volatile uint32_t BGCOLR;         
N  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
X  volatile uint32_t FGCMAR;         
N  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
X  volatile uint32_t BGCMAR;         
N  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
X  volatile uint32_t OPFCCR;         
N  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
X  volatile uint32_t OCOLR;          
N  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
X  volatile uint32_t OMAR;           
N  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
X  volatile uint32_t OOR;            
N  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
X  volatile uint32_t NLR;            
N  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
X  volatile uint32_t LWR;            
N  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
X  volatile uint32_t AMTCR;          
N  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
N  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
X  volatile uint32_t FGCLUT[256];    
N  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
X  volatile uint32_t BGCLUT[256];    
N} DMA2D_TypeDef;
N
N/** 
N  * @brief Ethernet MAC
N  */
N
Ntypedef struct
N{
N  __IO uint32_t MACCR;
X  volatile uint32_t MACCR;
N  __IO uint32_t MACFFR;
X  volatile uint32_t MACFFR;
N  __IO uint32_t MACHTHR;
X  volatile uint32_t MACHTHR;
N  __IO uint32_t MACHTLR;
X  volatile uint32_t MACHTLR;
N  __IO uint32_t MACMIIAR;
X  volatile uint32_t MACMIIAR;
N  __IO uint32_t MACMIIDR;
X  volatile uint32_t MACMIIDR;
N  __IO uint32_t MACFCR;
X  volatile uint32_t MACFCR;
N  __IO uint32_t MACVLANTR;             /*    8 */
X  volatile uint32_t MACVLANTR;              
N  uint32_t      RESERVED0[2];
N  __IO uint32_t MACRWUFFR;             /*   11 */
X  volatile uint32_t MACRWUFFR;              
N  __IO uint32_t MACPMTCSR;
X  volatile uint32_t MACPMTCSR;
N  uint32_t      RESERVED1[2];
N  __IO uint32_t MACSR;                 /*   15 */
X  volatile uint32_t MACSR;                  
N  __IO uint32_t MACIMR;
X  volatile uint32_t MACIMR;
N  __IO uint32_t MACA0HR;
X  volatile uint32_t MACA0HR;
N  __IO uint32_t MACA0LR;
X  volatile uint32_t MACA0LR;
N  __IO uint32_t MACA1HR;
X  volatile uint32_t MACA1HR;
N  __IO uint32_t MACA1LR;
X  volatile uint32_t MACA1LR;
N  __IO uint32_t MACA2HR;
X  volatile uint32_t MACA2HR;
N  __IO uint32_t MACA2LR;
X  volatile uint32_t MACA2LR;
N  __IO uint32_t MACA3HR;
X  volatile uint32_t MACA3HR;
N  __IO uint32_t MACA3LR;               /*   24 */
X  volatile uint32_t MACA3LR;                
N  uint32_t      RESERVED2[40];
N  __IO uint32_t MMCCR;                 /*   65 */
X  volatile uint32_t MMCCR;                  
N  __IO uint32_t MMCRIR;
X  volatile uint32_t MMCRIR;
N  __IO uint32_t MMCTIR;
X  volatile uint32_t MMCTIR;
N  __IO uint32_t MMCRIMR;
X  volatile uint32_t MMCRIMR;
N  __IO uint32_t MMCTIMR;               /*   69 */
X  volatile uint32_t MMCTIMR;                
N  uint32_t      RESERVED3[14];
N  __IO uint32_t MMCTGFSCCR;            /*   84 */
X  volatile uint32_t MMCTGFSCCR;             
N  __IO uint32_t MMCTGFMSCCR;
X  volatile uint32_t MMCTGFMSCCR;
N  uint32_t      RESERVED4[5];
N  __IO uint32_t MMCTGFCR;
X  volatile uint32_t MMCTGFCR;
N  uint32_t      RESERVED5[10];
N  __IO uint32_t MMCRFCECR;
X  volatile uint32_t MMCRFCECR;
N  __IO uint32_t MMCRFAECR;
X  volatile uint32_t MMCRFAECR;
N  uint32_t      RESERVED6[10];
N  __IO uint32_t MMCRGUFCR;
X  volatile uint32_t MMCRGUFCR;
N  uint32_t      RESERVED7[334];
N  __IO uint32_t PTPTSCR;
X  volatile uint32_t PTPTSCR;
N  __IO uint32_t PTPSSIR;
X  volatile uint32_t PTPSSIR;
N  __IO uint32_t PTPTSHR;
X  volatile uint32_t PTPTSHR;
N  __IO uint32_t PTPTSLR;
X  volatile uint32_t PTPTSLR;
N  __IO uint32_t PTPTSHUR;
X  volatile uint32_t PTPTSHUR;
N  __IO uint32_t PTPTSLUR;
X  volatile uint32_t PTPTSLUR;
N  __IO uint32_t PTPTSAR;
X  volatile uint32_t PTPTSAR;
N  __IO uint32_t PTPTTHR;
X  volatile uint32_t PTPTTHR;
N  __IO uint32_t PTPTTLR;
X  volatile uint32_t PTPTTLR;
N  __IO uint32_t RESERVED8;
X  volatile uint32_t RESERVED8;
N  __IO uint32_t PTPTSSR;
X  volatile uint32_t PTPTSSR;
N  uint32_t      RESERVED9[565];
N  __IO uint32_t DMABMR;
X  volatile uint32_t DMABMR;
N  __IO uint32_t DMATPDR;
X  volatile uint32_t DMATPDR;
N  __IO uint32_t DMARPDR;
X  volatile uint32_t DMARPDR;
N  __IO uint32_t DMARDLAR;
X  volatile uint32_t DMARDLAR;
N  __IO uint32_t DMATDLAR;
X  volatile uint32_t DMATDLAR;
N  __IO uint32_t DMASR;
X  volatile uint32_t DMASR;
N  __IO uint32_t DMAOMR;
X  volatile uint32_t DMAOMR;
N  __IO uint32_t DMAIER;
X  volatile uint32_t DMAIER;
N  __IO uint32_t DMAMFBOCR;
X  volatile uint32_t DMAMFBOCR;
N  __IO uint32_t DMARSWTR;
X  volatile uint32_t DMARSWTR;
N  uint32_t      RESERVED10[8];
N  __IO uint32_t DMACHTDR;
X  volatile uint32_t DMACHTDR;
N  __IO uint32_t DMACHRDR;
X  volatile uint32_t DMACHRDR;
N  __IO uint32_t DMACHTBAR;
X  volatile uint32_t DMACHTBAR;
N  __IO uint32_t DMACHRBAR;
X  volatile uint32_t DMACHRBAR;
N} ETH_TypeDef;
N
N/** 
N  * @brief External Interrupt/Event Controller
N  */
N
Ntypedef struct
N{
N  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
X  volatile uint32_t IMR;     
N  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
X  volatile uint32_t EMR;     
N  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
X  volatile uint32_t RTSR;    
N  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
X  volatile uint32_t FTSR;    
N  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
X  volatile uint32_t SWIER;   
N  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
X  volatile uint32_t PR;      
N} EXTI_TypeDef;
N
N/** 
N  * @brief FLASH Registers
N  */
N
Ntypedef struct
N{
N  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
X  volatile uint32_t ACR;       
N  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
X  volatile uint32_t KEYR;      
N  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
X  volatile uint32_t OPTKEYR;   
N  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
X  volatile uint32_t SR;        
N  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
X  volatile uint32_t CR;        
N  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
X  volatile uint32_t OPTCR;     
N  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
X  volatile uint32_t OPTCR1;    
N} FLASH_TypeDef;
N
N#if defined (STM32F40_41xxx)
X#if 1L
N/** 
N  * @brief Flexible Static Memory Controller
N  */
N
Ntypedef struct
N{
N  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
X  volatile uint32_t BTCR[8];        
N} FSMC_Bank1_TypeDef; 
N
N/** 
N  * @brief Flexible Static Memory Controller Bank1E
N  */
N  
Ntypedef struct
N{
N  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
X  volatile uint32_t BWTR[7];     
N} FSMC_Bank1E_TypeDef;
N
N/** 
N  * @brief Flexible Static Memory Controller Bank2
N  */
N  
Ntypedef struct
N{
N  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
X  volatile uint32_t PCR2;        
N  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
X  volatile uint32_t SR2;         
N  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
X  volatile uint32_t PMEM2;       
N  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
X  volatile uint32_t PATT2;       
N  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
N  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
X  volatile uint32_t ECCR2;       
N} FSMC_Bank2_TypeDef;
N
N/** 
N  * @brief Flexible Static Memory Controller Bank3
N  */
N  
Ntypedef struct
N{
N  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
X  volatile uint32_t PCR3;        
N  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
X  volatile uint32_t SR3;         
N  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
X  volatile uint32_t PMEM3;       
N  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
X  volatile uint32_t PATT3;       
N  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
N  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
X  volatile uint32_t ECCR3;       
N} FSMC_Bank3_TypeDef;
N
N/** 
N  * @brief Flexible Static Memory Controller Bank4
N  */
N  
Ntypedef struct
N{
N  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
X  volatile uint32_t PCR4;        
N  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
X  volatile uint32_t SR4;         
N  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
X  volatile uint32_t PMEM4;       
N  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
X  volatile uint32_t PATT4;       
N  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
X  volatile uint32_t PIO4;        
N} FSMC_Bank4_TypeDef; 
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
X#if 0L || 0L
S/** 
S  * @brief Flexible Memory Controller
S  */
S
Stypedef struct
S{
S  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
S} FMC_Bank1_TypeDef; 
S
S/** 
S  * @brief Flexible Memory Controller Bank1E
S  */
S  
Stypedef struct
S{
S  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
S} FMC_Bank1E_TypeDef;
S
S/** 
S  * @brief Flexible Memory Controller Bank2
S  */
S  
Stypedef struct
S{
S  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
S  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
S  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
S  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
S  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
S  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
S} FMC_Bank2_TypeDef;
S
S/** 
S  * @brief Flexible Memory Controller Bank3
S  */
S  
Stypedef struct
S{
S  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
S  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
S  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
S  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
S  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
S  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
S} FMC_Bank3_TypeDef;
S
S/** 
S  * @brief Flexible Memory Controller Bank4
S  */
S  
Stypedef struct
S{
S  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
S  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
S  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
S  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
S  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
S} FMC_Bank4_TypeDef; 
S
S/** 
S  * @brief Flexible Memory Controller Bank5_6
S  */
S  
Stypedef struct
S{
S  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
S  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
S  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
S  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
S  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
S} FMC_Bank5_6_TypeDef; 
N#endif /* STM32F427_437xx ||  STM32F429_439xx */
N
N/** 
N  * @brief General Purpose I/O
N  */
N
Ntypedef struct
N{
N  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
X  volatile uint32_t MODER;     
N  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
X  volatile uint32_t OTYPER;    
N  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
X  volatile uint32_t OSPEEDR;   
N  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
X  volatile uint32_t PUPDR;     
N  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
X  volatile uint32_t IDR;       
N  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
X  volatile uint32_t ODR;       
N  __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
X  volatile uint16_t BSRRL;     
N  __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
X  volatile uint16_t BSRRH;     
N  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
X  volatile uint32_t LCKR;      
N  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
X  volatile uint32_t AFR[2];    
N} GPIO_TypeDef;
N
N/** 
N  * @brief System configuration controller
N  */
N  
Ntypedef struct
N{
N  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
X  volatile uint32_t MEMRMP;        
N  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
X  volatile uint32_t PMC;           
N  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
X  volatile uint32_t EXTICR[4];     
N  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
N  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
X  volatile uint32_t CMPCR;         
N} SYSCFG_TypeDef;
N
N/** 
N  * @brief Inter-integrated Circuit Interface
N  */
N
Ntypedef struct
N{
N  __IO uint16_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
X  volatile uint16_t CR1;         
N  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                   */
N  __IO uint16_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
X  volatile uint16_t CR2;         
N  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                   */
N  __IO uint16_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
X  volatile uint16_t OAR1;        
N  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                   */
N  __IO uint16_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
X  volatile uint16_t OAR2;        
N  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                   */
N  __IO uint16_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
X  volatile uint16_t DR;          
N  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                   */
N  __IO uint16_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
X  volatile uint16_t SR1;         
N  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                   */
N  __IO uint16_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
X  volatile uint16_t SR2;         
N  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                   */
N  __IO uint16_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
X  volatile uint16_t CCR;         
N  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                   */
N  __IO uint16_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
X  volatile uint16_t TRISE;       
N  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                   */
N  __IO uint16_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
X  volatile uint16_t FLTR;        
N  uint16_t      RESERVED9;  /*!< Reserved, 0x26                                   */
N} I2C_TypeDef;
N
N/** 
N  * @brief Independent WATCHDOG
N  */
N
Ntypedef struct
N{
N  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
X  volatile uint32_t KR;    
N  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
X  volatile uint32_t PR;    
N  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
X  volatile uint32_t RLR;   
N  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
X  volatile uint32_t SR;    
N} IWDG_TypeDef;
N
N/** 
N  * @brief LCD-TFT Display Controller
N  */
N  
Ntypedef struct
N{
N  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
N  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
X  volatile uint32_t SSCR;           
N  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
X  volatile uint32_t BPCR;           
N  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
X  volatile uint32_t AWCR;           
N  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
X  volatile uint32_t TWCR;           
N  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
X  volatile uint32_t GCR;            
N  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
N  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
X  volatile uint32_t SRCR;           
N  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
N  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
X  volatile uint32_t BCCR;           
N  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
N  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
X  volatile uint32_t IER;            
N  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
X  volatile uint32_t ISR;            
N  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
X  volatile uint32_t ICR;            
N  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
X  volatile uint32_t LIPCR;          
N  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
X  volatile uint32_t CPSR;           
N  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                       Address offset: 0x48 */
X  volatile uint32_t CDSR;          
N} LTDC_TypeDef;  
N
N/** 
N  * @brief LCD-TFT Display layer x Controller
N  */
N  
Ntypedef struct
N{  
N  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
X  volatile uint32_t CR;             
N  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
X  volatile uint32_t WHPCR;          
N  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
X  volatile uint32_t WVPCR;          
N  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
X  volatile uint32_t CKCR;           
N  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
X  volatile uint32_t PFCR;           
N  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
X  volatile uint32_t CACR;           
N  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
X  volatile uint32_t DCCR;           
N  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
X  volatile uint32_t BFCR;           
N  uint32_t      RESERVED0[2];  /*!< Reserved */
N  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
X  volatile uint32_t CFBAR;          
N  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
X  volatile uint32_t CFBLR;          
N  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
X  volatile uint32_t CFBLNR;         
N  uint32_t      RESERVED1[3];  /*!< Reserved */
N  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
X  volatile uint32_t CLUTWR;          
N
N} LTDC_Layer_TypeDef;
N
N/** 
N  * @brief Power Control
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
X  volatile uint32_t CR;    
N  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
X  volatile uint32_t CSR;   
N} PWR_TypeDef;
N
N/** 
N  * @brief Reset and Clock Control
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
X  volatile uint32_t CR;             
N  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
X  volatile uint32_t PLLCFGR;        
N  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
X  volatile uint32_t CFGR;           
N  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
X  volatile uint32_t CIR;            
N  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
X  volatile uint32_t AHB1RSTR;       
N  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
X  volatile uint32_t AHB2RSTR;       
N  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
X  volatile uint32_t AHB3RSTR;       
N  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
N  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
X  volatile uint32_t APB1RSTR;       
N  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
X  volatile uint32_t APB2RSTR;       
N  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
N  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
X  volatile uint32_t AHB1ENR;        
N  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
X  volatile uint32_t AHB2ENR;        
N  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
X  volatile uint32_t AHB3ENR;        
N  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
N  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
X  volatile uint32_t APB1ENR;        
N  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
X  volatile uint32_t APB2ENR;        
N  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
N  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
X  volatile uint32_t AHB1LPENR;      
N  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
X  volatile uint32_t AHB2LPENR;      
N  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
X  volatile uint32_t AHB3LPENR;      
N  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
N  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
X  volatile uint32_t APB1LPENR;      
N  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
X  volatile uint32_t APB2LPENR;      
N  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
N  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
X  volatile uint32_t BDCR;           
N  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
X  volatile uint32_t CSR;            
N  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
N  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
X  volatile uint32_t SSCGR;          
N  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
X  volatile uint32_t PLLI2SCFGR;     
N  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
X  volatile uint32_t PLLSAICFGR;     
N  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
X  volatile uint32_t DCKCFGR;        
N
N} RCC_TypeDef;
N
N/** 
N  * @brief Real-Time Clock
N  */
N
Ntypedef struct
N{
N  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
X  volatile uint32_t TR;       
N  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
X  volatile uint32_t DR;       
N  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
X  volatile uint32_t CR;       
N  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
X  volatile uint32_t ISR;      
N  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
X  volatile uint32_t PRER;     
N  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
X  volatile uint32_t WUTR;     
N  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
X  volatile uint32_t CALIBR;   
N  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
X  volatile uint32_t ALRMAR;   
N  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
X  volatile uint32_t ALRMBR;   
N  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
X  volatile uint32_t WPR;      
N  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
X  volatile uint32_t SSR;      
N  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
X  volatile uint32_t SHIFTR;   
N  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
X  volatile uint32_t TSTR;     
N  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
X  volatile uint32_t TSDR;     
N  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
X  volatile uint32_t TSSSR;    
N  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
X  volatile uint32_t CALR;     
N  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
X  volatile uint32_t TAFCR;    
N  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
X  volatile uint32_t ALRMASSR; 
N  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
X  volatile uint32_t ALRMBSSR; 
N  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
N  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
X  volatile uint32_t BKP0R;    
N  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
X  volatile uint32_t BKP1R;    
N  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
X  volatile uint32_t BKP2R;    
N  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
X  volatile uint32_t BKP3R;    
N  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
X  volatile uint32_t BKP4R;    
N  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
X  volatile uint32_t BKP5R;    
N  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
X  volatile uint32_t BKP6R;    
N  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
X  volatile uint32_t BKP7R;    
N  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
X  volatile uint32_t BKP8R;    
N  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
X  volatile uint32_t BKP9R;    
N  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
X  volatile uint32_t BKP10R;   
N  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
X  volatile uint32_t BKP11R;   
N  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
X  volatile uint32_t BKP12R;   
N  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
X  volatile uint32_t BKP13R;   
N  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
X  volatile uint32_t BKP14R;   
N  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
X  volatile uint32_t BKP15R;   
N  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
X  volatile uint32_t BKP16R;   
N  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
X  volatile uint32_t BKP17R;   
N  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
X  volatile uint32_t BKP18R;   
N  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
X  volatile uint32_t BKP19R;   
N} RTC_TypeDef;
N
N
N/** 
N  * @brief Serial Audio Interface
N  */
N  
Ntypedef struct
N{
N  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
X  volatile uint32_t GCR;       
N} SAI_TypeDef;
N
Ntypedef struct
N{
N  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
X  volatile uint32_t CR1;       
N  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
X  volatile uint32_t CR2;       
N  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
X  volatile uint32_t FRCR;      
N  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
X  volatile uint32_t SLOTR;     
N  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
X  volatile uint32_t IMR;       
N  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
X  volatile uint32_t SR;        
N  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
X  volatile uint32_t CLRFR;     
N  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
X  volatile uint32_t DR;        
N} SAI_Block_TypeDef;
N
N/** 
N  * @brief SD host Interface
N  */
N
Ntypedef struct
N{
N  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
X  volatile uint32_t POWER;           
N  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
X  volatile uint32_t CLKCR;           
N  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
X  volatile uint32_t ARG;             
N  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
X  volatile uint32_t CMD;             
N  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
X  volatile const uint32_t  RESPCMD;         
N  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
X  volatile const uint32_t  RESP1;           
N  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
X  volatile const uint32_t  RESP2;           
N  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
X  volatile const uint32_t  RESP3;           
N  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
X  volatile const uint32_t  RESP4;           
N  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
X  volatile uint32_t DTIMER;          
N  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
X  volatile uint32_t DLEN;            
N  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
X  volatile uint32_t DCTRL;           
N  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
X  volatile const uint32_t  DCOUNT;          
N  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
X  volatile const uint32_t  STA;             
N  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
X  volatile uint32_t ICR;             
N  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
X  volatile uint32_t MASK;            
N  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
N  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
X  volatile const uint32_t  FIFOCNT;         
N  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
N  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
X  volatile uint32_t FIFO;            
N} SDIO_TypeDef;
N
N/** 
N  * @brief Serial Peripheral Interface
N  */
N
Ntypedef struct
N{
N  __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
X  volatile uint16_t CR1;         
N  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */
N  __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
X  volatile uint16_t CR2;         
N  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */
N  __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
X  volatile uint16_t SR;          
N  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */
N  __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
X  volatile uint16_t DR;          
N  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */
N  __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
X  volatile uint16_t CRCPR;       
N  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */
N  __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
X  volatile uint16_t RXCRCR;      
N  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */
N  __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
X  volatile uint16_t TXCRCR;      
N  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */
N  __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
X  volatile uint16_t I2SCFGR;     
N  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */
N  __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
X  volatile uint16_t I2SPR;       
N  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */
N} SPI_TypeDef;
N
N/** 
N  * @brief TIM
N  */
N
Ntypedef struct
N{
N  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
X  volatile uint16_t CR1;          
N  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
N  __IO uint16_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
X  volatile uint16_t CR2;          
N  uint16_t      RESERVED1;   /*!< Reserved, 0x06                                            */
N  __IO uint16_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
X  volatile uint16_t SMCR;         
N  uint16_t      RESERVED2;   /*!< Reserved, 0x0A                                            */
N  __IO uint16_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
X  volatile uint16_t DIER;         
N  uint16_t      RESERVED3;   /*!< Reserved, 0x0E                                            */
N  __IO uint16_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
X  volatile uint16_t SR;           
N  uint16_t      RESERVED4;   /*!< Reserved, 0x12                                            */
N  __IO uint16_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
X  volatile uint16_t EGR;          
N  uint16_t      RESERVED5;   /*!< Reserved, 0x16                                            */
N  __IO uint16_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
X  volatile uint16_t CCMR1;        
N  uint16_t      RESERVED6;   /*!< Reserved, 0x1A                                            */
N  __IO uint16_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
X  volatile uint16_t CCMR2;        
N  uint16_t      RESERVED7;   /*!< Reserved, 0x1E                                            */
N  __IO uint16_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
X  volatile uint16_t CCER;         
N  uint16_t      RESERVED8;   /*!< Reserved, 0x22                                            */
N  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
X  volatile uint32_t CNT;          
N  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
X  volatile uint16_t PSC;          
N  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
N  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
X  volatile uint32_t ARR;          
N  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
X  volatile uint16_t RCR;          
N  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
N  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
X  volatile uint32_t CCR1;         
N  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
X  volatile uint32_t CCR2;         
N  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
X  volatile uint32_t CCR3;         
N  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
X  volatile uint32_t CCR4;         
N  __IO uint16_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
X  volatile uint16_t BDTR;         
N  uint16_t      RESERVED11;  /*!< Reserved, 0x46                                            */
N  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
X  volatile uint16_t DCR;          
N  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
N  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
X  volatile uint16_t DMAR;         
N  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
N  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
X  volatile uint16_t OR;           
N  uint16_t      RESERVED14;  /*!< Reserved, 0x52                                            */
N} TIM_TypeDef;
N
N/** 
N  * @brief Universal Synchronous Asynchronous Receiver Transmitter
N  */
N 
Ntypedef struct
N{
N  __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
X  volatile uint16_t SR;          
N  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
N  __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
X  volatile uint16_t DR;          
N  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
N  __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
X  volatile uint16_t BRR;         
N  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
N  __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
X  volatile uint16_t CR1;         
N  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
N  __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
X  volatile uint16_t CR2;         
N  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
N  __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
X  volatile uint16_t CR3;         
N  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
N  __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
X  volatile uint16_t GTPR;        
N  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
N} USART_TypeDef;
N
N/** 
N  * @brief Window WATCHDOG
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
X  volatile uint32_t CR;    
N  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
X  volatile uint32_t CFR;   
N  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
X  volatile uint32_t SR;    
N} WWDG_TypeDef;
N
N/** 
N  * @brief Crypto Processor
N  */
N
Ntypedef struct
N{
N  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
X  volatile uint32_t CR;          
N  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
X  volatile uint32_t SR;          
N  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
X  volatile uint32_t DR;          
N  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
X  volatile uint32_t DOUT;        
N  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
X  volatile uint32_t DMACR;       
N  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
X  volatile uint32_t IMSCR;       
N  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
X  volatile uint32_t RISR;        
N  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
X  volatile uint32_t MISR;        
N  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
X  volatile uint32_t K0LR;        
N  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
X  volatile uint32_t K0RR;        
N  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
X  volatile uint32_t K1LR;        
N  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
X  volatile uint32_t K1RR;        
N  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
X  volatile uint32_t K2LR;        
N  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
X  volatile uint32_t K2RR;        
N  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
X  volatile uint32_t K3LR;        
N  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
X  volatile uint32_t K3RR;        
N  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
X  volatile uint32_t IV0LR;       
N  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
X  volatile uint32_t IV0RR;       
N  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
X  volatile uint32_t IV1LR;       
N  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
X  volatile uint32_t IV1RR;       
N  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
X  volatile uint32_t CSGCMCCM0R;  
N  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
X  volatile uint32_t CSGCMCCM1R;  
N  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
X  volatile uint32_t CSGCMCCM2R;  
N  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
X  volatile uint32_t CSGCMCCM3R;  
N  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
X  volatile uint32_t CSGCMCCM4R;  
N  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
X  volatile uint32_t CSGCMCCM5R;  
N  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
X  volatile uint32_t CSGCMCCM6R;  
N  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
X  volatile uint32_t CSGCMCCM7R;  
N  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
X  volatile uint32_t CSGCM0R;     
N  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
X  volatile uint32_t CSGCM1R;     
N  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
X  volatile uint32_t CSGCM2R;     
N  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
X  volatile uint32_t CSGCM3R;     
N  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
X  volatile uint32_t CSGCM4R;     
N  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
X  volatile uint32_t CSGCM5R;     
N  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
X  volatile uint32_t CSGCM6R;     
N  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
X  volatile uint32_t CSGCM7R;     
N} CRYP_TypeDef;
N
N/** 
N  * @brief HASH
N  */
N  
Ntypedef struct 
N{
N  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
X  volatile uint32_t CR;                
N  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
X  volatile uint32_t DIN;               
N  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
X  volatile uint32_t STR;               
N  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
X  volatile uint32_t HR[5];             
N  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
X  volatile uint32_t IMR;               
N  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
X  volatile uint32_t SR;                
N       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
N  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
X  volatile uint32_t CSR[54];           
N} HASH_TypeDef;
N
N/** 
N  * @brief HASH_DIGEST
N  */
N  
Ntypedef struct 
N{
N  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ 
X  volatile uint32_t HR[8];       
N} HASH_DIGEST_TypeDef;
N
N/** 
N  * @brief RNG
N  */
N  
Ntypedef struct 
N{
N  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
X  volatile uint32_t CR;   
N  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
X  volatile uint32_t SR;   
N  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
X  volatile uint32_t DR;   
N} RNG_TypeDef;
N
N/**
N  * @}
N  */
N  
N/** @addtogroup Peripheral_memory_map
N  * @{
N  */
N#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
N#define CCMDATARAM_BASE       ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
N#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
N#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
N#define SRAM3_BASE            ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region                              */
N#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
N#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
N
N#if defined (STM32F40_41xxx)
X#if 1L
N#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address                                                */
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
X#if 0L || 0L
S#define FMC_R_BASE            ((uint32_t)0xA0000000) /*!< FMC registers base address                                                 */
N#endif /* STM32F427_437xx ||  STM32F429_439xx */
N
N#define CCMDATARAM_BB_BASE    ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region  */
N#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                             */
N#define SRAM2_BB_BASE         ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region                              */
N#define SRAM3_BB_BASE         ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region                              */
N#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                                */
N#define BKPSRAM_BB_BASE       ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
N
N/* Legacy defines */
N#define SRAM_BASE             SRAM1_BASE
N#define SRAM_BB_BASE          SRAM1_BB_BASE
N
N
N/*!< Peripheral memory map */
N#define APB1PERIPH_BASE       PERIPH_BASE
N#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
N#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
N#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
N
N/*!< APB1 peripherals */
N#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
N#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
N#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
N#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
N#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
N#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
N#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
N#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
N#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
N#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
N#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
N#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
N#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)
N#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
N#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
N#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)
N#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
N#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
N#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
N#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
N#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
N#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
N#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
N#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
N#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
N#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
N#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
N#define UART7_BASE            (APB1PERIPH_BASE + 0x7800)
N#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00)
N
N/*!< APB2 peripherals */
N#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
N#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
N#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
N#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
N#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
N#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
N#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
N#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
N#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
N#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
N#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400)
N#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
N#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
N#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
N#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
N#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
N#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000)
N#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400)
N#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800)
N#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
N#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
N#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800)
N#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84)
N#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104) 
N
N/*!< AHB1 peripherals */
N#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
N#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
N#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
N#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
N#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
N#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
N#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
N#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
N#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
N#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400)
N#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800)
N#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
N#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
N#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
N#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
N#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
N#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
N#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
N#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
N#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
N#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
N#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
N#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
N#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
N#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
N#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
N#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
N#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
N#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
N#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
N#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
N#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
N#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
N#define ETH_MAC_BASE          (ETH_BASE)
N#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
N#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
N#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
N#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000)
N
N/*!< AHB2 peripherals */
N#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
N#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000)
N#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400)
N#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710)
N#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
N
N#if defined (STM32F40_41xxx)
X#if 1L
N/*!< FSMC Bankx registers base address */
N#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
N#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
N#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)
N#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)
N#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
X#if 0L || 0L
S/*!< FMC Bankx registers base address */
S#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000)
S#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104)
S#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060)
S#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080)
S#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0)
S#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140)
N#endif /* STM32F427_437xx ||  STM32F429_439xx */
N
N/* Debug MCU registers base address */
N#define DBGMCU_BASE           ((uint32_t )0xE0042000)
N
N/**
N  * @}
N  */
N  
N/** @addtogroup Peripheral_declaration
N  * @{
N  */  
N#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
N#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
N#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
N#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
N#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
N#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
N#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
N#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
N#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
N#define RTC                 ((RTC_TypeDef *) RTC_BASE)
N#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
N#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
N#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
N#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
N#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
N#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
N#define USART2              ((USART_TypeDef *) USART2_BASE)
N#define USART3              ((USART_TypeDef *) USART3_BASE)
N#define UART4               ((USART_TypeDef *) UART4_BASE)
N#define UART5               ((USART_TypeDef *) UART5_BASE)
N#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
N#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
N#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
N#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
N#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
N#define PWR                 ((PWR_TypeDef *) PWR_BASE)
N#define DAC                 ((DAC_TypeDef *) DAC_BASE)
N#define UART7               ((USART_TypeDef *) UART7_BASE)
N#define UART8               ((USART_TypeDef *) UART8_BASE)
N#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
N#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
N#define USART1              ((USART_TypeDef *) USART1_BASE)
N#define USART6              ((USART_TypeDef *) USART6_BASE)
N#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
N#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
N#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
N#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
N#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
N#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
N#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
N#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
N#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
N#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
N#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
N#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
N#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
N#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
N#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
N#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
N#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
N#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
N#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
N#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
N#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
N#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
N#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
N#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
N#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
N#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
N#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
N#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
N#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
N#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
N#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
N#define CRC                 ((CRC_TypeDef *) CRC_BASE)
N#define RCC                 ((RCC_TypeDef *) RCC_BASE)
N#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
N#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
N#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
N#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
N#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
N#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
N#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
N#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
N#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
N#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
N#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
N#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
N#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
N#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
N#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
N#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
N#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
N#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
N#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
N#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
N#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
N#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
N#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
N#define HASH                ((HASH_TypeDef *) HASH_BASE)
N#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
N#define RNG                 ((RNG_TypeDef *) RNG_BASE)
N
N#if defined (STM32F40_41xxx)
X#if 1L
N#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
N#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
N#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
N#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
N#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
X#if 0L || 0L
S#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
S#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
S#define FMC_Bank2           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
S#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
S#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
S#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
N#endif /* STM32F427_437xx ||  STM32F429_439xx */
N
N#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
N
N/**
N  * @}
N  */
N
N/** @addtogroup Exported_constants
N  * @{
N  */
N  
N  /** @addtogroup Peripheral_Registers_Bits_Definition
N  * @{
N  */
N    
N/******************************************************************************/
N/*                         Peripheral Registers_Bits_Definition               */
N/******************************************************************************/
N
N/******************************************************************************/
N/*                                                                            */
N/*                        Analog to Digital Converter                         */
N/*                                                                            */
N/******************************************************************************/
N/********************  Bit definition for ADC_SR register  ********************/
N#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!<Analog watchdog flag               */
N#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!<End of conversion                  */
N#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!<Injected channel end of conversion */
N#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!<Injected channel Start flag        */
N#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!<Regular channel Start flag         */
N#define  ADC_SR_OVR                          ((uint8_t)0x20)               /*!<Overrun flag                       */
N
N/*******************  Bit definition for ADC_CR1 register  ********************/
N#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
N#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC                              */
N#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable                     */
N#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels                */
N#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode                                             */
N#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode  */
N#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion                   */
N#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels                */
N#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels               */
N#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count)  */
N#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
N#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
N#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
N#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels           */
N#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels            */
N#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution)                            */
N#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable                              */
N  
N/*******************  Bit definition for ADC_CR2 register  ********************/
N#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF             */
N#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion              */
N#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode          */
N#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */
N#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection        */
N#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment                     */
N#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
N#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
N#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
N#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
N#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
N#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
N#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
N#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
N#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
N#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
N#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
N#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
N
N/******************  Bit definition for ADC_SMPR1 register  *******************/
N#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
N#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
N#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
N#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
N#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
N#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
N#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
N#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
N#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
N#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
N#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
N#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
N#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
N#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
N#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
N#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
N#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
N#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
N#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
N#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
N#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
N#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
N#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
N#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
N#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
N#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
N#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
N#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
N#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
N#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
N#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
N
N/******************  Bit definition for ADC_SMPR2 register  *******************/
N#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
N#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
N#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
N#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
N#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
N#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
N#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
N#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
N#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
N#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
N#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
N#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
N#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
N#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
N#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
N#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
N#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
N#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
N#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
N#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
N#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
N#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
N#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
N#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
N#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
N#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
N#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
N#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
N#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
N#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
N#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
N#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
N#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
N#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
N
N/******************  Bit definition for ADC_JOFR1 register  *******************/
N#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 1 */
N
N/******************  Bit definition for ADC_JOFR2 register  *******************/
N#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 2 */
N
N/******************  Bit definition for ADC_JOFR3 register  *******************/
N#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 3 */
N
N/******************  Bit definition for ADC_JOFR4 register  *******************/
N#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 4 */
N
N/*******************  Bit definition for ADC_HTR register  ********************/
N#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog high threshold */
N
N/*******************  Bit definition for ADC_LTR register  ********************/
N#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog low threshold */
N
N/*******************  Bit definition for ADC_SQR1 register  *******************/
N#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
N#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
N#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
N#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
N#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
N#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
N#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
N#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
N#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
N#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
N#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
N#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
N#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
N#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
N#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
N#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
N#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
N#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
N#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
N#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
N#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
N#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
N#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
N
N/*******************  Bit definition for ADC_SQR2 register  *******************/
N#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
N#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
N#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
N#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
N#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
N#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
N#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
N#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
N#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
N#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
N#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
N#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
N#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
N#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
N#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
N#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
N#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
N#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
N#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
N#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
N#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
N#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
N#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
N#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
N#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
N#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
N#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
N#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
N#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
N#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
N
N/*******************  Bit definition for ADC_SQR3 register  *******************/
N#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
N#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
N#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
N#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
N#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
N#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
N#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
N#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
N#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
N#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
N#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
N#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
N#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
N#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
N#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
N#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
N#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
N#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
N#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
N#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
N#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
N#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
N#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
N#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
N#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
N#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
N#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
N#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
N#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
N#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
N
N/*******************  Bit definition for ADC_JSQR register  *******************/
N#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
N#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
N#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
N#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
N#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
N#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
N#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
N#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
N#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
N#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
N#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
N#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
N#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
N#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
N#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
N#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
N#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
N#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
N#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
N#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
N#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
N
N/*******************  Bit definition for ADC_JDR1 register  *******************/
N#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
N
N/*******************  Bit definition for ADC_JDR2 register  *******************/
N#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
N
N/*******************  Bit definition for ADC_JDR3 register  *******************/
N#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
N
N/*******************  Bit definition for ADC_JDR4 register  *******************/
N#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
N
N/********************  Bit definition for ADC_DR register  ********************/
N#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
N#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
N
N/*******************  Bit definition for ADC_CSR register  ********************/
N#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */
N#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */
N#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
N#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */
N#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */
N#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */
N#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */
N#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */
N#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
N#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */
N#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */
N#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */
N#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */
N#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */
N#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
N#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */
N#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */
N#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */
N
N/*******************  Bit definition for ADC_CCR register  ********************/
N#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
N#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
N#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
N#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
N#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
N#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
N#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
N#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
N#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
N#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
N
N/*******************  Bit definition for ADC_CDR register  ********************/
N#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
N#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
N
N/******************************************************************************/
N/*                                                                            */
N/*                         Controller Area Network                            */
N/*                                                                            */
N/******************************************************************************/
N/*!<CAN control and status registers */
N/*******************  Bit definition for CAN_MCR register  ********************/
N#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
N#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
N#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
N#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
N#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
N#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
N#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
N#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
N#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
N
N/*******************  Bit definition for CAN_MSR register  ********************/
N#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
N#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
N#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
N#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
N#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
N#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
N#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
N#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
N#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
N
N/*******************  Bit definition for CAN_TSR register  ********************/
N#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
N#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
N#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
N#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
N#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
N#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
N#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
N#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
N#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
N#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
N#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
N#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
N#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
N#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
N#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
N#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
N
N#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
N#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
N#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
N#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
N
N#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
N#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
N#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
N#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
N
N/*******************  Bit definition for CAN_RF0R register  *******************/
N#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
N#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
N#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
N#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
N
N/*******************  Bit definition for CAN_RF1R register  *******************/
N#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
N#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
N#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
N#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
N
N/********************  Bit definition for CAN_IER register  *******************/
N#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
N#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
N#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
N#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
N#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
N#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
N#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
N#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
N#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
N#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
N#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
N#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
N#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
N#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
N
N/********************  Bit definition for CAN_ESR register  *******************/
N#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
N#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
N#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
N
N#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
N#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
N#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
N
N#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
N#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
N
N/*******************  Bit definition for CAN_BTR register  ********************/
N#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
N#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
N#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
N#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
N#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
N#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
N
N/*!<Mailbox registers */
N/******************  Bit definition for CAN_TI0R register  ********************/
N#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
N#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
N#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
N#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
N#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
N
N/******************  Bit definition for CAN_TDT0R register  *******************/
N#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
N#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
N#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
N
N/******************  Bit definition for CAN_TDL0R register  *******************/
N#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
N#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
N#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
N#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
N
N/******************  Bit definition for CAN_TDH0R register  *******************/
N#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
N#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
N#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
N#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
N
N/*******************  Bit definition for CAN_TI1R register  *******************/
N#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
N#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
N#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
N#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
N#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
N
N/*******************  Bit definition for CAN_TDT1R register  ******************/
N#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
N#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
N#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
N
N/*******************  Bit definition for CAN_TDL1R register  ******************/
N#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
N#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
N#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
N#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
N
N/*******************  Bit definition for CAN_TDH1R register  ******************/
N#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
N#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
N#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
N#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
N
N/*******************  Bit definition for CAN_TI2R register  *******************/
N#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
N#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
N#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
N#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
N#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
N
N/*******************  Bit definition for CAN_TDT2R register  ******************/  
N#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
N#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
N#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
N
N/*******************  Bit definition for CAN_TDL2R register  ******************/
N#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
N#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
N#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
N#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
N
N/*******************  Bit definition for CAN_TDH2R register  ******************/
N#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
N#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
N#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
N#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
N
N/*******************  Bit definition for CAN_RI0R register  *******************/
N#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
N#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
N#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
N#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
N
N/*******************  Bit definition for CAN_RDT0R register  ******************/
N#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
N#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
N#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
N
N/*******************  Bit definition for CAN_RDL0R register  ******************/
N#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
N#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
N#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
N#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
N
N/*******************  Bit definition for CAN_RDH0R register  ******************/
N#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
N#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
N#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
N#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
N
N/*******************  Bit definition for CAN_RI1R register  *******************/
N#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
N#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
N#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
N#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
N
N/*******************  Bit definition for CAN_RDT1R register  ******************/
N#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
N#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
N#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
N
N/*******************  Bit definition for CAN_RDL1R register  ******************/
N#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
N#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
N#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
N#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
N
N/*******************  Bit definition for CAN_RDH1R register  ******************/
N#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
N#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
N#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
N#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
N
N/*!<CAN filter registers */
N/*******************  Bit definition for CAN_FMR register  ********************/
N#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
N
N/*******************  Bit definition for CAN_FM1R register  *******************/
N#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
N#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
N#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
N#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
N#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
N#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
N#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
N#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
N#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
N#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
N#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
N#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
N#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
N#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
N#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
N
N/*******************  Bit definition for CAN_FS1R register  *******************/
N#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
N#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
N#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
N#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
N#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
N#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
N#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
N#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
N#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
N#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
N#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
N#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
N#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
N#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
N#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
N
N/******************  Bit definition for CAN_FFA1R register  *******************/
N#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
N#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
N#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
N#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
N#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
N#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
N#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
N#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
N#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
N#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
N#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
N#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
N#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
N#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
N#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
N
N/*******************  Bit definition for CAN_FA1R register  *******************/
N#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
N#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
N#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
N#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
N#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
N#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
N#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
N#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
N#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
N#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
N#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
N#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
N#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
N#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
N#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
N
N/*******************  Bit definition for CAN_F0R1 register  *******************/
N#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F1R1 register  *******************/
N#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F2R1 register  *******************/
N#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F3R1 register  *******************/
N#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F4R1 register  *******************/
N#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F5R1 register  *******************/
N#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F6R1 register  *******************/
N#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F7R1 register  *******************/
N#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F8R1 register  *******************/
N#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F9R1 register  *******************/
N#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F10R1 register  ******************/
N#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F11R1 register  ******************/
N#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F12R1 register  ******************/
N#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F13R1 register  ******************/
N#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F0R2 register  *******************/
N#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F1R2 register  *******************/
N#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F2R2 register  *******************/
N#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F3R2 register  *******************/
N#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F4R2 register  *******************/
N#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F5R2 register  *******************/
N#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F6R2 register  *******************/
N#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F7R2 register  *******************/
N#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F8R2 register  *******************/
N#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F9R2 register  *******************/
N#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F10R2 register  ******************/
N#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F11R2 register  ******************/
N#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F12R2 register  ******************/
N#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/*******************  Bit definition for CAN_F13R2 register  ******************/
N#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
N#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
N#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
N#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
N#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
N#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
N#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
N#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
N#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
N#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
N#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
N#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
N#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
N#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
N#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
N#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
N#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
N#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
N#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
N#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
N#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
N#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
N#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
N#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
N#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
N#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
N#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
N#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
N#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
N#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
N#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
N#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
N
N/******************************************************************************/
N/*                                                                            */
N/*                          CRC calculation unit                              */
N/*                                                                            */
N/******************************************************************************/
N/*******************  Bit definition for CRC_DR register  *********************/
N#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
N
N
N/*******************  Bit definition for CRC_IDR register  ********************/
N#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
N
N
N/********************  Bit definition for CRC_CR register  ********************/
N#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
N
N/******************************************************************************/
N/*                                                                            */
N/*                            Crypto Processor                                */
N/*                                                                            */
N/******************************************************************************/
N/******************* Bits definition for CRYP_CR register  ********************/
N#define CRYP_CR_ALGODIR                      ((uint32_t)0x00000004)
N
N#define CRYP_CR_ALGOMODE                     ((uint32_t)0x00080038)
N#define CRYP_CR_ALGOMODE_0                   ((uint32_t)0x00000008)
N#define CRYP_CR_ALGOMODE_1                   ((uint32_t)0x00000010)
N#define CRYP_CR_ALGOMODE_2                   ((uint32_t)0x00000020)
N#define CRYP_CR_ALGOMODE_TDES_ECB            ((uint32_t)0x00000000)
N#define CRYP_CR_ALGOMODE_TDES_CBC            ((uint32_t)0x00000008)
N#define CRYP_CR_ALGOMODE_DES_ECB             ((uint32_t)0x00000010)
N#define CRYP_CR_ALGOMODE_DES_CBC             ((uint32_t)0x00000018)
N#define CRYP_CR_ALGOMODE_AES_ECB             ((uint32_t)0x00000020)
N#define CRYP_CR_ALGOMODE_AES_CBC             ((uint32_t)0x00000028)
N#define CRYP_CR_ALGOMODE_AES_CTR             ((uint32_t)0x00000030)
N#define CRYP_CR_ALGOMODE_AES_KEY             ((uint32_t)0x00000038)
N
N#define CRYP_CR_DATATYPE                     ((uint32_t)0x000000C0)
N#define CRYP_CR_DATATYPE_0                   ((uint32_t)0x00000040)
N#define CRYP_CR_DATATYPE_1                   ((uint32_t)0x00000080)
N#define CRYP_CR_KEYSIZE                      ((uint32_t)0x00000300)
N#define CRYP_CR_KEYSIZE_0                    ((uint32_t)0x00000100)
N#define CRYP_CR_KEYSIZE_1                    ((uint32_t)0x00000200)
N#define CRYP_CR_FFLUSH                       ((uint32_t)0x00004000)
N#define CRYP_CR_CRYPEN                       ((uint32_t)0x00008000)
N
N#define CRYP_CR_GCM_CCMPH                    ((uint32_t)0x00030000)
N#define CRYP_CR_GCM_CCMPH_0                  ((uint32_t)0x00010000)
N#define CRYP_CR_GCM_CCMPH_1                  ((uint32_t)0x00020000)
N#define CRYP_CR_ALGOMODE_3                   ((uint32_t)0x00080000) 
N
N/****************** Bits definition for CRYP_SR register  *********************/
N#define CRYP_SR_IFEM                         ((uint32_t)0x00000001)
N#define CRYP_SR_IFNF                         ((uint32_t)0x00000002)
N#define CRYP_SR_OFNE                         ((uint32_t)0x00000004)
N#define CRYP_SR_OFFU                         ((uint32_t)0x00000008)
N#define CRYP_SR_BUSY                         ((uint32_t)0x00000010)
N/****************** Bits definition for CRYP_DMACR register  ******************/
N#define CRYP_DMACR_DIEN                      ((uint32_t)0x00000001)
N#define CRYP_DMACR_DOEN                      ((uint32_t)0x00000002)
N/*****************  Bits definition for CRYP_IMSCR register  ******************/
N#define CRYP_IMSCR_INIM                      ((uint32_t)0x00000001)
N#define CRYP_IMSCR_OUTIM                     ((uint32_t)0x00000002)
N/****************** Bits definition for CRYP_RISR register  *******************/
N#define CRYP_RISR_OUTRIS                     ((uint32_t)0x00000001)
N#define CRYP_RISR_INRIS                      ((uint32_t)0x00000002)
N/****************** Bits definition for CRYP_MISR register  *******************/
N#define CRYP_MISR_INMIS                      ((uint32_t)0x00000001)
N#define CRYP_MISR_OUTMIS                     ((uint32_t)0x00000002)
N
N/******************************************************************************/
N/*                                                                            */
N/*                      Digital to Analog Converter                           */
N/*                                                                            */
N/******************************************************************************/
N/********************  Bit definition for DAC_CR register  ********************/
N#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
N#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
N#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
N
N#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
N#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
N#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
N#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
N
N#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
N#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
N#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
N
N#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
N#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
N
N#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
N#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
N#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
N#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
N
N#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
N#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
N#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
N#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
N
N#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
N#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
N#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
N
N#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
N#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
N
N#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
N
N/*****************  Bit definition for DAC_SWTRIGR register  ******************/
N#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
N#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
N
N/*****************  Bit definition for DAC_DHR12R1 register  ******************/
N#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
N
N/*****************  Bit definition for DAC_DHR12L1 register  ******************/
N#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
N
N/******************  Bit definition for DAC_DHR8R1 register  ******************/
N#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
N
N/*****************  Bit definition for DAC_DHR12R2 register  ******************/
N#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
N
N/*****************  Bit definition for DAC_DHR12L2 register  ******************/
N#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
N
N/******************  Bit definition for DAC_DHR8R2 register  ******************/
N#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
N
N/*****************  Bit definition for DAC_DHR12RD register  ******************/
N#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
N#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
N
N/*****************  Bit definition for DAC_DHR12LD register  ******************/
N#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
N#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
N
N/******************  Bit definition for DAC_DHR8RD register  ******************/
N#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
N#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
N
N/*******************  Bit definition for DAC_DOR1 register  *******************/
N#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
N
N/*******************  Bit definition for DAC_DOR2 register  *******************/
N#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
N
N/********************  Bit definition for DAC_SR register  ********************/
N#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
N#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
N
N/******************************************************************************/
N/*                                                                            */
N/*                                 Debug MCU                                  */
N/*                                                                            */
N/******************************************************************************/
N
N/******************************************************************************/
N/*                                                                            */
N/*                                    DCMI                                    */
N/*                                                                            */
N/******************************************************************************/
N/********************  Bits definition for DCMI_CR register  ******************/
N#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001)
N#define DCMI_CR_CM                           ((uint32_t)0x00000002)
N#define DCMI_CR_CROP                         ((uint32_t)0x00000004)
N#define DCMI_CR_JPEG                         ((uint32_t)0x00000008)
N#define DCMI_CR_ESS                          ((uint32_t)0x00000010)
N#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020)
N#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040)
N#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080)
N#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100)
N#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200)
N#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400)
N#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800)
N#define DCMI_CR_CRE                          ((uint32_t)0x00001000)
N#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000)
N
N/********************  Bits definition for DCMI_SR register  ******************/
N#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001)
N#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002)
N#define DCMI_SR_FNE                          ((uint32_t)0x00000004)
N
N/********************  Bits definition for DCMI_RISR register  ****************/
N#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001)
N#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002)
N#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004)
N#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008)
N#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010)
N
N/********************  Bits definition for DCMI_IER register  *****************/
N#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001)
N#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002)
N#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004)
N#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008)
N#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010)
N
N/********************  Bits definition for DCMI_MISR register  ****************/
N#define DCMI_MISR_FRAME_MIS                  ((uint32_t)0x00000001)
N#define DCMI_MISR_OVF_MIS                    ((uint32_t)0x00000002)
N#define DCMI_MISR_ERR_MIS                    ((uint32_t)0x00000004)
N#define DCMI_MISR_VSYNC_MIS                  ((uint32_t)0x00000008)
N#define DCMI_MISR_LINE_MIS                   ((uint32_t)0x00000010)
N
N/********************  Bits definition for DCMI_ICR register  *****************/
N#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001)
N#define DCMI_ICR_OVF_ISC                     ((uint32_t)0x00000002)
N#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004)
N#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008)
N#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010)
N
N/******************************************************************************/
N/*                                                                            */
N/*                             DMA Controller                                 */
N/*                                                                            */
N/******************************************************************************/
N/********************  Bits definition for DMA_SxCR register  *****************/ 
N#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
N#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
N#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
N#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
N#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
N#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
N#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
N#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
N#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
N#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
N#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
N#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  
N#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
N#define DMA_SxCR_PL                          ((uint32_t)0x00030000)
N#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
N#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
N#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
N#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
N#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
N#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
N#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
N#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
N#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
N#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
N#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
N#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
N#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
N#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
N#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
N#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
N#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
N#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
N#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
N#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
N#define DMA_SxCR_EN                          ((uint32_t)0x00000001)
N
N/********************  Bits definition for DMA_SxCNDTR register  **************/
N#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
N#define DMA_SxNDT_0                          ((uint32_t)0x00000001)
N#define DMA_SxNDT_1                          ((uint32_t)0x00000002)
N#define DMA_SxNDT_2                          ((uint32_t)0x00000004)
N#define DMA_SxNDT_3                          ((uint32_t)0x00000008)
N#define DMA_SxNDT_4                          ((uint32_t)0x00000010)
N#define DMA_SxNDT_5                          ((uint32_t)0x00000020)
N#define DMA_SxNDT_6                          ((uint32_t)0x00000040)
N#define DMA_SxNDT_7                          ((uint32_t)0x00000080)
N#define DMA_SxNDT_8                          ((uint32_t)0x00000100)
N#define DMA_SxNDT_9                          ((uint32_t)0x00000200)
N#define DMA_SxNDT_10                         ((uint32_t)0x00000400)
N#define DMA_SxNDT_11                         ((uint32_t)0x00000800)
N#define DMA_SxNDT_12                         ((uint32_t)0x00001000)
N#define DMA_SxNDT_13                         ((uint32_t)0x00002000)
N#define DMA_SxNDT_14                         ((uint32_t)0x00004000)
N#define DMA_SxNDT_15                         ((uint32_t)0x00008000)
N
N/********************  Bits definition for DMA_SxFCR register  ****************/ 
N#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
N#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
N#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
N#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
N#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
N#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
N#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
N#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
N#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
N
N/********************  Bits definition for DMA_LISR register  *****************/ 
N#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
N#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
N#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
N#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
N#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
N#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
N#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
N#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
N#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
N#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
N#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
N#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
N#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
N#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
N#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
N#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
N#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
N#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
N#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
N#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
N
N/********************  Bits definition for DMA_HISR register  *****************/ 
N#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
N#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
N#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
N#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
N#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
N#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
N#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
N#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
N#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
N#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
N#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
N#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
N#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
N#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
N#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
N#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
N#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
N#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
N#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
N#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
N
N/********************  Bits definition for DMA_LIFCR register  ****************/ 
N#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
N#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
N#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
N#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
N#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
N#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
N#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
N#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
N#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
N#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
N#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
N#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
N#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
N#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
N#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
N#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
N#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
N#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
N#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
N#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
N
N/********************  Bits definition for DMA_HIFCR  register  ****************/ 
N#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
N#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
N#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
N#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
N#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
N#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
N#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
N#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
N#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
N#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
N#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
N#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
N#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
N#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
N#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
N#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
N#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
N#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
N#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
N#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
N
N/******************************************************************************/
N/*                                                                            */
N/*                         AHB Master DMA2D Controller (DMA2D)                */
N/*                                                                            */
N/******************************************************************************/
N
N/********************  Bit definition for DMA2D_CR register  ******************/
N
N#define DMA2D_CR_START                     ((uint32_t)0x00000001)               /*!< Start transfer */
N#define DMA2D_CR_SUSP                      ((uint32_t)0x00000002)               /*!< Suspend transfer */
N#define DMA2D_CR_ABORT                     ((uint32_t)0x00000004)               /*!< Abort transfer */
N#define DMA2D_CR_TEIE                      ((uint32_t)0x00000100)               /*!< Transfer Error Interrupt Enable */
N#define DMA2D_CR_TCIE                      ((uint32_t)0x00000200)               /*!< Transfer Complete Interrupt Enable */
N#define DMA2D_CR_TWIE                      ((uint32_t)0x00000400)               /*!< Transfer Watermark Interrupt Enable */
N#define DMA2D_CR_CAEIE                     ((uint32_t)0x00000800)               /*!< CLUT Access Error Interrupt Enable */
N#define DMA2D_CR_CTCIE                     ((uint32_t)0x00001000)               /*!< CLUT Transfer Complete Interrupt Enable */
N#define DMA2D_CR_CEIE                      ((uint32_t)0x00002000)               /*!< Configuration Error Interrupt Enable */
N#define DMA2D_CR_MODE                      ((uint32_t)0x00030000)               /*!< DMA2D Mode */
N
N/********************  Bit definition for DMA2D_ISR register  *****************/
N
N#define DMA2D_ISR_TEIF                     ((uint32_t)0x00000001)               /*!< Transfer Error Interrupt Flag */
N#define DMA2D_ISR_TCIF                     ((uint32_t)0x00000002)               /*!< Transfer Complete Interrupt Flag */
N#define DMA2D_ISR_TWIF                     ((uint32_t)0x00000004)               /*!< Transfer Watermark Interrupt Flag */
N#define DMA2D_ISR_CAEIF                    ((uint32_t)0x00000008)               /*!< CLUT Access Error Interrupt Flag */
N#define DMA2D_ISR_CTCIF                    ((uint32_t)0x00000010)               /*!< CLUT Transfer Complete Interrupt Flag */
N#define DMA2D_ISR_CEIF                     ((uint32_t)0x00000020)               /*!< Configuration Error Interrupt Flag */
N
N/********************  Bit definition for DMA2D_IFSR register  ****************/
N
N#define DMA2D_IFSR_CTEIF                   ((uint32_t)0x00000001)               /*!< Clears Transfer Error Interrupt Flag */
N#define DMA2D_IFSR_CTCIF                   ((uint32_t)0x00000002)               /*!< Clears Transfer Complete Interrupt Flag */
N#define DMA2D_IFSR_CTWIF                   ((uint32_t)0x00000004)               /*!< Clears Transfer Watermark Interrupt Flag */
N#define DMA2D_IFSR_CCAEIF                  ((uint32_t)0x00000008)               /*!< Clears CLUT Access Error Interrupt Flag */
N#define DMA2D_IFSR_CCTCIF                  ((uint32_t)0x00000010)               /*!< Clears CLUT Transfer Complete Interrupt Flag */
N#define DMA2D_IFSR_CCEIF                   ((uint32_t)0x00000020)               /*!< Clears Configuration Error Interrupt Flag */
N
N/********************  Bit definition for DMA2D_FGMAR register  ***************/
N
N#define DMA2D_FGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
N
N/********************  Bit definition for DMA2D_FGOR register  ****************/
N
N#define DMA2D_FGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
N
N/********************  Bit definition for DMA2D_BGMAR register  ***************/
N
N#define DMA2D_BGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
N
N/********************  Bit definition for DMA2D_BGOR register  ****************/
N
N#define DMA2D_BGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
N
N/********************  Bit definition for DMA2D_FGPFCCR register  *************/
N
N#define DMA2D_FGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */
N#define DMA2D_FGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
N#define DMA2D_FGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */
N#define DMA2D_FGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */
N#define DMA2D_FGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha mode */
N#define DMA2D_FGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */
N
N/********************  Bit definition for DMA2D_FGCOLR register  **************/
N
N#define DMA2D_FGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */
N#define DMA2D_FGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
N#define DMA2D_FGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */   
N
N/********************  Bit definition for DMA2D_BGPFCCR register  *************/
N
N#define DMA2D_BGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */
N#define DMA2D_BGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
N#define DMA2D_BGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */
N#define DMA2D_BGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */
N#define DMA2D_BGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha Mode */
N#define DMA2D_BGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */
N
N/********************  Bit definition for DMA2D_BGCOLR register  **************/
N
N#define DMA2D_BGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */
N#define DMA2D_BGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
N#define DMA2D_BGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */
N
N/********************  Bit definition for DMA2D_FGCMAR register  **************/
N
N#define DMA2D_FGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
N
N/********************  Bit definition for DMA2D_BGCMAR register  **************/
N
N#define DMA2D_BGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
N
N/********************  Bit definition for DMA2D_OPFCCR register  **************/
N
N#define DMA2D_OPFCCR_CM                    ((uint32_t)0x00000007)               /*!< Color mode */
N
N/********************  Bit definition for DMA2D_OCOLR register  ***************/
N
N/*!<Mode_ARGB8888/RGB888 */
N
N#define DMA2D_OCOLR_BLUE_1                 ((uint32_t)0x000000FF)               /*!< BLUE Value */
N#define DMA2D_OCOLR_GREEN_1                ((uint32_t)0x0000FF00)               /*!< GREEN Value  */
N#define DMA2D_OCOLR_RED_1                  ((uint32_t)0x00FF0000)               /*!< Red Value */
N#define DMA2D_OCOLR_ALPHA_1                ((uint32_t)0xFF000000)               /*!< Alpha Channel Value */
N
N/*!<Mode_RGB565 */
N#define DMA2D_OCOLR_BLUE_2                 ((uint32_t)0x0000001F)               /*!< BLUE Value */
N#define DMA2D_OCOLR_GREEN_2                ((uint32_t)0x000007E0)               /*!< GREEN Value  */
N#define DMA2D_OCOLR_RED_2                  ((uint32_t)0x0000F800)               /*!< Red Value */
N
N/*!<Mode_ARGB1555 */
N#define DMA2D_OCOLR_BLUE_3                 ((uint32_t)0x0000001F)               /*!< BLUE Value */
N#define DMA2D_OCOLR_GREEN_3                ((uint32_t)0x000003E0)               /*!< GREEN Value  */
N#define DMA2D_OCOLR_RED_3                  ((uint32_t)0x00007C00)               /*!< Red Value */
N#define DMA2D_OCOLR_ALPHA_3                ((uint32_t)0x00008000)               /*!< Alpha Channel Value */
N
N/*!<Mode_ARGB4444 */
N#define DMA2D_OCOLR_BLUE_4                 ((uint32_t)0x0000000F)               /*!< BLUE Value */
N#define DMA2D_OCOLR_GREEN_4                ((uint32_t)0x000000F0)               /*!< GREEN Value  */
N#define DMA2D_OCOLR_RED_4                  ((uint32_t)0x00000F00)               /*!< Red Value */
N#define DMA2D_OCOLR_ALPHA_4                ((uint32_t)0x0000F000)               /*!< Alpha Channel Value */
N
N/********************  Bit definition for DMA2D_OMAR register  ****************/
N
N#define DMA2D_OMAR_MA                      ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
N
N/********************  Bit definition for DMA2D_OOR register  *****************/
N
N#define DMA2D_OOR_LO                       ((uint32_t)0x00003FFF)               /*!< Line Offset */
N
N/********************  Bit definition for DMA2D_NLR register  *****************/
N
N#define DMA2D_NLR_NL                       ((uint32_t)0x0000FFFF)               /*!< Number of Lines */
N#define DMA2D_NLR_PL                       ((uint32_t)0x3FFF0000)               /*!< Pixel per Lines */
N
N/********************  Bit definition for DMA2D_LWR register  *****************/
N
N#define DMA2D_LWR_LW                       ((uint32_t)0x0000FFFF)               /*!< Line Watermark */
N
N/********************  Bit definition for DMA2D_AMTCR register  ***************/
N
N#define DMA2D_AMTCR_EN                     ((uint32_t)0x00000001)               /*!< Enable */
N#define DMA2D_AMTCR_DT                     ((uint32_t)0x0000FF00)               /*!< Dead Time */
N
N
N
N/********************  Bit definition for DMA2D_FGCLUT register  **************/
N                                                                     
N/********************  Bit definition for DMA2D_BGCLUT register  **************/
N
N
N/******************************************************************************/
N/*                                                                            */
N/*                    External Interrupt/Event Controller                     */
N/*                                                                            */
N/******************************************************************************/
N/*******************  Bit definition for EXTI_IMR register  *******************/
N#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
N#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
N#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
N#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
N#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
N#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
N#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
N#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
N#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
N#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
N#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
N#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
N#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
N#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
N#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
N#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
N#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
N#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
N#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
N#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
N
N/*******************  Bit definition for EXTI_EMR register  *******************/
N#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
N#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
N#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
N#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
N#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
N#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
N#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
N#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
N#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
N#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
N#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
N#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
N#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
N#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
N#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
N#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
N#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
N#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
N#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
N#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
N
N/******************  Bit definition for EXTI_RTSR register  *******************/
N#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
N#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
N#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
N#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
N#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
N#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
N#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
N#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
N#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
N#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
N#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
N#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
N#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
N#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
N#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
N#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
N#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
N#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
N#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
N#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
N
N/******************  Bit definition for EXTI_FTSR register  *******************/
N#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
N#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
N#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
N#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
N#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
N#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
N#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
N#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
N#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
N#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
N#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
N#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
N#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
N#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
N#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
N#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
N#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
N#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
N#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
N#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
N
N/******************  Bit definition for EXTI_SWIER register  ******************/
N#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
N#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
N#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
N#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
N#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
N#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
N#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
N#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
N#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
N#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
N#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
N#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
N#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
N#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
N#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
N#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
N#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
N#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
N#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
N#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
N
N/*******************  Bit definition for EXTI_PR register  ********************/
N#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
N#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
N#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
N#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
N#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
N#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
N#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
N#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
N#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
N#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
N#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
N#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
N#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
N#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
N#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
N#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
N#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
N#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
N#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
N#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
N
N/******************************************************************************/
N/*                                                                            */
N/*                                    FLASH                                   */
N/*                                                                            */
N/******************************************************************************/
N/*******************  Bits definition for FLASH_ACR register  *****************/
N#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000F)
N#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
N#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
N#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
N#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
N#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
N#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
N#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
N#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
N#define FLASH_ACR_LATENCY_8WS                ((uint32_t)0x00000008)
N#define FLASH_ACR_LATENCY_9WS                ((uint32_t)0x00000009)
N#define FLASH_ACR_LATENCY_10WS               ((uint32_t)0x0000000A)
N#define FLASH_ACR_LATENCY_11WS               ((uint32_t)0x0000000B)
N#define FLASH_ACR_LATENCY_12WS               ((uint32_t)0x0000000C)
N#define FLASH_ACR_LATENCY_13WS               ((uint32_t)0x0000000D)
N#define FLASH_ACR_LATENCY_14WS               ((uint32_t)0x0000000E)
N#define FLASH_ACR_LATENCY_15WS               ((uint32_t)0x0000000F)
N
N#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
N#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)
N#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)
N#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)
N#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)
N#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)
N#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)
N
N/*******************  Bits definition for FLASH_SR register  ******************/
N#define FLASH_SR_EOP                         ((uint32_t)0x00000001)
N#define FLASH_SR_SOP                         ((uint32_t)0x00000002)
N#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
N#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
N#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
N#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)
N#define FLASH_SR_BSY                         ((uint32_t)0x00010000)
N
N/*******************  Bits definition for FLASH_CR register  ******************/
N#define FLASH_CR_PG                          ((uint32_t)0x00000001)
N#define FLASH_CR_SER                         ((uint32_t)0x00000002)
N#define FLASH_CR_MER                         ((uint32_t)0x00000004)
N#define FLASH_CR_MER1                        FLASH_CR_MER
N#define FLASH_CR_SNB                         ((uint32_t)0x000000F8)
N#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
N#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
N#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
N#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
N#define FLASH_CR_SNB_4                       ((uint32_t)0x00000040)
N#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300)
N#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
N#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
N#define FLASH_CR_MER2                        ((uint32_t)0x00008000)
N#define FLASH_CR_STRT                        ((uint32_t)0x00010000)
N#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
N#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
N
N/*******************  Bits definition for FLASH_OPTCR register  ***************/
N#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001)
N#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002)
N#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004)
N#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008)
N#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000C)
N#define FLASH_OPTCR_BFB2                    ((uint32_t)0x00000010)
N
N#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020)
N#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040)
N#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080)
N#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00)
N#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100)
N#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200)
N#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400)
N#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800)
N#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000)
N#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000)
N#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000)
N#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000)
N#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000)
N#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000)
N#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000)
N#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000)
N#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000)
N#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000)
N#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000)
N#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000)
N#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000)
N#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000)
N#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000)
N#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000)
N#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000)
N
N#define FLASH_OPTCR_DB1M                    ((uint32_t)0x40000000) 
N#define FLASH_OPTCR_SPRMOD                  ((uint32_t)0x80000000) 
N                                             
N/******************  Bits definition for FLASH_OPTCR1 register  ***************/
N#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000)
N#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000)
N#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000)
N#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000)
N#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000)
N#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000)
N#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000)
N#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000)
N#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000)
N#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000)
N#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000)
N#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000)
N#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000)
N
N#if defined (STM32F40_41xxx)
X#if 1L
N/******************************************************************************/
N/*                                                                            */
N/*                       Flexible Static Memory Controller                    */
N/*                                                                            */
N/******************************************************************************/
N/******************  Bit definition for FSMC_BCR1 register  *******************/
N#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
N#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
N
N#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
N#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
N#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
N
N#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
N#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
N
N#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
N#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
N#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
N#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
N#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
N#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
N#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
N#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
N#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
N#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
N
N/******************  Bit definition for FSMC_BCR2 register  *******************/
N#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                */
N#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
N
N#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
N#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
N#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
N
N#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
N#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
N
N#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
N#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
N#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
N#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
N#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
N#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
N#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
N#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
N#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
N#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
N
N/******************  Bit definition for FSMC_BCR3 register  *******************/
N#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
N#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
N
N#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
N#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
N#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
N
N#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
N#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
N
N#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
N#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
N#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
N#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
N#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
N#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
N#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
N#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
N#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
N#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
N
N/******************  Bit definition for FSMC_BCR4 register  *******************/
N#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
N#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
N
N#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
N#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
N#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
N
N#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
N#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
N
N#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
N#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
N#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
N#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
N#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
N#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
N#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
N#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
N#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
N#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
N
N/******************  Bit definition for FSMC_BTR1 register  ******************/
N#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
N#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
N
N#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
N#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
N#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
N#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
N
N#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
N#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
N
N#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
N#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
N#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
N
N#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
N#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
N#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
N#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
N
N#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
N#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
N
N#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
N#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
N#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
N
N/******************  Bit definition for FSMC_BTR2 register  *******************/
N#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
N#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
N
N#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
N#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
N#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
N#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
N
N#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
N#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
N
N#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
N#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
N#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
N
N#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
N#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
N#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
N#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
N
N#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
N#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
N
N#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
N#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
N#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
N
N/*******************  Bit definition for FSMC_BTR3 register  *******************/
N#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
N#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
N
N#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
N#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
N#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
N#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
N
N#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
N#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
N
N#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
N#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
N#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
N
N#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
N#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
N#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
N#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
N
N#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
N#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
N
N#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
N#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
N#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
N
N/******************  Bit definition for FSMC_BTR4 register  *******************/
N#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
N#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
N
N#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
N#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
N#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
N#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
N
N#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
N#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
N
N#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
N#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
N#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
N
N#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
N#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
N#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
N#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
N
N#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
N#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
N
N#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
N#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
N#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
N
N/******************  Bit definition for FSMC_BWTR1 register  ******************/
N#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
N#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
N
N#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
N#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
N#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
N#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
N
N#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
N#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
N
N#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
N#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
N#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
N#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
N
N#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
N#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
N
N#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
N#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
N#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
N
N/******************  Bit definition for FSMC_BWTR2 register  ******************/
N#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
N#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
N
N#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
N#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
N#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
N#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
N
N#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
N#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
N
N#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
N#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
N#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
N#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
N
N#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
N#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
N
N#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
N#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
N#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
N
N/******************  Bit definition for FSMC_BWTR3 register  ******************/
N#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
N#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
N
N#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
N#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
N#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
N#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
N
N#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
N#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
N
N#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
N#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
N#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
N#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
N
N#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
N#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
N
N#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
N#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
N#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
N
N/******************  Bit definition for FSMC_BWTR4 register  ******************/
N#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
N#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
N
N#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
N#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
N#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
N#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
N
N#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
N#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
N
N#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
N#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
N#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
N#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
N#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
N
N#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
N#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
N
N#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
N#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
N#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
N
N/******************  Bit definition for FSMC_PCR2 register  *******************/
N#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
N#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
N#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
N
N#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
N#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
N
N#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
N
N#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
N#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
N#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
N#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
N#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
N
N#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
N#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
N#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
N#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
N#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
N
N#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size) */
N#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
N#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
N#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
N
N/******************  Bit definition for FSMC_PCR3 register  *******************/
N#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
N#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
N#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
N
N#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
N#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
N
N#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
N
N#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
N#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
N#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
N#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
N#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
N
N#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
N#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
N#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
N#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
N#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
N
N#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
N#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
N#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
N#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
N
N/******************  Bit definition for FSMC_PCR4 register  *******************/
N#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
N#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
N#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
N
N#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
N#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
N
N#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
N
N#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
N#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
N#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
N#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
N#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
N
N#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
N#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
N#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
N#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
N#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
N
N#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
N#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
N#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
N#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
N
N/*******************  Bit definition for FSMC_SR2 register  *******************/
N#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
N#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
N#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
N#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
N#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
N#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
N#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
N
N/*******************  Bit definition for FSMC_SR3 register  *******************/
N#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
N#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
N#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
N#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
N#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
N#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
N#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
N
N/*******************  Bit definition for FSMC_SR4 register  *******************/
N#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                 */
N#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                       */
N#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status                */
N#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit   */
N#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit         */
N#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit  */
N#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
N
N/******************  Bit definition for FSMC_PMEM2 register  ******************/
N#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
N#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
N#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
N#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
N
N#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
N#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
N#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
N#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
N#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
N#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
N
N#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
N#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
N#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
N#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
N#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
N#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
N#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
N
N#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
N#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
N#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
N#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
N#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
N#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
N
N/******************  Bit definition for FSMC_PMEM3 register  ******************/
N#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
N#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
N#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
N#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
N
N#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
N#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
N#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
N#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
N#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
N#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
N
N#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
N#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
N#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
N#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
N#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
N#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
N#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
N
N#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
N#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
N#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
N#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
N#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
N#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
N
N/******************  Bit definition for FSMC_PMEM4 register  ******************/
N#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
N#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
N#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
N#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
N
N#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
N#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
N#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
N#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
N#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
N#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
N
N#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
N#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
N#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
N#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
N#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
N#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
N#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
N
N#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
N#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
N#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
N#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
N#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
N#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
N
N/******************  Bit definition for FSMC_PATT2 register  ******************/
N#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
N#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
N#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
N#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
N
N#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
N#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
N#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
N#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
N#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
N#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
N
N#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
N#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
N#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
N#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
N#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
N#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
N#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
N
N#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
N#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
N#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
N#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
N#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
N#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
N
N/******************  Bit definition for FSMC_PATT3 register  ******************/
N#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
N#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
N#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
N#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
N
N#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
N#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
N#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
N#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
N#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
N#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
N
N#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
N#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
N#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
N#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
N#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
N#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
N#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
N
N#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
N#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
N#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
N#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
N#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
N#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
N
N/******************  Bit definition for FSMC_PATT4 register  ******************/
N#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
N#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
N#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
N#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
N
N#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
N#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
N#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
N#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
N#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
N#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
N
N#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
N#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
N#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
N#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
N#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
N#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
N#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
N
N#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
N#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
N#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
N#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
N#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
N#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
N
N/******************  Bit definition for FSMC_PIO4 register  *******************/
N#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
N#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
N#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
N#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
N
N#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
N#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
N#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
N#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
N#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
N#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
N
N#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
N#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
N#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
N#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
N#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
N#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
N#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
N#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
N#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
N
N#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
N#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
N#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
N#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
N#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
N#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
N#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
N#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
N#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
N
N/******************  Bit definition for FSMC_ECCR2 register  ******************/
N#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
N
N/******************  Bit definition for FSMC_ECCR3 register  ******************/
N#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
X#if 0L || 0L
S/******************************************************************************/
S/*                                                                            */
S/*                          Flexible Memory Controller                        */
S/*                                                                            */
S/******************************************************************************/
S/******************  Bit definition for FMC_BCR1 register  *******************/
S#define  FMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
S#define  FMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
S
S#define  FMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
S#define  FMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
S#define  FMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
S#define  FMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
S#define  FMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
S#define  FMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
S#define  FMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
S#define  FMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
S#define  FMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
S#define  FMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
S#define  FMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
S#define  FMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
S#define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000)        /*!<Continous clock enable     */
S
S/******************  Bit definition for FMC_BCR2 register  *******************/
S#define  FMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
S#define  FMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
S
S#define  FMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
S#define  FMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
S#define  FMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
S#define  FMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
S#define  FMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
S#define  FMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
S#define  FMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
S#define  FMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
S#define  FMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
S#define  FMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
S#define  FMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
S#define  FMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
S
S/******************  Bit definition for FMC_BCR3 register  *******************/
S#define  FMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
S#define  FMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
S
S#define  FMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
S#define  FMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
S#define  FMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
S#define  FMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
S#define  FMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
S#define  FMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
S#define  FMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
S#define  FMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
S#define  FMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
S#define  FMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
S#define  FMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
S#define  FMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
S
S/******************  Bit definition for FMC_BCR4 register  *******************/
S#define  FMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
S#define  FMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
S
S#define  FMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
S#define  FMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
S#define  FMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
S#define  FMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
S#define  FMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
S#define  FMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
S#define  FMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
S#define  FMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
S#define  FMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
S#define  FMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
S#define  FMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
S#define  FMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
S
S/******************  Bit definition for FMC_BTR1 register  ******************/
S#define  FMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
S#define  FMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BTR1_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BTR1_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BTR1_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BTR1_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
S#define  FMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_BTR2 register  *******************/
S#define  FMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BTR2_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BTR2_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BTR2_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BTR2_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
S#define  FMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/*******************  Bit definition for FMC_BTR3 register  *******************/
S#define  FMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BTR3_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BTR3_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BTR3_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BTR3_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
S#define  FMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_BTR4 register  *******************/
S#define  FMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BTR4_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BTR4_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BTR4_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BTR4_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
S#define  FMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_BWTR1 register  ******************/
S#define  FMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_BWTR2 register  ******************/
S#define  FMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
S#define  FMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_BWTR3 register  ******************/
S#define  FMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_BWTR4 register  ******************/
S#define  FMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_PCR2 register  *******************/
S#define  FMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
S#define  FMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
S#define  FMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
S
S#define  FMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
S#define  FMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
S
S#define  FMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
S#define  FMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
S#define  FMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
S#define  FMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
S#define  FMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
S
S#define  FMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
S#define  FMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
S#define  FMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
S#define  FMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
S
S#define  FMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size)           */
S#define  FMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
S#define  FMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
S#define  FMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
S
S/******************  Bit definition for FMC_PCR3 register  *******************/
S#define  FMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
S#define  FMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
S#define  FMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
S
S#define  FMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
S#define  FMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
S
S#define  FMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
S#define  FMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
S#define  FMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
S#define  FMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
S#define  FMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
S
S#define  FMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
S#define  FMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
S#define  FMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
S#define  FMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
S
S#define  FMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
S#define  FMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
S#define  FMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
S#define  FMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
S
S/******************  Bit definition for FMC_PCR4 register  *******************/
S#define  FMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
S#define  FMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
S#define  FMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
S
S#define  FMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
S#define  FMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
S
S#define  FMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
S#define  FMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
S#define  FMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
S#define  FMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
S#define  FMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
S
S#define  FMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
S#define  FMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
S#define  FMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
S#define  FMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
S
S#define  FMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
S#define  FMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
S#define  FMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
S#define  FMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
S
S/*******************  Bit definition for FMC_SR2 register  *******************/
S#define  FMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
S#define  FMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
S#define  FMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
S#define  FMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
S#define  FMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
S#define  FMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
S#define  FMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
S
S/*******************  Bit definition for FMC_SR3 register  *******************/
S#define  FMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
S#define  FMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
S#define  FMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
S#define  FMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
S#define  FMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
S#define  FMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
S#define  FMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
S
S/*******************  Bit definition for FMC_SR4 register  *******************/
S#define  FMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
S#define  FMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
S#define  FMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
S#define  FMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
S#define  FMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
S#define  FMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
S#define  FMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
S
S/******************  Bit definition for FMC_PMEM2 register  ******************/
S#define  FMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
S#define  FMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
S#define  FMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
S#define  FMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
S#define  FMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_PMEM3 register  ******************/
S#define  FMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
S#define  FMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
S#define  FMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
S#define  FMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
S#define  FMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_PMEM4 register  ******************/
S#define  FMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
S#define  FMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
S#define  FMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
S#define  FMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
S#define  FMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_PATT2 register  ******************/
S#define  FMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
S#define  FMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
S#define  FMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
S#define  FMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
S#define  FMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_PATT3 register  ******************/
S#define  FMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
S#define  FMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
S#define  FMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
S#define  FMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
S#define  FMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_PATT4 register  ******************/
S#define  FMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
S#define  FMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
S#define  FMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
S#define  FMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
S#define  FMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_PIO4 register  *******************/
S#define  FMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
S#define  FMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
S#define  FMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
S#define  FMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
S#define  FMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_ECCR2 register  ******************/
S#define  FMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
S
S/******************  Bit definition for FMC_ECCR3 register  ******************/
S#define  FMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
S
S/******************  Bit definition for FMC_SDCR1 register  ******************/
S#define  FMC_SDCR1_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
S#define  FMC_SDCR1_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_SDCR1_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
S
S#define  FMC_SDCR1_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
S#define  FMC_SDCR1_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FMC_SDCR1_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FMC_SDCR1_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
S#define  FMC_SDCR1_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_SDCR1_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_SDCR1_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
S
S#define  FMC_SDCR1_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
S#define  FMC_SDCR1_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
S#define  FMC_SDCR1_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
S
S#define  FMC_SDCR1_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
S
S#define  FMC_SDCR1_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDRAM clock configuration */
S#define  FMC_SDCR1_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
S#define  FMC_SDCR1_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
S
S#define  FMC_SDCR1_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
S
S#define  FMC_SDCR1_RPIPE                    ((uint32_t)0x00006000)        /*!<Write protection */
S#define  FMC_SDCR1_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FMC_SDCR1_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_SDCR2 register  ******************/
S#define  FMC_SDCR2_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
S#define  FMC_SDCR2_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_SDCR2_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
S
S#define  FMC_SDCR2_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
S#define  FMC_SDCR2_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FMC_SDCR2_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FMC_SDCR2_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
S#define  FMC_SDCR2_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_SDCR2_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_SDCR2_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
S
S#define  FMC_SDCR2_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
S#define  FMC_SDCR2_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
S#define  FMC_SDCR2_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
S
S#define  FMC_SDCR2_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
S
S#define  FMC_SDCR2_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDCLK[1:0] (SDRAM clock configuration) */
S#define  FMC_SDCR2_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
S#define  FMC_SDCR2_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
S
S#define  FMC_SDCR2_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
S
S#define  FMC_SDCR2_RPIPE                    ((uint32_t)0x00006000)        /*!<RPIPE[1:0](Read pipe) */
S#define  FMC_SDCR2_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FMC_SDCR2_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_SDTR1 register  ******************/
S#define  FMC_SDTR1_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
S#define  FMC_SDTR1_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_SDTR1_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_SDTR1_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_SDTR1_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
S                                            
S#define  FMC_SDTR1_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
S#define  FMC_SDTR1_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_SDTR1_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_SDTR1_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_SDTR1_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_SDTR1_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
S#define  FMC_SDTR1_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_SDTR1_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_SDTR1_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_SDTR1_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  FMC_SDTR1_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
S#define  FMC_SDTR1_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
S#define  FMC_SDTR1_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
S#define  FMC_SDTR1_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
S
S#define  FMC_SDTR1_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
S#define  FMC_SDTR1_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_SDTR1_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_SDTR1_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
S
S#define  FMC_SDTR1_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
S#define  FMC_SDTR1_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_SDTR1_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_SDTR1_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
S
S#define  FMC_SDTR1_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
S#define  FMC_SDTR1_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_SDTR1_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_SDTR1_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
S
S/******************  Bit definition for FMC_SDTR2 register  ******************/
S#define  FMC_SDTR2_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
S#define  FMC_SDTR2_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_SDTR2_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_SDTR2_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_SDTR2_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
S                                            
S#define  FMC_SDTR2_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
S#define  FMC_SDTR2_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_SDTR2_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_SDTR2_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_SDTR2_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_SDTR2_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
S#define  FMC_SDTR2_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_SDTR2_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_SDTR2_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_SDTR2_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  FMC_SDTR2_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
S#define  FMC_SDTR2_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
S#define  FMC_SDTR2_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
S#define  FMC_SDTR2_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
S
S#define  FMC_SDTR2_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
S#define  FMC_SDTR2_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_SDTR2_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_SDTR2_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
S
S#define  FMC_SDTR2_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
S#define  FMC_SDTR2_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_SDTR2_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_SDTR2_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
S
S#define  FMC_SDTR2_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
S#define  FMC_SDTR2_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_SDTR2_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_SDTR2_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
S
S/******************  Bit definition for FMC_SDCMR register  ******************/
S#define  FMC_SDCMR_MODE                     ((uint32_t)0x00000007)        /*!<MODE[2:0] bits (Command mode) */
S#define  FMC_SDCMR_MODE_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_SDCMR_MODE_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_SDCMR_MODE_2                   ((uint32_t)0x00000003)        /*!<Bit 2 */
S                                            
S#define  FMC_SDCMR_CTB2                     ((uint32_t)0x00000008)        /*!<Command target 2 */
S
S#define  FMC_SDCMR_CTB1                     ((uint32_t)0x00000010)        /*!<Command target 1 */
S
S#define  FMC_SDCMR_NRFS                     ((uint32_t)0x000001E0)        /*!<NRFS[3:0] bits (Number of auto-refresh) */
S#define  FMC_SDCMR_NRFS_0                   ((uint32_t)0x00000020)        /*!<Bit 0 */
S#define  FMC_SDCMR_NRFS_1                   ((uint32_t)0x00000040)        /*!<Bit 1 */
S#define  FMC_SDCMR_NRFS_2                   ((uint32_t)0x00000080)        /*!<Bit 2 */
S#define  FMC_SDCMR_NRFS_3                   ((uint32_t)0x00000100)        /*!<Bit 3 */
S
S#define  FMC_SDCMR_MRD                      ((uint32_t)0x003FFE00)        /*!<MRD[12:0] bits (Mode register definition) */
S
S/******************  Bit definition for FMC_SDRTR register  ******************/
S#define  FMC_SDRTR_CRE                      ((uint32_t)0x00000001)        /*!<Clear refresh error flag */
S
S#define  FMC_SDRTR_COUNT                    ((uint32_t)0x00003FFE)        /*!<COUNT[12:0] bits (Refresh timer count) */
S
S#define  FMC_SDRTR_REIE                     ((uint32_t)0x00004000)        /*!<RES interupt enable */
S
S/******************  Bit definition for FMC_SDSR register  ******************/
S#define  FMC_SDSR_RE                        ((uint32_t)0x00000001)        /*!<Refresh error flag */
S
S#define  FMC_SDSR_MODES1                    ((uint32_t)0x00000006)        /*!<MODES1[1:0]bits (Status mode for bank 1) */
S#define  FMC_SDSR_MODES1_0                  ((uint32_t)0x00000002)        /*!<Bit 0 */
S#define  FMC_SDSR_MODES1_1                  ((uint32_t)0x00000004)        /*!<Bit 1 */
S
S#define  FMC_SDSR_MODES2                    ((uint32_t)0x00000018)        /*!<MODES2[1:0]bits (Status mode for bank 2) */
S#define  FMC_SDSR_MODES2_0                  ((uint32_t)0x00000008)        /*!<Bit 0 */
S#define  FMC_SDSR_MODES2_1                  ((uint32_t)0x00000010)        /*!<Bit 1 */
S
S#define  FMC_SDSR_BUSY                      ((uint32_t)0x00000020)        /*!<Busy status */
S
N#endif /* STM32F427_437xx ||  STM32F429_439xx */
N
N/******************************************************************************/
N/*                                                                            */
N/*                            General Purpose I/O                             */
N/*                                                                            */
N/******************************************************************************/
N/******************  Bits definition for GPIO_MODER register  *****************/
N#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
N#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
N#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
N
N#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
N#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
N#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
N
N#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
N#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
N#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
N
N#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
N#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
N#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
N
N#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
N#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
N#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
N
N#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
N#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
N#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
N
N#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
N#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
N#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
N
N#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
N#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
N#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
N
N#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
N#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
N#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
N
N#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
N#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
N#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
N
N#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
N#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
N#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
N
N#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
N#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
N#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
N
N#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
N#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
N#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
N
N#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
N#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
N#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
N
N#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
N#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
N#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
N
N#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
N#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
N#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
N
N/******************  Bits definition for GPIO_OTYPER register  ****************/
N#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
N#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
N#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
N#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
N#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
N#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
N#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
N#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
N#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
N#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
N#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
N#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
N#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
N#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
N#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
N#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
N
N/******************  Bits definition for GPIO_OSPEEDR register  ***************/
N#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
N#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
N#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
N
N#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
N#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
N#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
N
N#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
N#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
N#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
N
N#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
N#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
N#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
N
N#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
N#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
N#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
N
N#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
N#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
N#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
N
N#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
N#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
N#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
N
N#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
N#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
N#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
N
N#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
N#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
N#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
N
N#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
N#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
N#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
N
N#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
N#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
N#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
N
N#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
N#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
N#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
N
N#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
N#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
N#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
N
N#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
N#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
N#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
N
N#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
N#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
N#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
N
N#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
N#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
N#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
N
N/******************  Bits definition for GPIO_PUPDR register  *****************/
N#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
N#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
N#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
N
N#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
N#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
N#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
N
N#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
N#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
N#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
N
N#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
N#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
N#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
N
N#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
N#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
N#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
N
N#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
N#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
N#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
N
N#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
N#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
N#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
N
N#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
N#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
N#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
N
N#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
N#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
N#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
N
N#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
N#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
N#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
N
N#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
N#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
N#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
N
N#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
N#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
N#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
N
N#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
N#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
N#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
N
N#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
N#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
N#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
N
N#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
N#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
N#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
N
N#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
N#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
N#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
N
N/******************  Bits definition for GPIO_IDR register  *******************/
N#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
N#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
N#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
N#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
N#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
N#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
N#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
N#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
N#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
N#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
N#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
N#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
N#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
N#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
N#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
N#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
N/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
N#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
N#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
N#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
N#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
N#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
N#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
N#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
N#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
N#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
N#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
N#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
N#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
N#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
N#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
N#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
N#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
N
N/******************  Bits definition for GPIO_ODR register  *******************/
N#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
N#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
N#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
N#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
N#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
N#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
N#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
N#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
N#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
N#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
N#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
N#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
N#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
N#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
N#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
N#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
N/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
N#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
N#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
N#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
N#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
N#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
N#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
N#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
N#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
N#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
N#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
N#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
N#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
N#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
N#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
N#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
N#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
N
N/******************  Bits definition for GPIO_BSRR register  ******************/
N#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
N#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
N#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
N#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
N#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
N#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
N#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
N#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
N#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
N#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
N#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
N#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
N#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
N#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
N#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
N#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
N#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
N#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
N#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
N#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
N#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
N#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
N#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
N#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
N#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
N#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
N#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
N#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
N#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
N#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
N#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
N#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
N
N/******************************************************************************/
N/*                                                                            */
N/*                                    HASH                                    */
N/*                                                                            */
N/******************************************************************************/
N/******************  Bits definition for HASH_CR register  ********************/
N#define HASH_CR_INIT                         ((uint32_t)0x00000004)
N#define HASH_CR_DMAE                         ((uint32_t)0x00000008)
N#define HASH_CR_DATATYPE                     ((uint32_t)0x00000030)
N#define HASH_CR_DATATYPE_0                   ((uint32_t)0x00000010)
N#define HASH_CR_DATATYPE_1                   ((uint32_t)0x00000020)
N#define HASH_CR_MODE                         ((uint32_t)0x00000040)
N#define HASH_CR_ALGO                         ((uint32_t)0x00040080)
N#define HASH_CR_ALGO_0                       ((uint32_t)0x00000080)
N#define HASH_CR_ALGO_1                       ((uint32_t)0x00040000)
N#define HASH_CR_NBW                          ((uint32_t)0x00000F00)
N#define HASH_CR_NBW_0                        ((uint32_t)0x00000100)
N#define HASH_CR_NBW_1                        ((uint32_t)0x00000200)
N#define HASH_CR_NBW_2                        ((uint32_t)0x00000400)
N#define HASH_CR_NBW_3                        ((uint32_t)0x00000800)
N#define HASH_CR_DINNE                        ((uint32_t)0x00001000)
N#define HASH_CR_MDMAT                        ((uint32_t)0x00002000)
N#define HASH_CR_LKEY                         ((uint32_t)0x00010000)
N
N/******************  Bits definition for HASH_STR register  *******************/
N#define HASH_STR_NBW                         ((uint32_t)0x0000001F)
N#define HASH_STR_NBW_0                       ((uint32_t)0x00000001)
N#define HASH_STR_NBW_1                       ((uint32_t)0x00000002)
N#define HASH_STR_NBW_2                       ((uint32_t)0x00000004)
N#define HASH_STR_NBW_3                       ((uint32_t)0x00000008)
N#define HASH_STR_NBW_4                       ((uint32_t)0x00000010)
N#define HASH_STR_DCAL                        ((uint32_t)0x00000100)
N
N/******************  Bits definition for HASH_IMR register  *******************/
N#define HASH_IMR_DINIM                       ((uint32_t)0x00000001)
N#define HASH_IMR_DCIM                        ((uint32_t)0x00000002)
N
N/******************  Bits definition for HASH_SR register  ********************/
N#define HASH_SR_DINIS                        ((uint32_t)0x00000001)
N#define HASH_SR_DCIS                         ((uint32_t)0x00000002)
N#define HASH_SR_DMAS                         ((uint32_t)0x00000004)
N#define HASH_SR_BUSY                         ((uint32_t)0x00000008)
N
N/******************************************************************************/
N/*                                                                            */
N/*                      Inter-integrated Circuit Interface                    */
N/*                                                                            */
N/******************************************************************************/
N/*******************  Bit definition for I2C_CR1 register  ********************/
N#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!<Peripheral Enable                             */
N#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!<SMBus Mode                                    */
N#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!<SMBus Type                                    */
N#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!<ARP Enable                                    */
N#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!<PEC Enable                                    */
N#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!<General Call Enable                           */
N#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!<Clock Stretching Disable (Slave mode)         */
N#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!<Start Generation                              */
N#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!<Stop Generation                               */
N#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!<Acknowledge Enable                            */
N#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!<Acknowledge/PEC Position (for data reception) */
N#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!<Packet Error Checking                         */
N#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!<SMBus Alert                                   */
N#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!<Software Reset                                */
N
N/*******************  Bit definition for I2C_CR2 register  ********************/
N#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
N#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
N#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
N#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
N#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
N#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
N#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
N
N#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!<Error Interrupt Enable  */
N#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!<Event Interrupt Enable  */
N#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!<Buffer Interrupt Enable */
N#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!<DMA Requests Enable     */
N#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!<DMA Last Transfer       */
N
N/*******************  Bit definition for I2C_OAR1 register  *******************/
N#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!<Interface Address */
N#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!<Interface Address */
N
N#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!<Bit 0 */
N#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!<Bit 1 */
N#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!<Bit 2 */
N#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!<Bit 3 */
N#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!<Bit 4 */
N#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!<Bit 5 */
N#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!<Bit 6 */
N#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!<Bit 7 */
N#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!<Bit 8 */
N#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!<Bit 9 */
N
N#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!<Addressing Mode (Slave mode) */
N
N/*******************  Bit definition for I2C_OAR2 register  *******************/
N#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!<Dual addressing mode enable */
N#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!<Interface address           */
N
N/********************  Bit definition for I2C_DR register  ********************/
N#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!<8-bit Data Register         */
N
N/*******************  Bit definition for I2C_SR1 register  ********************/
N#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!<Start Bit (Master mode)                         */
N#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!<Address sent (master mode)/matched (slave mode) */
N#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!<Byte Transfer Finished                          */
N#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!<10-bit header sent (Master mode)                */
N#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!<Stop detection (Slave mode)                     */
N#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!<Data Register not Empty (receivers)             */
N#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!<Data Register Empty (transmitters)              */
N#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!<Bus Error                                       */
N#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!<Arbitration Lost (master mode)                  */
N#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!<Acknowledge Failure                             */
N#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!<Overrun/Underrun                                */
N#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!<PEC Error in reception                          */
N#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!<Timeout or Tlow Error                           */
N#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!<SMBus Alert                                     */
N
N/*******************  Bit definition for I2C_SR2 register  ********************/
N#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!<Master/Slave                              */
N#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!<Bus Busy                                  */
N#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!<Transmitter/Receiver                      */
N#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!<General Call Address (Slave mode)         */
N#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!<SMBus Device Default Address (Slave mode) */
N#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!<SMBus Host Header (Slave mode)            */
N#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!<Dual Flag (Slave mode)                    */
N#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!<Packet Error Checking Register            */
N
N/*******************  Bit definition for I2C_CCR register  ********************/
N#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!<Clock Control Register in Fast/Standard mode (Master mode) */
N#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!<Fast Mode Duty Cycle                                       */
N#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!<I2C Master Mode Selection                                  */
N
N/******************  Bit definition for I2C_TRISE register  *******************/
N#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
N
N/******************  Bit definition for I2C_FLTR register  *******************/
N#define  I2C_FLTR_DNF                     ((uint8_t)0x0F)                  /*!<Digital Noise Filter */
N#define  I2C_FLTR_ANOFF                   ((uint8_t)0x10)                  /*!<Analog Noise Filter OFF */
N
N/******************************************************************************/
N/*                                                                            */
N/*                           Independent WATCHDOG                             */
N/*                                                                            */
N/******************************************************************************/
N/*******************  Bit definition for IWDG_KR register  ********************/
N#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!<Key value (write only, read 0000h)  */
N
N/*******************  Bit definition for IWDG_PR register  ********************/
N#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!<PR[2:0] (Prescaler divider)         */
N#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!<Bit 0 */
N#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!<Bit 1 */
N#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!<Bit 2 */
N
N/*******************  Bit definition for IWDG_RLR register  *******************/
N#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!<Watchdog counter reload value        */
N
N/*******************  Bit definition for IWDG_SR register  ********************/
N#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!<Watchdog prescaler value update      */
N#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!<Watchdog counter reload value update */
N
N/******************************************************************************/
N/*                                                                            */
N/*                      LCD-TFT Display Controller (LTDC)                     */
N/*                                                                            */
N/******************************************************************************/
N
N/********************  Bit definition for LTDC_SSCR register  *****************/
N
N#define LTDC_SSCR_VSH                       ((uint32_t)0x000007FF)              /*!< Vertical Synchronization Height */
N#define LTDC_SSCR_HSW                       ((uint32_t)0x0FFF0000)              /*!< Horizontal Synchronization Width */
N
N/********************  Bit definition for LTDC_BPCR register  *****************/
N
N#define LTDC_BPCR_AVBP                      ((uint32_t)0x000007FF)              /*!< Accumulated Vertical Back Porch */
N#define LTDC_BPCR_AHBP                      ((uint32_t)0x0FFF0000)              /*!< Accumulated Horizontal Back Porch */
N
N/********************  Bit definition for LTDC_AWCR register  *****************/
N
N#define LTDC_AWCR_AAH                       ((uint32_t)0x000007FF)              /*!< Accumulated Active heigh */
N#define LTDC_AWCR_AAW                       ((uint32_t)0x0FFF0000)              /*!< Accumulated Active Width */
N
N/********************  Bit definition for LTDC_TWCR register  *****************/
N
N#define LTDC_TWCR_TOTALH                    ((uint32_t)0x000007FF)              /*!< Total Heigh */
N#define LTDC_TWCR_TOTALW                    ((uint32_t)0x0FFF0000)              /*!< Total Width */
N
N/********************  Bit definition for LTDC_GCR register  ******************/
N
N#define LTDC_GCR_LTDCEN                     ((uint32_t)0x00000001)              /*!< LCD-TFT controller enable bit */
N#define LTDC_GCR_DBW                        ((uint32_t)0x00000070)              /*!< Dither Blue Width */
N#define LTDC_GCR_DGW                        ((uint32_t)0x00000700)              /*!< Dither Green Width */
N#define LTDC_GCR_DRW                        ((uint32_t)0x00007000)              /*!< Dither Red Width */
N#define LTDC_GCR_DTEN                       ((uint32_t)0x00010000)              /*!< Dither Enable */
N#define LTDC_GCR_PCPOL                      ((uint32_t)0x10000000)              /*!< Pixel Clock Polarity */
N#define LTDC_GCR_DEPOL                      ((uint32_t)0x20000000)              /*!< Data Enable Polarity */
N#define LTDC_GCR_VSPOL                      ((uint32_t)0x40000000)              /*!< Vertical Synchronization Polarity */
N#define LTDC_GCR_HSPOL                      ((uint32_t)0x80000000)              /*!< Horizontal Synchronization Polarity */
N
N/********************  Bit definition for LTDC_SRCR register  *****************/
N
N#define LTDC_SRCR_IMR                      ((uint32_t)0x00000001)               /*!< Immediate Reload */
N#define LTDC_SRCR_VBR                      ((uint32_t)0x00000002)               /*!< Vertical Blanking Reload */
N
N/********************  Bit definition for LTDC_BCCR register  *****************/
N
N#define LTDC_BCCR_BCBLUE                    ((uint32_t)0x000000FF)              /*!< Background Blue value */
N#define LTDC_BCCR_BCGREEN                   ((uint32_t)0x0000FF00)              /*!< Background Green value */
N#define LTDC_BCCR_BCRED                     ((uint32_t)0x00FF0000)              /*!< Background Red value */
N
N/********************  Bit definition for LTDC_IER register  ******************/
N
N#define LTDC_IER_LIE                        ((uint32_t)0x00000001)              /*!< Line Interrupt Enable */
N#define LTDC_IER_FUIE                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Enable */
N#define LTDC_IER_TERRIE                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Enable */
N#define LTDC_IER_RRIE                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt enable */
N
N/********************  Bit definition for LTDC_ISR register  ******************/
N
N#define LTDC_ISR_LIF                        ((uint32_t)0x00000001)              /*!< Line Interrupt Flag */
N#define LTDC_ISR_FUIF                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Flag */
N#define LTDC_ISR_TERRIF                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Flag */
N#define LTDC_ISR_RRIF                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt Flag */
N
N/********************  Bit definition for LTDC_ICR register  ******************/
N
N#define LTDC_ICR_CLIF                       ((uint32_t)0x00000001)              /*!< Clears the Line Interrupt Flag */
N#define LTDC_ICR_CFUIF                      ((uint32_t)0x00000002)              /*!< Clears the FIFO Underrun Interrupt Flag */
N#define LTDC_ICR_CTERRIF                    ((uint32_t)0x00000004)              /*!< Clears the Transfer Error Interrupt Flag */
N#define LTDC_ICR_CRRIF                      ((uint32_t)0x00000008)              /*!< Clears Register Reload interrupt Flag */
N
N/********************  Bit definition for LTDC_LIPCR register  ****************/
N
N#define LTDC_LIPCR_LIPOS                    ((uint32_t)0x000007FF)              /*!< Line Interrupt Position */
N
N/********************  Bit definition for LTDC_CPSR register  *****************/
N
N#define LTDC_CPSR_CYPOS                     ((uint32_t)0x0000FFFF)              /*!< Current Y Position */
N#define LTDC_CPSR_CXPOS                     ((uint32_t)0xFFFF0000)              /*!< Current X Position */
N
N/********************  Bit definition for LTDC_CDSR register  *****************/
N
N#define LTDC_CDSR_VDES                      ((uint32_t)0x00000001)              /*!< Vertical Data Enable Status */
N#define LTDC_CDSR_HDES                      ((uint32_t)0x00000002)              /*!< Horizontal Data Enable Status */
N#define LTDC_CDSR_VSYNCS                    ((uint32_t)0x00000004)              /*!< Vertical Synchronization Status */
N#define LTDC_CDSR_HSYNCS                    ((uint32_t)0x00000008)              /*!< Horizontal Synchronization Status */
N
N/********************  Bit definition for LTDC_LxCR register  *****************/
N
N#define LTDC_LxCR_LEN                       ((uint32_t)0x00000001)              /*!< Layer Enable */
N#define LTDC_LxCR_COLKEN                    ((uint32_t)0x00000002)              /*!< Color Keying Enable */
N#define LTDC_LxCR_CLUTEN                    ((uint32_t)0x00000010)              /*!< Color Lockup Table Enable */
N
N/********************  Bit definition for LTDC_LxWHPCR register  **************/
N
N#define LTDC_LxWHPCR_WHSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Horizontal Start Position */
N#define LTDC_LxWHPCR_WHSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Horizontal Stop Position */
N
N/********************  Bit definition for LTDC_LxWVPCR register  **************/
N
N#define LTDC_LxWVPCR_WVSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Vertical Start Position */
N#define LTDC_LxWVPCR_WVSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Vertical Stop Position */
N
N/********************  Bit definition for LTDC_LxCKCR register  ***************/
N
N#define LTDC_LxCKCR_CKBLUE                  ((uint32_t)0x000000FF)              /*!< Color Key Blue value */
N#define LTDC_LxCKCR_CKGREEN                 ((uint32_t)0x0000FF00)              /*!< Color Key Green value */
N#define LTDC_LxCKCR_CKRED                   ((uint32_t)0x00FF0000)              /*!< Color Key Red value */
N
N/********************  Bit definition for LTDC_LxPFCR register  ***************/
N
N#define LTDC_LxPFCR_PF                      ((uint32_t)0x00000007)              /*!< Pixel Format */
N
N/********************  Bit definition for LTDC_LxCACR register  ***************/
N
N#define LTDC_LxCACR_CONSTA                  ((uint32_t)0x000000FF)              /*!< Constant Alpha */
N
N/********************  Bit definition for LTDC_LxDCCR register  ***************/
N
N#define LTDC_LxDCCR_DCBLUE                  ((uint32_t)0x000000FF)              /*!< Default Color Blue */
N#define LTDC_LxDCCR_DCGREEN                 ((uint32_t)0x0000FF00)              /*!< Default Color Green */
N#define LTDC_LxDCCR_DCRED                   ((uint32_t)0x00FF0000)              /*!< Default Color Red */
N#define LTDC_LxDCCR_DCALPHA                 ((uint32_t)0xFF000000)              /*!< Default Color Alpha */
N                                
N/********************  Bit definition for LTDC_LxBFCR register  ***************/
N
N#define LTDC_LxBFCR_BF2                     ((uint32_t)0x00000007)              /*!< Blending Factor 2 */
N#define LTDC_LxBFCR_BF1                     ((uint32_t)0x00000700)              /*!< Blending Factor 1 */
N
N/********************  Bit definition for LTDC_LxCFBAR register  **************/
N
N#define LTDC_LxCFBAR_CFBADD                 ((uint32_t)0xFFFFFFFF)              /*!< Color Frame Buffer Start Address */
N
N/********************  Bit definition for LTDC_LxCFBLR register  **************/
N
N#define LTDC_LxCFBLR_CFBLL                  ((uint32_t)0x00001FFF)              /*!< Color Frame Buffer Line Length */
N#define LTDC_LxCFBLR_CFBP                   ((uint32_t)0x1FFF0000)              /*!< Color Frame Buffer Pitch in bytes */
N
N/********************  Bit definition for LTDC_LxCFBLNR register  *************/
N
N#define LTDC_LxCFBLNR_CFBLNBR               ((uint32_t)0x000007FF)              /*!< Frame Buffer Line Number */
N
N/********************  Bit definition for LTDC_LxCLUTWR register  *************/
N
N#define LTDC_LxCLUTWR_BLUE                  ((uint32_t)0x000000FF)              /*!< Blue value */
N#define LTDC_LxCLUTWR_GREEN                 ((uint32_t)0x0000FF00)              /*!< Green value */
N#define LTDC_LxCLUTWR_RED                   ((uint32_t)0x00FF0000)              /*!< Red value */
N#define LTDC_LxCLUTWR_CLUTADD               ((uint32_t)0xFF000000)              /*!< CLUT address */
N
N/******************************************************************************/
N/*                                                                            */
N/*                             Power Control                                  */
N/*                                                                            */
N/******************************************************************************/
N/********************  Bit definition for PWR_CR register  ********************/
N#define  PWR_CR_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep                 */
N#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep                */
N#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag                   */
N#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag                  */
N#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable       */
N
N#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
N#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
N#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
N#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
N
N/*!< PVD level configuration */
N#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
N#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
N#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
N#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
N#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
N#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
N#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
N#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
N
N#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection                     */
N#define  PWR_CR_FPDS                         ((uint32_t)0x00000200)     /*!< Flash power down in Stop mode                              */
N#define  PWR_CR_LPUDS                        ((uint32_t)0x00000400)     /*!< Low-Power Regulator in Stop under-drive mode               */
N#define  PWR_CR_MRUDS                        ((uint32_t)0x00000800)     /*!< Main regulator in Stop under-drive mode                    */
N#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400)     /*!< Low-power regulator Low Voltage in Deep Sleep mode         */
N#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800)     /*!< Main regulator Low Voltage in Deep Sleep mode              */
N
N#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000)     /*!< Refer to AN4073 on how to use this bit */ 
N
N#define  PWR_CR_VOS                          ((uint32_t)0x0000C000)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
N#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000)     /*!< Bit 0 */
N#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000)     /*!< Bit 1 */
N
N#define  PWR_CR_ODEN                         ((uint32_t)0x00010000)     /*!< Over Drive enable                   */
N#define  PWR_CR_ODSWEN                       ((uint32_t)0x00020000)     /*!< Over Drive switch enabled           */
N#define  PWR_CR_UDEN                         ((uint32_t)0x000C0000)     /*!< Under Drive enable in stop mode     */
N#define  PWR_CR_UDEN_0                       ((uint32_t)0x00040000)     /*!< Bit 0                               */
N#define  PWR_CR_UDEN_1                       ((uint32_t)0x00080000)     /*!< Bit 1                               */
N
N#define  PWR_CR_FMSSR                        ((uint32_t)0x00100000)     /*!< Flash Memory Sleep System Run        */
N#define  PWR_CR_FISSR                        ((uint32_t)0x00200000)     /*!< Flash Interface Stop while System Run */
N
N/* Legacy define */
N#define  PWR_CR_PMODE                        PWR_CR_VOS
N
N/*******************  Bit definition for PWR_CSR register  ********************/
N#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag                                      */
N#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag                                     */
N#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output                                       */
N#define  PWR_CSR_BRR                         ((uint32_t)0x00000008)     /*!< Backup regulator ready                           */
N#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100)     /*!< Enable WKUP pin                                  */
N#define  PWR_CSR_BRE                         ((uint32_t)0x00000200)     /*!< Backup regulator enable                          */
N#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000)     /*!< Regulator voltage scaling output selection ready */
N#define  PWR_CSR_ODRDY                       ((uint32_t)0x00010000)     /*!< Over Drive generator ready                       */
N#define  PWR_CSR_ODSWRDY                     ((uint32_t)0x00020000)     /*!< Over Drive Switch ready                          */
N#define  PWR_CSR_UDSWRDY                     ((uint32_t)0x000C0000)     /*!< Under Drive ready                                */
N
N/* Legacy define */
N#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
N
N/******************************************************************************/
N/*                                                                            */
N/*                         Reset and Clock Control                            */
N/*                                                                            */
N/******************************************************************************/
N/********************  Bit definition for RCC_CR register  ********************/
N#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
N#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
N
N#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
N#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
N#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
N#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
N#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
N#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
N
N#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
N#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
N#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
N#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
N#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
N#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
N#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
N#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
N#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
N
N#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
N#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
N#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
N#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
N#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
N#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
N#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)
N#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)
N#define  RCC_CR_PLLSAION                     ((uint32_t)0x10000000)
N#define  RCC_CR_PLLSAIRDY                    ((uint32_t)0x20000000)
N
N/********************  Bit definition for RCC_PLLCFGR register  ***************/
N#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
N#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
N#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
N#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
N#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
N#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
N#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
N
N#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
N#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
N#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
N#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
N#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
N#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
N#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
N#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
N#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
N#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
N
N#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
N#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
N#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
N
N#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
N#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
N#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
N
N#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
N#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
N#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
N#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
N#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
N
N/********************  Bit definition for RCC_CFGR register  ******************/
N/*!< SW configuration */
N#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
N#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
N#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
N
N#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
N#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
N#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
N
N/*!< SWS configuration */
N#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
N#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
N#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
N
N#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
N#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
N#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
N
N/*!< HPRE configuration */
N#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
N#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
N#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
N#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
N#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
N
N#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
N#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
N#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
N#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
N#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
N#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
N#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
N#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
N#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
N
N/*!< PPRE1 configuration */
N#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
N#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
N#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
N#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
N
N#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
N#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
N#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
N#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
N#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
N
N/*!< PPRE2 configuration */
N#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
N#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
N#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
N#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
N
N#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
N#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
N#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
N#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
N#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        /*!< HCLK divided by 16 */
N
N/*!< RTCPRE configuration */
N#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
N#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
N#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
N#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
N#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
N#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
N
N/*!< MCO1 configuration */
N#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
N#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
N#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
N
N#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)
N
N#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
N#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
N#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
N#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
N
N#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
N#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
N#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
N#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
N
N#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
N#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
N#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
N
N/********************  Bit definition for RCC_CIR register  *******************/
N#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
N#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
N#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
N#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
N#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
N#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)
N#define  RCC_CIR_PLLSAIRDYF                  ((uint32_t)0x00000040)
N#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
N#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
N#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
N#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
N#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
N#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
N#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)
N#define  RCC_CIR_PLLSAIRDYIE                 ((uint32_t)0x00004000)
N#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
N#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
N#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
N#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
N#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
N#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)
N#define  RCC_CIR_PLLSAIRDYC                  ((uint32_t)0x00400000)
N#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
N
N/********************  Bit definition for RCC_AHB1RSTR register  **************/
N#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
N#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
N#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
N#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)
N#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)
N#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020)
N#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040)
N#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
N#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100)
N#define  RCC_AHB1RSTR_GPIOJRST               ((uint32_t)0x00000200)
N#define  RCC_AHB1RSTR_GPIOKRST               ((uint32_t)0x00000400)
N#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
N#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
N#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
N#define  RCC_AHB1RSTR_DMA2DRST               ((uint32_t)0x00800000)
N#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000)
N#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x10000000)
N
N/********************  Bit definition for RCC_AHB2RSTR register  **************/
N#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001)
N#define  RCC_AHB2RSTR_CRYPRST                ((uint32_t)0x00000010)
N#define  RCC_AHB2RSTR_HASHRST                ((uint32_t)0x00000020)
N /* maintained for legacy purpose */
N #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
N#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040)
N#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)
N
N/********************  Bit definition for RCC_AHB3RSTR register  **************/
N#if defined(STM32F40_41xxx)
X#if 1L
N#define  RCC_AHB3RSTR_FSMCRST                ((uint32_t)0x00000001)
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
X#if 0L || 0L
S#define  RCC_AHB3RSTR_FMCRST                ((uint32_t)0x00000001)
N#endif /* STM32F427_437xx ||  STM32F429_439xx */
N/********************  Bit definition for RCC_APB1RSTR register  **************/
N#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)
N#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)
N#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)
N#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
N#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)
N#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)
N#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)
N#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)
N#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)
N#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)
N#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)
N#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)
N#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
N#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)
N#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)
N#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)
N#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
N#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
N#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)
N#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)
N#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)
N#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
N#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)
N#define  RCC_APB1RSTR_UART7RST               ((uint32_t)0x40000000)
N#define  RCC_APB1RSTR_UART8RST               ((uint32_t)0x80000000)
N
N/********************  Bit definition for RCC_APB2RSTR register  **************/
N#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
N#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002)
N#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
N#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
N#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
N#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)
N#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)
N#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000)
N#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
N#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
N#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)
N#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
N#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000)
N#define  RCC_APB2RSTR_SPI6RST                ((uint32_t)0x00200000)
N#define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00400000)
N#define  RCC_APB2RSTR_LTDCRST                ((uint32_t)0x04000000)
N
N/* Old SPI1RST bit definition, maintained for legacy purpose */
N#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
N
N/********************  Bit definition for RCC_AHB1ENR register  ***************/
N#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
N#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
N#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
N#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)
N#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)
N#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020)
N#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040)
N#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
N#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100)
N#define  RCC_AHB1ENR_GPIOJEN                 ((uint32_t)0x00000200)
N#define  RCC_AHB1ENR_GPIOKEN                 ((uint32_t)0x00000400)
N#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
N#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)
N#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000)
N#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
N#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
N#define  RCC_AHB1ENR_DMA2DEN                 ((uint32_t)0x00800000)
N#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000)
N#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000)
N#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000)
N#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000)
N#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000)
N#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000)
N
N/********************  Bit definition for RCC_AHB2ENR register  ***************/
N#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001)
N#define  RCC_AHB2ENR_CRYPEN                  ((uint32_t)0x00000010)
N#define  RCC_AHB2ENR_HASHEN                  ((uint32_t)0x00000020)
N#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040)
N#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)
N
N/********************  Bit definition for RCC_AHB3ENR register  ***************/
N
N#if defined(STM32F40_41xxx)
X#if 1L
N#define  RCC_AHB3ENR_FSMCEN                  ((uint32_t)0x00000001)
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
X#if 0L || 0L
S#define  RCC_AHB3ENR_FMCEN                  ((uint32_t)0x00000001)
N#endif /* STM32F427_437xx ||  STM32F429_439xx */
N
N/********************  Bit definition for RCC_APB1ENR register  ***************/
N#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)
N#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)
N#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)
N#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
N#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)
N#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)
N#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)
N#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)
N#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)
N#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
N#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
N#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)
N#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
N#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)
N#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)
N#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)
N#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
N#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
N#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)
N#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)
N#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)
N#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
N#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)
N#define  RCC_APB1ENR_UART7EN                 ((uint32_t)0x40000000)
N#define  RCC_APB1ENR_UART8EN                 ((uint32_t)0x80000000)
N
N/********************  Bit definition for RCC_APB2ENR register  ***************/
N#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
N#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002)
N#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
N#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
N#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
N#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200)
N#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400)
N#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)
N#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
N#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000)
N#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
N#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
N#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)
N#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
N#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000)
N#define  RCC_APB2ENR_SPI6EN                  ((uint32_t)0x00200000)
N#define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00400000)
N#define  RCC_APB2ENR_LTDCEN                  ((uint32_t)0x04000000)
N
N/********************  Bit definition for RCC_AHB1LPENR register  *************/
N#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
N#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
N#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
N#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)
N#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)
N#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020)
N#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040)
N#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
N#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100)
N#define  RCC_AHB1LPENR_GPIOJLPEN             ((uint32_t)0x00000200)
N#define  RCC_AHB1LPENR_GPIOKLPEN             ((uint32_t)0x00000400)
N#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
N#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
N#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
N#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)
N#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)
N#define  RCC_AHB1LPENR_SRAM3LPEN             ((uint32_t)0x00080000)
N#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
N#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
N#define  RCC_AHB1LPENR_DMA2DLPEN             ((uint32_t)0x00800000)
N#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000)
N#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000)
N#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000)
N#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000)
N#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000)
N#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000)
N
N/********************  Bit definition for RCC_AHB2LPENR register  *************/
N#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001)
N#define  RCC_AHB2LPENR_CRYPLPEN              ((uint32_t)0x00000010)
N#define  RCC_AHB2LPENR_HASHLPEN              ((uint32_t)0x00000020)
N#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040)
N#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)
N
N/********************  Bit definition for RCC_AHB3LPENR register  *************/
N#if defined(STM32F40_41xxx)
X#if 1L
N#define  RCC_AHB3LPENR_FSMCLPEN              ((uint32_t)0x00000001)
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
X#if 0L || 0L
S#define  RCC_AHB3LPENR_FMCLPEN              ((uint32_t)0x00000001)
N#endif /* STM32F427_437xx ||  STM32F429_439xx */
N
N/********************  Bit definition for RCC_APB1LPENR register  *************/
N#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)
N#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)
N#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)
N#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
N#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)
N#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)
N#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040)
N#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080)
N#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100)
N#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
N#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
N#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)
N#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
N#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)
N#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)
N#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)
N#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
N#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
N#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)
N#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000)
N#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000)
N#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
N#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
N#define  RCC_APB1LPENR_UART7LPEN             ((uint32_t)0x40000000)
N#define  RCC_APB1LPENR_UART8LPEN             ((uint32_t)0x80000000)
N
N/********************  Bit definition for RCC_APB2LPENR register  *************/
N#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
N#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002)
N#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
N#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
N#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
N#define  RCC_APB2LPENR_ADC2PEN               ((uint32_t)0x00000200)
N#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400)
N#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)
N#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
N#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000)
N#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
N#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
N#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)
N#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
N#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000)
N#define  RCC_APB2LPENR_SPI6LPEN              ((uint32_t)0x00200000)
N#define  RCC_APB2LPENR_SAI1LPEN              ((uint32_t)0x00400000)
N#define  RCC_APB2LPENR_LTDCLPEN              ((uint32_t)0x04000000)
N
N/********************  Bit definition for RCC_BDCR register  ******************/
N#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
N#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
N#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
N#define  RCC_BDCR_LSEMOD                     ((uint32_t)0x00000008)
N
N#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)
N#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)
N#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)
N
N#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
N#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
N
N/********************  Bit definition for RCC_CSR register  *******************/
N#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
N#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
N#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
N#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
N#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)
N#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
N#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
N#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)
N#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
N#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
N
N/********************  Bit definition for RCC_SSCGR register  *****************/
N#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
N#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
N#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
N#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
N
N/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
N#define  RCC_PLLI2SCFGR_PLLI2SM              ((uint32_t)0x0000003F)
N#define  RCC_PLLI2SCFGR_PLLI2SM_0            ((uint32_t)0x00000001)
N#define  RCC_PLLI2SCFGR_PLLI2SM_1            ((uint32_t)0x00000002)
N#define  RCC_PLLI2SCFGR_PLLI2SM_2            ((uint32_t)0x00000004)
N#define  RCC_PLLI2SCFGR_PLLI2SM_3            ((uint32_t)0x00000008)
N#define  RCC_PLLI2SCFGR_PLLI2SM_4            ((uint32_t)0x00000010)
N#define  RCC_PLLI2SCFGR_PLLI2SM_5            ((uint32_t)0x00000020)
N
N/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
N#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)
N#define  RCC_PLLI2SCFGR_PLLI2SQ              ((uint32_t)0x0F000000)
N#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)
N
N/********************  Bit definition for RCC_PLLSAICFGR register  ************/
N#define  RCC_PLLSAICFGR_PLLI2SN              ((uint32_t)0x00007FC0)
N#define  RCC_PLLSAICFGR_PLLI2SQ              ((uint32_t)0x0F000000)
N#define  RCC_PLLSAICFGR_PLLI2SR              ((uint32_t)0x70000000)
N
N/********************  Bit definition for RCC_DCKCFGR register  ***************/
N#define  RCC_DCKCFGR_PLLI2SDIVQ              ((uint32_t)0x0000001F)
N#define  RCC_DCKCFGR_PLLSAIDIVQ              ((uint32_t)0x00001F00)
N#define  RCC_DCKCFGR_PLLSAIDIVR              ((uint32_t)0x00030000)
N#define  RCC_DCKCFGR_SAI1ASRC                ((uint32_t)0x00300000)
N#define  RCC_DCKCFGR_SAI1BSRC                ((uint32_t)0x00C00000)
N#define  RCC_DCKCFGR_TIMPRE                  ((uint32_t)0x01000000)
N
N
N/******************************************************************************/
N/*                                                                            */
N/*                                    RNG                                     */
N/*                                                                            */
N/******************************************************************************/
N/********************  Bits definition for RNG_CR register  *******************/
N#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
N#define RNG_CR_IE                            ((uint32_t)0x00000008)
N
N/********************  Bits definition for RNG_SR register  *******************/
N#define RNG_SR_DRDY                          ((uint32_t)0x00000001)
N#define RNG_SR_CECS                          ((uint32_t)0x00000002)
N#define RNG_SR_SECS                          ((uint32_t)0x00000004)
N#define RNG_SR_CEIS                          ((uint32_t)0x00000020)
N#define RNG_SR_SEIS                          ((uint32_t)0x00000040)
N
N/******************************************************************************/
N/*                                                                            */
N/*                           Real-Time Clock (RTC)                            */
N/*                                                                            */
N/******************************************************************************/
N/********************  Bits definition for RTC_TR register  *******************/
N#define RTC_TR_PM                            ((uint32_t)0x00400000)
N#define RTC_TR_HT                            ((uint32_t)0x00300000)
N#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
N#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
N#define RTC_TR_HU                            ((uint32_t)0x000F0000)
N#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
N#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
N#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
N#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
N#define RTC_TR_MNT                           ((uint32_t)0x00007000)
N#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
N#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
N#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
N#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
N#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
N#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
N#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
N#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
N#define RTC_TR_ST                            ((uint32_t)0x00000070)
N#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
N#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
N#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
N#define RTC_TR_SU                            ((uint32_t)0x0000000F)
N#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
N#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
N#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
N#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
N
N/********************  Bits definition for RTC_DR register  *******************/
N#define RTC_DR_YT                            ((uint32_t)0x00F00000)
N#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
N#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
N#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
N#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
N#define RTC_DR_YU                            ((uint32_t)0x000F0000)
N#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
N#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
N#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
N#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
N#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
N#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
N#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
N#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
N#define RTC_DR_MT                            ((uint32_t)0x00001000)
N#define RTC_DR_MU                            ((uint32_t)0x00000F00)
N#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
N#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
N#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
N#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
N#define RTC_DR_DT                            ((uint32_t)0x00000030)
N#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
N#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
N#define RTC_DR_DU                            ((uint32_t)0x0000000F)
N#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
N#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
N#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
N#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
N
N/********************  Bits definition for RTC_CR register  *******************/
N#define RTC_CR_COE                           ((uint32_t)0x00800000)
N#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
N#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
N#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
N#define RTC_CR_POL                           ((uint32_t)0x00100000)
N#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
N#define RTC_CR_BCK                           ((uint32_t)0x00040000)
N#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
N#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
N#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
N#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
N#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
N#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
N#define RTC_CR_TSE                           ((uint32_t)0x00000800)
N#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
N#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
N#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
N#define RTC_CR_DCE                           ((uint32_t)0x00000080)
N#define RTC_CR_FMT                           ((uint32_t)0x00000040)
N#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
N#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
N#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
N#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
N#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
N#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
N#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
N
N/********************  Bits definition for RTC_ISR register  ******************/
N#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
N#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
N#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
N#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
N#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
N#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
N#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
N#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
N#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
N#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
N#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
N#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
N#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
N#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
N#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
N
N/********************  Bits definition for RTC_PRER register  *****************/
N#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
N#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00001FFF)
N
N/********************  Bits definition for RTC_WUTR register  *****************/
N#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
N
N/********************  Bits definition for RTC_CALIBR register  ***************/
N#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
N#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
N
N/********************  Bits definition for RTC_ALRMAR register  ***************/
N#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
N#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
N#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
N#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
N#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
N#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
N#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
N#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
N#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
N#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
N#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
N#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
N#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
N#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
N#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
N#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
N#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
N#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
N#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
N#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
N#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
N#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
N#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
N#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
N#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
N#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
N#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
N#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
N#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
N#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
N#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
N#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
N#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
N#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
N#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
N#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
N#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
N#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
N#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
N#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
N
N/********************  Bits definition for RTC_ALRMBR register  ***************/
N#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
N#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
N#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
N#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
N#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
N#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
N#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
N#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
N#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
N#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
N#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
N#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
N#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
N#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
N#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
N#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
N#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
N#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
N#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
N#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
N#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
N#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
N#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
N#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
N#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
N#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
N#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
N#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
N#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
N#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
N#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
N#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
N#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
N#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
N#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
N#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
N#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
N#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
N#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
N#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
N
N/********************  Bits definition for RTC_WPR register  ******************/
N#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
N
N/********************  Bits definition for RTC_SSR register  ******************/
N#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
N
N/********************  Bits definition for RTC_SHIFTR register  ***************/
N#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
N#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
N
N/********************  Bits definition for RTC_TSTR register  *****************/
N#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
N#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
N#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
N#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
N#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
N#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
N#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
N#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
N#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
N#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
N#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
N#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
N#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
N#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
N#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
N#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
N#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
N#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
N#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
N#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
N#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
N#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
N#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
N#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
N#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
N#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
N#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
N
N/********************  Bits definition for RTC_TSDR register  *****************/
N#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
N#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
N#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
N#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
N#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
N#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
N#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
N#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
N#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
N#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
N#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
N#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
N#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
N#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
N#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
N#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
N#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
N#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
N
N/********************  Bits definition for RTC_TSSSR register  ****************/
N#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
N
N/********************  Bits definition for RTC_CAL register  *****************/
N#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
N#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
N#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
N#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
N#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
N#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
N#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
N#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
N#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
N#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
N#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
N#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
N#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
N
N/********************  Bits definition for RTC_TAFCR register  ****************/
N#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
N#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)
N#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)
N#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
N#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
N#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
N#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
N#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
N#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
N#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
N#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
N#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
N#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
N#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
N#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
N#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
N#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
N#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
N
N/********************  Bits definition for RTC_ALRMASSR register  *************/
N#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
N#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
N#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
N#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
N#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
N#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
N
N/********************  Bits definition for RTC_ALRMBSSR register  *************/
N#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
N#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
N#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
N#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
N#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
N#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
N
N/********************  Bits definition for RTC_BKP0R register  ****************/
N#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP1R register  ****************/
N#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP2R register  ****************/
N#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP3R register  ****************/
N#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP4R register  ****************/
N#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP5R register  ****************/
N#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP6R register  ****************/
N#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP7R register  ****************/
N#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP8R register  ****************/
N#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP9R register  ****************/
N#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP10R register  ***************/
N#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP11R register  ***************/
N#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP12R register  ***************/
N#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP13R register  ***************/
N#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP14R register  ***************/
N#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP15R register  ***************/
N#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP16R register  ***************/
N#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP17R register  ***************/
N#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP18R register  ***************/
N#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
N
N/********************  Bits definition for RTC_BKP19R register  ***************/
N#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
N
N/******************************************************************************/
N/*                                                                            */
N/*                          Serial Audio Interface                            */
N/*                                                                            */
N/******************************************************************************/
N/********************  Bit definition for SAI_GCR register  *******************/
N#define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
N#define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
N
N#define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
N#define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010)        /*!<Bit 0 */
N#define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020)        /*!<Bit 1 */
N
N/*******************  Bit definition for SAI_xCR1 register  *******************/
N#define  SAI_xCR1_MODE                    ((uint32_t)0x00000003)        /*!<MODE[1:0] bits (Audio Block Mode)           */
N#define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
N
N#define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000C)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
N#define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004)        /*!<Bit 0 */
N#define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008)        /*!<Bit 1 */
N
N#define  SAI_xCR1_DS                      ((uint32_t)0x000000E0)        /*!<DS[1:0] bits (Data Size) */
N#define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020)        /*!<Bit 0 */
N#define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040)        /*!<Bit 1 */
N#define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080)        /*!<Bit 2 */
N
N#define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100)        /*!<LSB First Configuration  */
N#define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200)        /*!<ClocK STRobing edge      */
N
N#define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00)        /*!<SYNCEN[1:0](SYNChronization ENable) */
N#define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400)        /*!<Bit 0 */
N#define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800)        /*!<Bit 1 */
N
N#define  SAI_xCR1_MONO                    ((uint32_t)0x00001000)        /*!<Mono mode                  */
N#define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000)        /*!<Output Drive               */
N#define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000)        /*!<Audio Block enable         */
N#define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000)        /*!<DMA enable                 */
N#define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000)        /*!<No Divider Configuration   */
N
N#define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00780000)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
N#define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00080000)        /*!<Bit 0  */
N#define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00100000)        /*!<Bit 1  */
N#define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00200000)        /*!<Bit 2  */
N#define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00400000)        /*!<Bit 3  */
N
N/*******************  Bit definition for SAI_xCR2 register  *******************/
N#define  SAI_xCR2_FTH                     ((uint32_t)0x00000003)        /*!<FTH[1:0](Fifo THreshold)  */
N#define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
N
N#define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008)        /*!<Fifo FLUSH                       */
N#define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010)        /*!<TRIState Management on data line */
N#define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020)        /*!<Mute mode                        */
N#define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040)        /*!<Muate value                      */
N
N#define  SAI_xCR2_MUTECNT                  ((uint32_t)0x00001F80)       /*!<MUTECNT[5:0] (MUTE counter) */
N#define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080)        /*!<Bit 0 */
N#define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100)        /*!<Bit 1 */
N#define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200)        /*!<Bit 2 */
N#define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400)        /*!<Bit 3 */
N#define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800)        /*!<Bit 4 */
N#define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000)        /*!<Bit 5 */
N
N#define  SAI_xCR2_CPL                     ((uint32_t)0x00080000)        /*!< Complement Bit             */
N
N#define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000)        /*!<COMP[1:0] (Companding mode) */
N#define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000)        /*!<Bit 0 */
N#define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000)        /*!<Bit 1 */
N
N/******************  Bit definition for SAI_xFRCR register  *******************/
N#define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FF)        /*!<FRL[1:0](Frame length)  */
N#define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
N#define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
N#define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
N#define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
N
N#define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00)        /*!<FRL[1:0] (Frame synchronization active level length)  */
N#define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800)        /*!<Bit 3 */
N#define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000)        /*!<Bit 4 */
N#define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000)        /*!<Bit 5 */
N#define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000)        /*!<Bit 6 */
N
N#define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000)        /*!< Frame Synchronization Definition */
N#define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000)        /*!<Frame Synchronization POLarity    */
N#define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000)        /*!<Frame Synchronization OFFset      */
N
N/******************  Bit definition for SAI_xSLOTR register  *******************/
N#define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001F)        /*!<FRL[4:0](First Bit Offset)  */
N#define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001)        /*!<Bit 0 */
N#define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002)        /*!<Bit 1 */
N#define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004)        /*!<Bit 2 */
N#define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008)        /*!<Bit 3 */
N#define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010)        /*!<Bit 4 */
N                                     
N#define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0)        /*!<SLOTSZ[1:0] (Slot size)  */
N#define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040)        /*!<Bit 0 */
N#define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080)        /*!<Bit 1 */
N
N#define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
N#define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100)        /*!<Bit 0 */
N#define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200)        /*!<Bit 1 */
N#define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400)        /*!<Bit 2 */
N#define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800)        /*!<Bit 3 */
N
N#define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000)        /*!<SLOTEN[15:0] (Slot Enable)  */
N
N/*******************  Bit definition for SAI_xIMR register  *******************/
N#define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001)        /*!<Overrun underrun interrupt enable                              */
N#define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002)        /*!<Mute detection interrupt enable                                */
N#define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004)        /*!<Wrong Clock Configuration interrupt enable                     */
N#define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008)        /*!<FIFO request interrupt enable                                  */
N#define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010)        /*!<Codec not ready interrupt enable                               */
N#define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020)        /*!<Anticipated frame synchronization detection interrupt enable   */
N#define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040)        /*!<Late frame synchronization detection interrupt enable          */
N
N/********************  Bit definition for SAI_xSR register  *******************/
N#define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001)         /*!<Overrun underrun                               */
N#define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002)         /*!<Mute detection                                 */
N#define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004)         /*!<Wrong Clock Configuration                      */
N#define  SAI_xSR_FREQ                     ((uint32_t)0x00000008)         /*!<FIFO request                                   */
N#define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010)         /*!<Codec not ready                                */
N#define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020)         /*!<Anticipated frame synchronization detection    */
N#define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040)         /*!<Late frame synchronization detection           */
N
N#define  SAI_xSR_FLVL                     ((uint32_t)0x00070000)         /*!<FLVL[2:0] (FIFO Level Threshold)               */
N#define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000)         /*!<Bit 0 */
N#define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000)         /*!<Bit 1 */
N#define  SAI_xSR_FLVL_2                   ((uint32_t)0x00030000)         /*!<Bit 2 */
N
N/******************  Bit definition for SAI_xCLRFR register  ******************/
N#define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001)        /*!<Clear Overrun underrun                               */
N#define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002)        /*!<Clear Mute detection                                 */
N#define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004)        /*!<Clear Wrong Clock Configuration                      */
N#define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008)        /*!<Clear FIFO request                                   */
N#define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010)        /*!<Clear Codec not ready                                */
N#define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020)        /*!<Clear Anticipated frame synchronization detection    */
N#define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040)        /*!<Clear Late frame synchronization detection           */
N
N/******************  Bit definition for SAI_xDR register  ******************/
N#define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFF)        
N
N/******************************************************************************/
N/*                                                                            */
N/*                          SD host Interface                                 */
N/*                                                                            */
N/******************************************************************************/
N/******************  Bit definition for SDIO_POWER register  ******************/
N#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
N#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!<Bit 0 */
N#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!<Bit 1 */
N
N/******************  Bit definition for SDIO_CLKCR register  ******************/
N#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!<Clock divide factor             */
N#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!<Clock enable bit                */
N#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!<Power saving configuration bit  */
N#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!<Clock divider bypass enable bit */
N
N#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
N#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!<Bit 0 */
N#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!<Bit 1 */
N
N#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!<SDIO_CK dephasing selection bit */
N#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!<HW Flow Control enable          */
N
N/*******************  Bit definition for SDIO_ARG register  *******************/
N#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */
N
N/*******************  Bit definition for SDIO_CMD register  *******************/
N#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!<Command Index                               */
N
N#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
N#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!< Bit 0 */
N#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!< Bit 1 */
N
N#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!<CPSM Waits for Interrupt Request                               */
N#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
N#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit                   */
N#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!<SD I/O suspend command                                         */
N#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!<Enable CMD completion                                          */
N#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!<Not Interrupt Enable */
N#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!<CE-ATA command       */
N
N/*****************  Bit definition for SDIO_RESPCMD register  *****************/
N#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!<Response command index */
N
N/******************  Bit definition for SDIO_RESP0 register  ******************/
N#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
N
N/******************  Bit definition for SDIO_RESP1 register  ******************/
N#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
N
N/******************  Bit definition for SDIO_RESP2 register  ******************/
N#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
N
N/******************  Bit definition for SDIO_RESP3 register  ******************/
N#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
N
N/******************  Bit definition for SDIO_RESP4 register  ******************/
N#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
N
N/******************  Bit definition for SDIO_DTIMER register  *****************/
N#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */
N
N/******************  Bit definition for SDIO_DLEN register  *******************/
N#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value    */
N
N/******************  Bit definition for SDIO_DCTRL register  ******************/
N#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!<Data transfer enabled bit         */
N#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!<Data transfer direction selection */
N#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!<Data transfer mode selection      */
N#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!<DMA enabled bit                   */
N
N#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
N#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!<Bit 0 */
N#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!<Bit 1 */
N#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!<Bit 2 */
N#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!<Bit 3 */
N
N#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!<Read wait start         */
N#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!<Read wait stop          */
N#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!<Read wait mode          */
N#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!<SD I/O enable functions */
N
N/******************  Bit definition for SDIO_DCOUNT register  *****************/
N#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */
N
N/******************  Bit definition for SDIO_STA register  ********************/
N#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed)  */
N#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed)   */
N#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout                      */
N#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout                                  */
N#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error                  */
N#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error                   */
N#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed)  */
N#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required)           */
N#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
N#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!<Start bit not detected on all data signals in wide bus mode */
N#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed)   */
N#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress                  */
N#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress                     */
N#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress                      */
N#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
N#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
N#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full                            */
N#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full                             */
N#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty                           */
N#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty                            */
N#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO               */
N#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO                */
N#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDIO interrupt received                       */
N#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received for CMD61 */
N
N/*******************  Bit definition for SDIO_ICR register  *******************/
N#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */
N#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */
N#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */
N#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */
N#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */
N#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit  */
N#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit  */
N#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit  */
N#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit  */
N#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!<STBITERR flag clear bit */
N#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit  */
N#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDIOIT flag clear bit   */
N#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!<CEATAEND flag clear bit */
N
N/******************  Bit definition for SDIO_MASK register  *******************/
N#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable          */
N#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable             */
N#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable           */
N#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable              */
N#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
N#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
N#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */
N#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable              */
N#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable                  */
N#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!<Start Bit Error Interrupt Enable           */
N#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable            */
N#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable           */
N#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable      */
N#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled      */
N#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable        */
N#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable         */
N#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable              */
N#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable              */
N#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable             */
N#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable             */
N#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */
N#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */
N#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDIO Mode Interrupt Received interrupt Enable */
N#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received Interrupt Enable */
N
N/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
N#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */
N
N/******************  Bit definition for SDIO_FIFO register  *******************/
N#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */
N
N/******************************************************************************/
N/*                                                                            */
N/*                        Serial Peripheral Interface                         */
N/*                                                                            */
N/******************************************************************************/
N/*******************  Bit definition for SPI_CR1 register  ********************/
N#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!<Clock Phase      */
N#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!<Clock Polarity   */
N#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!<Master Selection */
N
N#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!<BR[2:0] bits (Baud Rate Control) */
N#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!<Bit 0 */
N#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!<Bit 1 */
N#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!<Bit 2 */
N
N#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!<SPI Enable                          */
N#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!<Frame Format                        */
N#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!<Internal slave select               */
N#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!<Software slave management           */
N#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!<Receive only                        */
N#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!<Data Frame Format                   */
N#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!<Transmit CRC next                   */
N#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!<Hardware CRC calculation enable     */
N#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!<Output enable in bidirectional mode */
N#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!<Bidirectional data mode enable      */
N
N/*******************  Bit definition for SPI_CR2 register  ********************/
N#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!<Rx Buffer DMA Enable                 */
N#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!<Tx Buffer DMA Enable                 */
N#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!<SS Output Enable                     */
N#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!<Error Interrupt Enable               */
N#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!<RX buffer Not Empty Interrupt Enable */
N#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!<Tx buffer Empty Interrupt Enable     */
N
N/********************  Bit definition for SPI_SR register  ********************/
N#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!<Receive buffer Not Empty */
N#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!<Transmit buffer Empty    */
N#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!<Channel side             */
N#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!<Underrun flag            */
N#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!<CRC Error flag           */
N#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!<Mode fault               */
N#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!<Overrun flag             */
N#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!<Busy flag                */
N
N/********************  Bit definition for SPI_DR register  ********************/
N#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!<Data Register           */
N
N/*******************  Bit definition for SPI_CRCPR register  ******************/
N#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!<CRC polynomial register */
N
N/******************  Bit definition for SPI_RXCRCR register  ******************/
N#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!<Rx CRC Register         */
N
N/******************  Bit definition for SPI_TXCRCR register  ******************/
N#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!<Tx CRC Register         */
N
N/******************  Bit definition for SPI_I2SCFGR register  *****************/
N#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
N
N#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
N#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
N#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
N
N#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity               */
N
N#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
N#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
N#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
N
N#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization                 */
N
N#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
N#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
N#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
N
N#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable         */
N#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
N
N/******************  Bit definition for SPI_I2SPR register  *******************/
N#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler         */
N#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
N#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable   */
N
N/******************************************************************************/
N/*                                                                            */
N/*                                 SYSCFG                                     */
N/*                                                                            */
N/******************************************************************************/
N/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
N#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
N#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!<Bit 0 */
N#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!<Bit 1 */
N#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004) /*!<Bit 2 */
N
N#define SYSCFG_MEMRMP_FB_MODE           ((uint32_t)0x00000100) /*!< User Flash Bank mode */
N
N#define SYSCFG_MEMRMP_SWP_FMC           ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
N#define SYSCFG_MEMRMP_SWP_FMC_0         ((uint32_t)0x00000400) /*!<Bit 0 */
N#define SYSCFG_MEMRMP_SWP_FMC_1         ((uint32_t)0x00000800) /*!<Bit 1 */
N
N
N/******************  Bit definition for SYSCFG_PMC register  ******************/
N#define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit  */
N#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */
N#define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit  */
N#define SYSCFG_PMC_ADC3DC2              ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit  */
N
N#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
N/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
N#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
N
N/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
N#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!<EXTI 0 configuration */
N#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
N#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
N#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!<EXTI 3 configuration */
N/** 
N  * @brief   EXTI0 configuration  
N  */ 
N#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!<PA[0] pin */
N#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!<PB[0] pin */
N#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!<PC[0] pin */
N#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!<PD[0] pin */
N#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!<PE[0] pin */
N#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!<PF[0] pin */
N#define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0006) /*!<PG[0] pin */
N#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0007) /*!<PH[0] pin */
N#define SYSCFG_EXTICR1_EXTI0_PI         ((uint16_t)0x0008) /*!<PI[0] pin */
N#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint16_t)0x0009) /*!<PJ[0] pin */
N#define SYSCFG_EXTICR1_EXTI0_PK         ((uint16_t)0x000A) /*!<PK[0] pin */
N
N/** 
N  * @brief   EXTI1 configuration  
N  */ 
N#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!<PA[1] pin */
N#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!<PB[1] pin */
N#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!<PC[1] pin */
N#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!<PD[1] pin */
N#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!<PE[1] pin */
N#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!<PF[1] pin */
N#define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0060) /*!<PG[1] pin */
N#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0070) /*!<PH[1] pin */
N#define SYSCFG_EXTICR1_EXTI1_PI         ((uint16_t)0x0080) /*!<PI[1] pin */
N#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint16_t)0x0090) /*!<PJ[1] pin */
N#define SYSCFG_EXTICR1_EXTI1_PK         ((uint16_t)0x00A0) /*!<PK[1] pin */
N
N/** 
N  * @brief   EXTI2 configuration  
N  */ 
N#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!<PA[2] pin */
N#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!<PB[2] pin */
N#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!<PC[2] pin */
N#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!<PD[2] pin */
N#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!<PE[2] pin */
N#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!<PF[2] pin */
N#define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0600) /*!<PG[2] pin */
N#define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0700) /*!<PH[2] pin */
N#define SYSCFG_EXTICR1_EXTI2_PI         ((uint16_t)0x0800) /*!<PI[2] pin */
N#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint16_t)0x0900) /*!<PJ[2] pin */
N#define SYSCFG_EXTICR1_EXTI2_PK         ((uint16_t)0x0A00) /*!<PK[2] pin */
N
N/** 
N  * @brief   EXTI3 configuration  
N  */ 
N#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!<PA[3] pin */
N#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!<PB[3] pin */
N#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!<PC[3] pin */
N#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!<PD[3] pin */
N#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!<PE[3] pin */
N#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!<PF[3] pin */
N#define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x6000) /*!<PG[3] pin */
N#define SYSCFG_EXTICR1_EXTI3_PH         ((uint16_t)0x7000) /*!<PH[3] pin */
N#define SYSCFG_EXTICR1_EXTI3_PI         ((uint16_t)0x8000) /*!<PI[3] pin */
N#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint16_t)0x9000) /*!<PJ[3] pin */
N#define SYSCFG_EXTICR1_EXTI3_PK         ((uint16_t)0xA000) /*!<PK[3] pin */
N
N/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
N#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!<EXTI 4 configuration */
N#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
N#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
N#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!<EXTI 7 configuration */
N/** 
N  * @brief   EXTI4 configuration  
N  */ 
N#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!<PA[4] pin */
N#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!<PB[4] pin */
N#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!<PC[4] pin */
N#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!<PD[4] pin */
N#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!<PE[4] pin */
N#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!<PF[4] pin */
N#define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0006) /*!<PG[4] pin */
N#define SYSCFG_EXTICR2_EXTI4_PH         ((uint16_t)0x0007) /*!<PH[4] pin */
N#define SYSCFG_EXTICR2_EXTI4_PI         ((uint16_t)0x0008) /*!<PI[4] pin */
N#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint16_t)0x0009) /*!<PJ[4] pin */
N#define SYSCFG_EXTICR2_EXTI4_PK         ((uint16_t)0x000A) /*!<PK[4] pin */
N
N/** 
N  * @brief   EXTI5 configuration  
N  */ 
N#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!<PA[5] pin */
N#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!<PB[5] pin */
N#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!<PC[5] pin */
N#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!<PD[5] pin */
N#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!<PE[5] pin */
N#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!<PF[5] pin */
N#define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0060) /*!<PG[5] pin */
N#define SYSCFG_EXTICR2_EXTI5_PH         ((uint16_t)0x0070) /*!<PH[5] pin */
N#define SYSCFG_EXTICR2_EXTI5_PI         ((uint16_t)0x0080) /*!<PI[5] pin */
N#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint16_t)0x0090) /*!<PJ[5] pin */
N#define SYSCFG_EXTICR2_EXTI5_PK         ((uint16_t)0x00A0) /*!<PK[5] pin */
N
N/** 
N  * @brief   EXTI6 configuration  
N  */ 
N#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!<PA[6] pin */
N#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!<PB[6] pin */
N#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!<PC[6] pin */
N#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!<PD[6] pin */
N#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!<PE[6] pin */
N#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!<PF[6] pin */
N#define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0600) /*!<PG[6] pin */
N#define SYSCFG_EXTICR2_EXTI6_PH         ((uint16_t)0x0700) /*!<PH[6] pin */
N#define SYSCFG_EXTICR2_EXTI6_PI         ((uint16_t)0x0800) /*!<PI[6] pin */
N#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint16_t)0x0900) /*!<PJ[6] pin */
N#define SYSCFG_EXTICR2_EXTI6_PK         ((uint16_t)0x0A00) /*!<PK[6] pin */
N
N/** 
N  * @brief   EXTI7 configuration  
N  */ 
N#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!<PA[7] pin */
N#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!<PB[7] pin */
N#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!<PC[7] pin */
N#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!<PD[7] pin */
N#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!<PE[7] pin */
N#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!<PF[7] pin */
N#define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x6000) /*!<PG[7] pin */
N#define SYSCFG_EXTICR2_EXTI7_PH         ((uint16_t)0x7000) /*!<PH[7] pin */
N#define SYSCFG_EXTICR2_EXTI7_PI         ((uint16_t)0x8000) /*!<PI[7] pin */
N#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint16_t)0x9000) /*!<PJ[7] pin */
N#define SYSCFG_EXTICR2_EXTI7_PK         ((uint16_t)0xA000) /*!<PK[7] pin */
N
N/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
N#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!<EXTI 8 configuration */
N#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
N#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
N#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!<EXTI 11 configuration */
N           
N/** 
N  * @brief   EXTI8 configuration  
N  */ 
N#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!<PA[8] pin */
N#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!<PB[8] pin */
N#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!<PC[8] pin */
N#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!<PD[8] pin */
N#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!<PE[8] pin */
N#define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0005) /*!<PF[8] pin */
N#define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0006) /*!<PG[8] pin */
N#define SYSCFG_EXTICR3_EXTI8_PH         ((uint16_t)0x0007) /*!<PH[8] pin */
N#define SYSCFG_EXTICR3_EXTI8_PI         ((uint16_t)0x0008) /*!<PI[8] pin */
N#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint16_t)0x0009) /*!<PJ[8] pin */
N
N/** 
N  * @brief   EXTI9 configuration  
N  */ 
N#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!<PA[9] pin */
N#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!<PB[9] pin */
N#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!<PC[9] pin */
N#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!<PD[9] pin */
N#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!<PE[9] pin */
N#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!<PF[9] pin */
N#define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0060) /*!<PG[9] pin */
N#define SYSCFG_EXTICR3_EXTI9_PH         ((uint16_t)0x0070) /*!<PH[9] pin */
N#define SYSCFG_EXTICR3_EXTI9_PI         ((uint16_t)0x0080) /*!<PI[9] pin */
N#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint16_t)0x0090) /*!<PJ[9] pin */
N
N/** 
N  * @brief   EXTI10 configuration  
N  */ 
N#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!<PA[10] pin */
N#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!<PB[10] pin */
N#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!<PC[10] pin */
N#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!<PD[10] pin */
N#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!<PE[10] pin */
N#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!<PF[10] pin */
N#define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0600) /*!<PG[10] pin */
N#define SYSCFG_EXTICR3_EXTI10_PH        ((uint16_t)0x0700) /*!<PH[10] pin */
N#define SYSCFG_EXTICR3_EXTI10_PI        ((uint16_t)0x0800) /*!<PI[10] pin */
N#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint16_t)0x0900) /*!<PJ[10] pin */
N
N/** 
N  * @brief   EXTI11 configuration  
N  */ 
N#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!<PA[11] pin */
N#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!<PB[11] pin */
N#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!<PC[11] pin */
N#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!<PD[11] pin */
N#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!<PE[11] pin */
N#define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x5000) /*!<PF[11] pin */
N#define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x6000) /*!<PG[11] pin */
N#define SYSCFG_EXTICR3_EXTI11_PH        ((uint16_t)0x7000) /*!<PH[11] pin */
N#define SYSCFG_EXTICR3_EXTI11_PI        ((uint16_t)0x8000) /*!<PI[11] pin */
N#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint16_t)0x9000) /*!<PJ[11] pin */
N
N/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
N#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!<EXTI 12 configuration */
N#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
N#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
N#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!<EXTI 15 configuration */
N/** 
N  * @brief   EXTI12 configuration  
N  */ 
N#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!<PA[12] pin */
N#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!<PB[12] pin */
N#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!<PC[12] pin */
N#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!<PD[12] pin */
N#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!<PE[12] pin */
N#define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0005) /*!<PF[12] pin */
N#define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0006) /*!<PG[12] pin */
N#define SYSCFG_EXTICR4_EXTI12_PH        ((uint16_t)0x0007) /*!<PH[12] pin */
N#define SYSCFG_EXTICR4_EXTI12_PI        ((uint16_t)0x0008) /*!<PI[12] pin */
N#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint16_t)0x0009) /*!<PJ[12] pin */
N
N/** 
N  * @brief   EXTI13 configuration  
N  */ 
N#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!<PA[13] pin */
N#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!<PB[13] pin */
N#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!<PC[13] pin */
N#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!<PD[13] pin */
N#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!<PE[13] pin */
N#define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0050) /*!<PF[13] pin */
N#define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0060) /*!<PG[13] pin */
N#define SYSCFG_EXTICR4_EXTI13_PH        ((uint16_t)0x0070) /*!<PH[13] pin */
N#define SYSCFG_EXTICR4_EXTI13_PI        ((uint16_t)0x0008) /*!<PI[13] pin */
N#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint16_t)0x0009) /*!<PJ[13] pin */
N
N/** 
N  * @brief   EXTI14 configuration  
N  */ 
N#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!<PA[14] pin */
N#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!<PB[14] pin */
N#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!<PC[14] pin */
N#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!<PD[14] pin */
N#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!<PE[14] pin */
N#define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0500) /*!<PF[14] pin */
N#define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0600) /*!<PG[14] pin */
N#define SYSCFG_EXTICR4_EXTI14_PH        ((uint16_t)0x0700) /*!<PH[14] pin */
N#define SYSCFG_EXTICR4_EXTI14_PI        ((uint16_t)0x0800) /*!<PI[14] pin */
N#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint16_t)0x0900) /*!<PJ[14] pin */
N
N/** 
N  * @brief   EXTI15 configuration  
N  */ 
N#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!<PA[15] pin */
N#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!<PB[15] pin */
N#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!<PC[15] pin */
N#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!<PD[15] pin */
N#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!<PE[15] pin */
N#define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x5000) /*!<PF[15] pin */
N#define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x6000) /*!<PG[15] pin */
N#define SYSCFG_EXTICR4_EXTI15_PH        ((uint16_t)0x7000) /*!<PH[15] pin */
N#define SYSCFG_EXTICR4_EXTI15_PI        ((uint16_t)0x8000) /*!<PI[15] pin */
N#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint16_t)0x9000) /*!<PJ[15] pin */
N
N/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
N#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
N#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */
N
N/******************************************************************************/
N/*                                                                            */
N/*                                    TIM                                     */
N/*                                                                            */
N/******************************************************************************/
N/*******************  Bit definition for TIM_CR1 register  ********************/
N#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable        */
N#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable        */
N#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
N#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode        */
N#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction             */
N
N#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
N#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
N#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
N
N#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable     */
N
N#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
N#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
N#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
N
N/*******************  Bit definition for TIM_CR2 register  ********************/
N#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control        */
N#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
N#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection            */
N
N#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
N#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
N#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
N#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
N
N#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
N#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output)  */
N#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
N#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output)  */
N#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
N#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output)  */
N#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
N#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output)  */
N
N/*******************  Bit definition for TIM_SMCR register  *******************/
N#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection)    */
N#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
N#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
N#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
N
N#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection)        */
N#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
N#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
N#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
N
N#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode                       */
N
N#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
N#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
N#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
N#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
N#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
N
N#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
N#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
N#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
N
N#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable     */
N#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
N
N/*******************  Bit definition for TIM_DIER register  *******************/
N#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
N#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable   */
N#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable   */
N#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable   */
N#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable   */
N#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable                 */
N#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable             */
N#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable               */
N#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable            */
N#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
N#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
N#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
N#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
N#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable               */
N#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable           */
N
N/********************  Bit definition for TIM_SR register  ********************/
N#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag              */
N#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag   */
N#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag   */
N#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag   */
N#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag   */
N#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag                 */
N#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag             */
N#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag               */
N#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
N#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
N#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
N#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
N
N/*******************  Bit definition for TIM_EGR register  ********************/
N#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation                         */
N#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation              */
N#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation              */
N#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation              */
N#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation              */
N#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
N#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation                        */
N#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation                          */
N
N/******************  Bit definition for TIM_CCMR1 register  *******************/
N#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
N#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
N#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
N
N#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable                 */
N#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable              */
N
N#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
N#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
N#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
N#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
N
N#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable                 */
N
N#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
N#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
N#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
N
N#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable                 */
N#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable              */
N
N#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
N#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
N#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
N#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
N
N#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
N
N/*----------------------------------------------------------------------------*/
N
N#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
N#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
N#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
N
N#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
N#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
N#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
N#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
N#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
N
N#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
N#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
N#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
N
N#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
N#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
N#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
N#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
N#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
N
N/******************  Bit definition for TIM_CCMR2 register  *******************/
N#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
N#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
N#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
N
N#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable           */
N#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable        */
N
N#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
N#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
N#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
N#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
N
N#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
N
N#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
N#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
N#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
N
N#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable    */
N#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
N
N#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
N#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
N#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
N#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
N
N#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
N
N/*----------------------------------------------------------------------------*/
N
N#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
N#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
N#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
N
N#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
N#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
N#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
N#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
N#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
N
N#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
N#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
N#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
N
N#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
N#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
N#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
N#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
N#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
N
N/*******************  Bit definition for TIM_CCER register  *******************/
N#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable                 */
N#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity               */
N#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable   */
N#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
N#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable                 */
N#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity               */
N#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable   */
N#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
N#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable                 */
N#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity               */
N#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable   */
N#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
N#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable                 */
N#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity               */
N#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
N
N/*******************  Bit definition for TIM_CNT register  ********************/
N#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value            */
N
N/*******************  Bit definition for TIM_PSC register  ********************/
N#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value          */
N
N/*******************  Bit definition for TIM_ARR register  ********************/
N#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
N
N/*******************  Bit definition for TIM_RCR register  ********************/
N#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
N
N/*******************  Bit definition for TIM_CCR1 register  *******************/
N#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value  */
N
N/*******************  Bit definition for TIM_CCR2 register  *******************/
N#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value  */
N
N/*******************  Bit definition for TIM_CCR3 register  *******************/
N#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value  */
N
N/*******************  Bit definition for TIM_CCR4 register  *******************/
N#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value  */
N
N/*******************  Bit definition for TIM_BDTR register  *******************/
N#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
N#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
N#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
N#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
N#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
N#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
N#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
N#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
N#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
N
N#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
N#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
N#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
N
N#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
N#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode  */
N#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable                      */
N#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity                    */
N#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable           */
N#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable                */
N
N/*******************  Bit definition for TIM_DCR register  ********************/
N#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
N#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
N#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
N#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
N#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
N#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
N
N#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
N#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
N#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
N#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
N#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
N#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
N
N/*******************  Bit definition for TIM_DMAR register  *******************/
N#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses                    */
N
N/*******************  Bit definition for TIM_OR register  *********************/
N#define TIM_OR_TI4_RMP                       ((uint16_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
N#define TIM_OR_TI4_RMP_0                     ((uint16_t)0x0040)            /*!<Bit 0 */
N#define TIM_OR_TI4_RMP_1                     ((uint16_t)0x0080)            /*!<Bit 1 */
N#define TIM_OR_ITR1_RMP                      ((uint16_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
N#define TIM_OR_ITR1_RMP_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
N#define TIM_OR_ITR1_RMP_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
N
N
N/******************************************************************************/
N/*                                                                            */
N/*         Universal Synchronous Asynchronous Receiver Transmitter            */
N/*                                                                            */
N/******************************************************************************/
N/*******************  Bit definition for USART_SR register  *******************/
N#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!<Parity Error                 */
N#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!<Framing Error                */
N#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!<Noise Error Flag             */
N#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!<OverRun Error                */
N#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!<IDLE line detected           */
N#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!<Read Data Register Not Empty */
N#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!<Transmission Complete        */
N#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!<Transmit Data Register Empty */
N#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!<LIN Break Detection Flag     */
N#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!<CTS Flag                     */
N
N/*******************  Bit definition for USART_DR register  *******************/
N#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!<Data value */
N
N/******************  Bit definition for USART_BRR register  *******************/
N#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!<Fraction of USARTDIV */
N#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!<Mantissa of USARTDIV */
N
N/******************  Bit definition for USART_CR1 register  *******************/
N#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!<Send Break                             */
N#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!<Receiver wakeup                        */
N#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!<Receiver Enable                        */
N#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!<Transmitter Enable                     */
N#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!<IDLE Interrupt Enable                  */
N#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!<RXNE Interrupt Enable                  */
N#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
N#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!<PE Interrupt Enable                    */
N#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!<PE Interrupt Enable                    */
N#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!<Parity Selection                       */
N#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!<Parity Control Enable                  */
N#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!<Wakeup method                          */
N#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!<Word length                            */
N#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!<USART Enable                           */
N#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!<USART Oversampling by 8 enable         */
N
N/******************  Bit definition for USART_CR2 register  *******************/
N#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!<Address of the USART node            */
N#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!<LIN Break Detection Length           */
N#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
N#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!<Last Bit Clock pulse                 */
N#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!<Clock Phase                          */
N#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!<Clock Polarity                       */
N#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!<Clock Enable                         */
N
N#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
N#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
N#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
N
N#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!<LIN mode enable */
N
N/******************  Bit definition for USART_CR3 register  *******************/
N#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!<Error Interrupt Enable      */
N#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!<IrDA mode Enable            */
N#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!<IrDA Low-Power              */
N#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!<Half-Duplex Selection       */
N#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!<Smartcard NACK enable       */
N#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!<Smartcard mode enable       */
N#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!<DMA Enable Receiver         */
N#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!<DMA Enable Transmitter      */
N#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!<RTS Enable                  */
N#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!<CTS Enable                  */
N#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!<CTS Interrupt Enable        */
N#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!<USART One bit method enable */
N
N/******************  Bit definition for USART_GTPR register  ******************/
N#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
N#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
N#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
N#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!<Bit 2 */
N#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!<Bit 3 */
N#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!<Bit 4 */
N#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!<Bit 5 */
N#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!<Bit 6 */
N#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!<Bit 7 */
N
N#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!<Guard time value */
N
N/******************************************************************************/
N/*                                                                            */
N/*                            Window WATCHDOG                                 */
N/*                                                                            */
N/******************************************************************************/
N/*******************  Bit definition for WWDG_CR register  ********************/
N#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
N#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
N#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
N#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
N#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
N#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
N#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
N#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
N
N#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
N
N/*******************  Bit definition for WWDG_CFR register  *******************/
N#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
N#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
N#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
N#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
N#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
N#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
N#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
N#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
N
N#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
N#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
N#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
N
N#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
N
N/*******************  Bit definition for WWDG_SR register  ********************/
N#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
N
N
N/******************************************************************************/
N/*                                                                            */
N/*                                DBG                                         */
N/*                                                                            */
N/******************************************************************************/
N/********************  Bit definition for DBGMCU_IDCODE register  *************/
N#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
N#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
N
N/********************  Bit definition for DBGMCU_CR register  *****************/
N#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
N#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
N#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
N#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
N
N#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
N#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
N#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
N
N/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
N#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001)
N#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002)
N#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004)
N#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)
N#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)
N#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020)
N#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040)
N#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080)
N#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100)
N#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)
N#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)
N#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)
N#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
N#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
N#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
N#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
N#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
N/* Old IWDGSTOP bit definition, maintained for legacy purpose */
N#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
N
N/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
N#define  DBGMCU_APB1_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
N#define  DBGMCU_APB1_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
N#define  DBGMCU_APB1_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
N#define  DBGMCU_APB1_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)
N#define  DBGMCU_APB1_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
N
N/******************************************************************************/
N/*                                                                            */
N/*                Ethernet MAC Registers bits definitions                     */
N/*                                                                            */
N/******************************************************************************/
N/* Bit definition for Ethernet MAC Control Register register */
N#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
N#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
N#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
N#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
N  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
N  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
N  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
N  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
N  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
N  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
N  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
N#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
N#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
N#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
N#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
N#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
N#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
N#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
N#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
N#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
N                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
N  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
N  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
N  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
N  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
N#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
N#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
N#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
N
N/* Bit definition for Ethernet MAC Frame Filter Register */
N#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
N#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
N#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
N#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
N#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
N  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
N  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
N  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
N#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
N#define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
N#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
N#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
N#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
N#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
N
N/* Bit definition for Ethernet MAC Hash Table High Register */
N#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
N
N/* Bit definition for Ethernet MAC Hash Table Low Register */
N#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
N
N/* Bit definition for Ethernet MAC MII Address Register */
N#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
N#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
N#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
N  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
N  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
N  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
N  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
N  #define ETH_MACMIIAR_CR_Div102  ((uint32_t)0x00000010)  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
N#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
N#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
N  
N/* Bit definition for Ethernet MAC MII Data Register */
N#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
N
N/* Bit definition for Ethernet MAC Flow Control Register */
N#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
N#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
N#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
N  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
N  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
N  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
N  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
N#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
N#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
N#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
N#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
N
N/* Bit definition for Ethernet MAC VLAN Tag Register */
N#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
N#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
N
N/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
N#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
N/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
N   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
N/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
N   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
N   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
N   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
N   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
N                              RSVD - Filter1 Command - RSVD - Filter0 Command
N   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
N   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
N   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
N
N/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
N#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
N#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
N#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
N#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
N#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
N#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
N#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
N
N/* Bit definition for Ethernet MAC Status Register */
N#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
N#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
N#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
N#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
N#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
N
N/* Bit definition for Ethernet MAC Interrupt Mask Register */
N#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
N#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
N
N/* Bit definition for Ethernet MAC Address0 High Register */
N#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
N
N/* Bit definition for Ethernet MAC Address0 Low Register */
N#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
N
N/* Bit definition for Ethernet MAC Address1 High Register */
N#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
N#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
N#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
N  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
N  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
N  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
N  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
N  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
N  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
N#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
N
N/* Bit definition for Ethernet MAC Address1 Low Register */
N#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
N
N/* Bit definition for Ethernet MAC Address2 High Register */
N#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
N#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
N#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
N  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
N  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
N  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
N  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
N  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
N  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
N#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
N
N/* Bit definition for Ethernet MAC Address2 Low Register */
N#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
N
N/* Bit definition for Ethernet MAC Address3 High Register */
N#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
N#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
N#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
N  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
N  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
N  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
N  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
N  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
N  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
N#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
N
N/* Bit definition for Ethernet MAC Address3 Low Register */
N#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
N
N/******************************************************************************/
N/*                Ethernet MMC Registers bits definition                      */
N/******************************************************************************/
N
N/* Bit definition for Ethernet MMC Contol Register */
N#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020)  /* MMC counter Full-Half preset */
N#define ETH_MMCCR_MCP        ((uint32_t)0x00000010)  /* MMC counter preset */
N#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
N#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
N#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
N#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
N
N/* Bit definition for Ethernet MMC Receive Interrupt Register */
N#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
N#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
N#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
N
N/* Bit definition for Ethernet MMC Transmit Interrupt Register */
N#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
N#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
N#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
N
N/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
N#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
N#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
N#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
N
N/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
N#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
N#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
N#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
N
N/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
N#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
N
N/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
N#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
N
N/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
N#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
N
N/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
N#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
N
N/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
N#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
N
N/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
N#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
N
N/******************************************************************************/
N/*               Ethernet PTP Registers bits definition                       */
N/******************************************************************************/
N
N/* Bit definition for Ethernet PTP Time Stamp Contol Register */
N#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000)  /* Time stamp clock node type */
N#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
N#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */
N#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
N#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
N#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
N#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400)  /* Time stamp PTP packet snooping for version2 format enable */
N#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200)  /* Time stamp Sub-seconds rollover */
N#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */
N
N#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
N#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
N#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
N#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
N#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
N#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
N
N/* Bit definition for Ethernet PTP Sub-Second Increment Register */
N#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
N
N/* Bit definition for Ethernet PTP Time Stamp High Register */
N#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
N
N/* Bit definition for Ethernet PTP Time Stamp Low Register */
N#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
N#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
N
N/* Bit definition for Ethernet PTP Time Stamp High Update Register */
N#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
N
N/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
N#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
N#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
N
N/* Bit definition for Ethernet PTP Time Stamp Addend Register */
N#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
N
N/* Bit definition for Ethernet PTP Target Time High Register */
N#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
N
N/* Bit definition for Ethernet PTP Target Time Low Register */
N#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
N
N/* Bit definition for Ethernet PTP Time Stamp Status Register */
N#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020)  /* Time stamp target time reached */
N#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010)  /* Time stamp seconds overflow */
N
N/******************************************************************************/
N/*                 Ethernet DMA Registers bits definition                     */
N/******************************************************************************/
N
N/* Bit definition for Ethernet DMA Bus Mode Register */
N#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
N#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
N#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
N#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
N  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
N  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
N  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
N  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
N  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
N  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
N  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
N  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
N  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
N  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
N  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
N  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
N#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
N#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
N  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
N  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
N  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
N  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
N#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
N  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
N  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
N  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
N  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
N  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
N  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
N  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
N  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
N  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
N  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
N  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
N  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
N#define ETH_DMABMR_EDE       ((uint32_t)0x00000080)  /* Enhanced Descriptor Enable */
N#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
N#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
N#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
N
N/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
N#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
N
N/* Bit definition for Ethernet DMA Receive Poll Demand Register */
N#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
N
N/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
N#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
N
N/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
N#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
N
N/* Bit definition for Ethernet DMA Status Register */
N#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
N#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
N#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
N#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
N  /* combination with EBS[2:0] for GetFlagStatus function */
N  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
N  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
N  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
N#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
N  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
N  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
N  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
N  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
N  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
N  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
N#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
N  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
N  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
N  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
N  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
N  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
N  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
N#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
N#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
N#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
N#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
N#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
N#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
N#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
N#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
N#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
N#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
N#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
N#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
N#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
N#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
N#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
N
N/* Bit definition for Ethernet DMA Operation Mode Register */
N#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
N#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
N#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
N#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
N#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
N#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
N  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
N  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
N  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
N  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
N  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
N  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
N  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
N  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
N#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
N#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
N#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
N#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
N  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
N  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
N  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
N  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
N#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
N#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
N
N/* Bit definition for Ethernet DMA Interrupt Enable Register */
N#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
N#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
N#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
N#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
N#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
N#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
N#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
N#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
N#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
N#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
N#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
N#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
N#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
N#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
N#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
N
N/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
N#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
N#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
N#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
N#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
N
N/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
N#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
N
N/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
N#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
N
N/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
N#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
N
N/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
N#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
N
N/**
N  *
N  */
N
N /**
N  * @}
N  */ 
N
N#ifdef USE_STDPERIPH_DRIVER
N  #include "stm32f4xx_conf.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 1
N/**
N  ******************************************************************************
N  * @file    Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h  
N  * @author  MCD Application Team
N  * @version V1.4.0
N  * @date    04-August-2014
N  * @brief   Library configuration file.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_CONF_H
N#define __STM32F4xx_CONF_H
N
N/* Includes ------------------------------------------------------------------*/
N/* Uncomment the line below to enable peripheral header file inclusion */
N#include "stm32f4xx_adc.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_adc.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_adc.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the ADC firmware 
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_ADC_H
N#define __STM32F4xx_ADC_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File. 
N  *          This file contains all the peripheral register's definitions, bits 
N  *          definitions and memory mapping for STM32F4xx devices.            
N  *            
N  *          The file is the unique include file that the application programmer
N  *          is using in the C source code, usually in main.c. This file contains:
N  *           - Configuration section that allows to select:
N  *              - The device used in the target application
N  *              - To use or not the peripheral抯 drivers in application code(i.e. 
N  *                code will be based on direct access to peripheral抯 registers 
N  *                rather than drivers API), this option is controlled by 
N  *                "#define USE_STDPERIPH_DRIVER"
N  *              - To change few application-specific parameters such as the HSE 
N  *                crystal frequency
N  *           - Data structures and the address mapping for all peripherals
N  *           - Peripheral's registers declarations and bits definition
N  *           - Macros to access peripheral抯 registers hardware
N  *  
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************  
N  */ 
N
N/** @addtogroup CMSIS
N  * @{
N  */
N
N/** @addtogroup stm32f4xx
N  * @{
N  */
N    
N#ifndef __STM32F4xx_H
S#define __STM32F4xx_H
S
S#ifdef __cplusplus
S extern "C" {
S#endif /* __cplusplus */
S  
S/** @addtogroup Library_configuration_section
S  * @{
S  */
S  
S/* Uncomment the line below according to the target STM32 device used in your
S   application 
S  */
S
S#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F411xE) && \
S    !defined(STM32F446xx)
X#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F411xE) &&     !defined(STM32F446xx)
S  /* #define STM32F40_41xxx */   /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG,  
S                                      STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, 
S                                      STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
S
S  /* #define STM32F427_437xx */  /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II,  
S                                      STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */
S
S  /* #define STM32F429_439xx */  /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI,  
S                                      STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, 
S                                      STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI,
S                                      STM32F439IG and STM32F439II Devices */
S
S  /* #define STM32F401xx */      /*!< STM32F401CB, STM32F401CC,  STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC  
S                                      STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */
S
S  /* #define STM32F411xE */      /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
S  
S  /* #define STM32F446xx */      /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC 
S                                      and STM32F446ZE Devices */
S#endif
S
S/* Old STM32F40XX definition, maintained for legacy purpose */
S#ifdef STM32F40XX
S  #define STM32F40_41xxx
S#endif /* STM32F40XX */
S
S/* Old STM32F427X definition, maintained for legacy purpose */
S#ifdef STM32F427X
S  #define STM32F427_437xx
S#endif /* STM32F427X */
S
S/*  Tip: To avoid modifying this file each time you need to switch between these
S        devices, you can define the device in your toolchain compiler preprocessor.
S  */
S
S#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F411xE) && \
S    !defined(STM32F446xx)  
X#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F411xE) &&     !defined(STM32F446xx)  
S #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
S#endif
S
S#if !defined  (USE_STDPERIPH_DRIVER)
S/**
S * @brief Comment the line below if you will not use the peripherals drivers.
S   In this case, these drivers will not be included and the application code will 
S   be based on direct access to peripherals registers 
S   */
S  /*#define USE_STDPERIPH_DRIVER */
S#endif /* USE_STDPERIPH_DRIVER */
S
S/**
S * @brief In the following line adjust the value of External High Speed oscillator (HSE)
S   used in your application 
S   
S   Tip: To avoid modifying this file each time you need to use different HSE, you
S        can define the HSE value in your toolchain compiler preprocessor.
S  */           
S#if defined(STM32F40_41xxx) || defined(STM32F427_437xx)  || defined(STM32F429_439xx) || defined(STM32F401xx)  || defined(STM32F411xE)
S #if !defined  (HSE_VALUE) 
S  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
S#endif /* HSE_VALUE */
S#elif defined(STM32F446xx)
S #if !defined  (HSE_VALUE) 
S  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
S#endif /* HSE_VALUE */
S#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
S/**
S * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
S   Timeout value 
S   */
S#if !defined  (HSE_STARTUP_TIMEOUT) 
S  #define HSE_STARTUP_TIMEOUT    ((uint16_t)0x05000)   /*!< Time out for HSE start up */
S#endif /* HSE_STARTUP_TIMEOUT */   
S
S#if !defined  (HSI_VALUE)   
S  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
S#endif /* HSI_VALUE */   
S
S/**
S * @brief STM32F4XX Standard Peripherals Library version number V1.5.0
S   */
S#define __STM32F4XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
S#define __STM32F4XX_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
S#define __STM32F4XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
S#define __STM32F4XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
S#define __STM32F4XX_STDPERIPH_VERSION        ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
S                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
S                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
S                                             |(__STM32F4XX_STDPERIPH_VERSION_RC))
X#define __STM32F4XX_STDPERIPH_VERSION        ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)                                             |(__STM32F4XX_STDPERIPH_VERSION_RC))
S                                             
S/**
S  * @}
S  */
S
S/** @addtogroup Configuration_section_for_CMSIS
S  * @{
S  */
S
S/**
S * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
S */
S#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
S#define __MPU_PRESENT             1       /*!< STM32F4XX provides an MPU                     */
S#define __NVIC_PRIO_BITS          4       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
S#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
S#define __FPU_PRESENT             1       /*!< FPU present                                   */
S
S/**
S * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
S *        in @ref Library_configuration_section 
S */
Stypedef enum IRQn
S{
S/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
S  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
S  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
S  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
S  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
S  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
S  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
S  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
S  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
S/******  STM32 specific Interrupt Numbers **********************************************************************/
S  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
S  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
S  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
S  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
S  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
S  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
S  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
S  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
S  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
S  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
S  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
S  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
S  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
S  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
S  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
S  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
S  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
S  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
S  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
S
S#if defined(STM32F40_41xxx)
S  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
S  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
S  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
S  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
S  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
S  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
S  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
S  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
S  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
S  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
S  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
S  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
S  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
S  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
S  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
S  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
S  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
S  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
S  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
S  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
S  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
S  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
S  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
S  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
S  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
S  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
S  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
S  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
S  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
S  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
S  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
S  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
S  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
S  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
S  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
S  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
S  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
S  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
S  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
S  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
S  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
S  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
S  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
S  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
S  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
S  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
S  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
S  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
S  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
S  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
S  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
S  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
S  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
S  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
S  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
S  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
S  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
S  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
S  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
S  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
S  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
S  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
S  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
S#endif /* STM32F40_41xxx */
S
S#if defined(STM32F427_437xx)
S  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
S  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
S  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
S  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
S  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
S  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
S  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
S  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
S  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
S  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
S  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
S  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
S  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
S  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
S  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
S  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
S  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
S  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
S  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
S  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
S  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
S  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
S  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
S  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
S  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
S  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
S  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
S  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
S  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
S  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
S  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
S  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
S  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
S  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
S  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
S  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
S  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
S  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
S  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
S  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
S  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
S  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
S  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
S  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
S  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
S  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
S  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
S  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
S  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
S  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
S  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
S  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
S  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
S  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
S  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
S  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
S  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
S  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
S  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
S  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
S  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
S  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
S  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
S  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
S  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
S  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
S  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
S  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
S  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
S  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */   
S#endif /* STM32F427_437xx */
S    
S#if defined(STM32F429_439xx)
S  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
S  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
S  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
S  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
S  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
S  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
S  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
S  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
S  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
S  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
S  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
S  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
S  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
S  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
S  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
S  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
S  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
S  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
S  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
S  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
S  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
S  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
S  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
S  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
S  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
S  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
S  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
S  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
S  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
S  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
S  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
S  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
S  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
S  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
S  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
S  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
S  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
S  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
S  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
S  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
S  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
S  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
S  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
S  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
S  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
S  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
S  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
S  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
S  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
S  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
S  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
S  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
S  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
S  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
S  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
S  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
S  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
S  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
S  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
S  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
S  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
S  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
S  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
S  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
S  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
S  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
S  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
S  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
S  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
S  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
S  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
S  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */
S#endif /* STM32F429_439xx */
S   
S#if defined(STM32F401xx) || defined(STM32F411xE)
S  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
S  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
S  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
S  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
S  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
S  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
S  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
S  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
S  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
S  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
S  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
S  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
S  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
S  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
S  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
S  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
S  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
S  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
S  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
S  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
S  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
S  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
S  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
S  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
S  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
S  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
S  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
S  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
S  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
S  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
S  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
S  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
S  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
S  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
S  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
S  FPU_IRQn                    = 81,      /*!< FPU global interrupt                                             */
S#if defined(STM32F401xx)
S  SPI4_IRQn                   = 84       /*!< SPI4 global Interrupt                                            */
S#endif /* STM32F411xE */
S#if defined(STM32F411xE)
S  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
S  SPI5_IRQn                   = 85      /*!< SPI5 global Interrupt                                             */
S#endif /* STM32F411xE */
S#endif /* STM32F401xx || STM32F411xE */
S
S#if defined(STM32F446xx)
S  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
S  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
S  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
S  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
S  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
S  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
S  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
S  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
S  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
S  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
S  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
S  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
S  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
S  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
S  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
S  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
S  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
S  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
S  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
S  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
S  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
S  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
S  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
S  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
S  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */
S  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
S  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
S  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
S  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
S  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
S  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
S  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
S  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
S  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
S  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
S  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
S  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
S  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
S  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
S  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
S  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
S  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
S  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
S  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
S  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
S  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
S  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
S  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
S  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
S  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
S  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
S  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
S  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
S  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
S  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
S  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
S  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
S  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
S  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
S  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
S  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
S  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
S  QUADSPI_IRQn                = 92,     /*!< QuadSPI global Interrupt                                          */
S  CEC_IRQn                    = 93,     /*!< QuadSPI global Interrupt                                          */
S  SPDIF_RX_IRQn               = 94,     /*!< QuadSPI global Interrupt                                          */
S  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C Event Interrupt                                            */
S  FMPI2C1_ER_IRQn             = 96      /*!< FMPCI2C Error Interrupt                                           */    
S#endif /* STM32F446xx */    
S} IRQn_Type;
S
S/**
S  * @}
S  */
S
S#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
S#include "system_stm32f4xx.h"
S#include <stdint.h>
S
S/** @addtogroup Exported_types
S  * @{
S  */  
S/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
Stypedef int32_t  s32;
Stypedef int16_t s16;
Stypedef int8_t  s8;
S
Stypedef const int32_t sc32;  /*!< Read Only */
Stypedef const int16_t sc16;  /*!< Read Only */
Stypedef const int8_t sc8;   /*!< Read Only */
S
Stypedef __IO int32_t  vs32;
Stypedef __IO int16_t  vs16;
Stypedef __IO int8_t   vs8;
S
Stypedef __I int32_t vsc32;  /*!< Read Only */
Stypedef __I int16_t vsc16;  /*!< Read Only */
Stypedef __I int8_t vsc8;   /*!< Read Only */
S
Stypedef uint32_t  u32;
Stypedef uint16_t u16;
Stypedef uint8_t  u8;
S
Stypedef const uint32_t uc32;  /*!< Read Only */
Stypedef const uint16_t uc16;  /*!< Read Only */
Stypedef const uint8_t uc8;   /*!< Read Only */
S
Stypedef __IO uint32_t  vu32;
Stypedef __IO uint16_t vu16;
Stypedef __IO uint8_t  vu8;
S
Stypedef __I uint32_t vuc32;  /*!< Read Only */
Stypedef __I uint16_t vuc16;  /*!< Read Only */
Stypedef __I uint8_t vuc8;   /*!< Read Only */
S
Stypedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
S
Stypedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
S#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
S
Stypedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
S
S/**
S  * @}
S  */
S
S/** @addtogroup Peripheral_registers_structures
S  * @{
S  */   
S
S/** 
S  * @brief Analog to Digital Converter  
S  */
S
Stypedef struct
S{
S  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
S  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
S  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
S  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
S  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
S  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
S  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
S  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
S  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
S  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
S  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
S  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
S  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
S  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
S  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
S  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
S  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
S  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
S  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
S  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
S} ADC_TypeDef;
S
Stypedef struct
S{
S  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
S  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
S  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
S                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
S} ADC_Common_TypeDef;
S
S
S/** 
S  * @brief Controller Area Network TxMailBox 
S  */
S
Stypedef struct
S{
S  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
S  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
S  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
S  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
S} CAN_TxMailBox_TypeDef;
S
S/** 
S  * @brief Controller Area Network FIFOMailBox 
S  */
S  
Stypedef struct
S{
S  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
S  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
S  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
S  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
S} CAN_FIFOMailBox_TypeDef;
S
S/** 
S  * @brief Controller Area Network FilterRegister 
S  */
S  
Stypedef struct
S{
S  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
S  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
S} CAN_FilterRegister_TypeDef;
S
S/** 
S  * @brief Controller Area Network 
S  */
S  
Stypedef struct
S{
S  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
S  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
S  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
S  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
S  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
S  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
S  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
S  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
S  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
S  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
S  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
S  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
S  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
S  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
S  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
S  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
S  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
S  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
S  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
S  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
S  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
S  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
S} CAN_TypeDef;
S
S#if defined(STM32F446xx)
S/**
S  * @brief Consumer Electronics Control
S  */
Stypedef struct
S{
S  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
S  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
S  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
S  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
S  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
S  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
S}CEC_TypeDef;
S#endif /* STM32F446xx */
S
S/** 
S  * @brief CRC calculation unit 
S  */
S
Stypedef struct
S{
S  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
S  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
S  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
S  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
S  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
S} CRC_TypeDef;
S
S/** 
S  * @brief Digital to Analog Converter
S  */
S
Stypedef struct
S{
S  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
S  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
S  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
S  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
S  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
S  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
S  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
S  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
S  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
S  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
S  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
S  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
S  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
S  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
S} DAC_TypeDef;
S
S/** 
S  * @brief Debug MCU
S  */
S
Stypedef struct
S{
S  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
S  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
S  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
S  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
S}DBGMCU_TypeDef;
S
S/** 
S  * @brief DCMI
S  */
S
Stypedef struct
S{
S  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
S  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
S  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
S  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
S  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
S  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
S  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
S  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
S  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
S  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
S  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
S} DCMI_TypeDef;
S
S/** 
S  * @brief DMA Controller
S  */
S
Stypedef struct
S{
S  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
S  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
S  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
S  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
S  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
S  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
S} DMA_Stream_TypeDef;
S
Stypedef struct
S{
S  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
S  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
S  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
S  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
S} DMA_TypeDef;
S 
S/** 
S  * @brief DMA2D Controller
S  */
S
Stypedef struct
S{
S  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
S  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
S  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
S  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
S  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
S  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
S  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
S  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
S  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
S  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
S  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
S  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
S  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
S  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
S  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
S  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
S  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
S  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
S  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
S  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
S  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
S  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
S  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
S} DMA2D_TypeDef;
S
S/** 
S  * @brief Ethernet MAC
S  */
S
Stypedef struct
S{
S  __IO uint32_t MACCR;
S  __IO uint32_t MACFFR;
S  __IO uint32_t MACHTHR;
S  __IO uint32_t MACHTLR;
S  __IO uint32_t MACMIIAR;
S  __IO uint32_t MACMIIDR;
S  __IO uint32_t MACFCR;
S  __IO uint32_t MACVLANTR;             /*    8 */
S  uint32_t      RESERVED0[2];
S  __IO uint32_t MACRWUFFR;             /*   11 */
S  __IO uint32_t MACPMTCSR;
S  uint32_t      RESERVED1[2];
S  __IO uint32_t MACSR;                 /*   15 */
S  __IO uint32_t MACIMR;
S  __IO uint32_t MACA0HR;
S  __IO uint32_t MACA0LR;
S  __IO uint32_t MACA1HR;
S  __IO uint32_t MACA1LR;
S  __IO uint32_t MACA2HR;
S  __IO uint32_t MACA2LR;
S  __IO uint32_t MACA3HR;
S  __IO uint32_t MACA3LR;               /*   24 */
S  uint32_t      RESERVED2[40];
S  __IO uint32_t MMCCR;                 /*   65 */
S  __IO uint32_t MMCRIR;
S  __IO uint32_t MMCTIR;
S  __IO uint32_t MMCRIMR;
S  __IO uint32_t MMCTIMR;               /*   69 */
S  uint32_t      RESERVED3[14];
S  __IO uint32_t MMCTGFSCCR;            /*   84 */
S  __IO uint32_t MMCTGFMSCCR;
S  uint32_t      RESERVED4[5];
S  __IO uint32_t MMCTGFCR;
S  uint32_t      RESERVED5[10];
S  __IO uint32_t MMCRFCECR;
S  __IO uint32_t MMCRFAECR;
S  uint32_t      RESERVED6[10];
S  __IO uint32_t MMCRGUFCR;
S  uint32_t      RESERVED7[334];
S  __IO uint32_t PTPTSCR;
S  __IO uint32_t PTPSSIR;
S  __IO uint32_t PTPTSHR;
S  __IO uint32_t PTPTSLR;
S  __IO uint32_t PTPTSHUR;
S  __IO uint32_t PTPTSLUR;
S  __IO uint32_t PTPTSAR;
S  __IO uint32_t PTPTTHR;
S  __IO uint32_t PTPTTLR;
S  __IO uint32_t RESERVED8;
S  __IO uint32_t PTPTSSR;
S  uint32_t      RESERVED9[565];
S  __IO uint32_t DMABMR;
S  __IO uint32_t DMATPDR;
S  __IO uint32_t DMARPDR;
S  __IO uint32_t DMARDLAR;
S  __IO uint32_t DMATDLAR;
S  __IO uint32_t DMASR;
S  __IO uint32_t DMAOMR;
S  __IO uint32_t DMAIER;
S  __IO uint32_t DMAMFBOCR;
S  __IO uint32_t DMARSWTR;
S  uint32_t      RESERVED10[8];
S  __IO uint32_t DMACHTDR;
S  __IO uint32_t DMACHRDR;
S  __IO uint32_t DMACHTBAR;
S  __IO uint32_t DMACHRBAR;
S} ETH_TypeDef;
S
S/** 
S  * @brief External Interrupt/Event Controller
S  */
S
Stypedef struct
S{
S  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
S  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
S  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
S  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
S  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
S  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
S} EXTI_TypeDef;
S
S/** 
S  * @brief FLASH Registers
S  */
S
Stypedef struct
S{
S  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
S  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
S  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
S  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
S  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
S  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
S  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
S} FLASH_TypeDef;
S
S#if defined(STM32F40_41xxx)
S/** 
S  * @brief Flexible Static Memory Controller
S  */
S
Stypedef struct
S{
S  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
S} FSMC_Bank1_TypeDef; 
S
S/** 
S  * @brief Flexible Static Memory Controller Bank1E
S  */
S  
Stypedef struct
S{
S  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
S} FSMC_Bank1E_TypeDef;
S
S/** 
S  * @brief Flexible Static Memory Controller Bank2
S  */
S  
Stypedef struct
S{
S  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
S  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
S  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
S  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
S  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
S  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
S} FSMC_Bank2_TypeDef;
S
S/** 
S  * @brief Flexible Static Memory Controller Bank3
S  */
S  
Stypedef struct
S{
S  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
S  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
S  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
S  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
S  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
S  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
S} FSMC_Bank3_TypeDef;
S
S/** 
S  * @brief Flexible Static Memory Controller Bank4
S  */
S  
Stypedef struct
S{
S  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
S  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
S  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
S  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
S  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
S} FSMC_Bank4_TypeDef; 
S#endif /* STM32F40_41xxx */
S
S#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
S/** 
S  * @brief Flexible Memory Controller
S  */
S
Stypedef struct
S{
S  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
S} FMC_Bank1_TypeDef; 
S
S/** 
S  * @brief Flexible Memory Controller Bank1E
S  */
S  
Stypedef struct
S{
S  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
S} FMC_Bank1E_TypeDef;
S
S/** 
S  * @brief Flexible Memory Controller Bank2
S  */
S  
Stypedef struct
S{
S  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
S  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
S  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
S  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
S  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
S  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
S} FMC_Bank2_TypeDef;
S
S/** 
S  * @brief Flexible Memory Controller Bank3
S  */
S  
Stypedef struct
S{
S  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
S  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
S  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
S  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
S  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
S  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
S} FMC_Bank3_TypeDef;
S
S/** 
S  * @brief Flexible Memory Controller Bank4
S  */
S  
Stypedef struct
S{
S  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
S  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
S  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
S  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
S  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
S} FMC_Bank4_TypeDef; 
S
S/** 
S  * @brief Flexible Memory Controller Bank5_6
S  */
S  
Stypedef struct
S{
S  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
S  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
S  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
S  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
S  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
S} FMC_Bank5_6_TypeDef; 
S#endif /* STM32F427_437xx ||  STM32F429_439xx || STM32F446xx */
S
S/** 
S  * @brief General Purpose I/O
S  */
S
Stypedef struct
S{
S  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
S  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
S  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
S  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
S  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
S  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
S  __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
S  __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
S  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
S  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
S} GPIO_TypeDef;
S
S/** 
S  * @brief System configuration controller
S  */
S  
Stypedef struct
S{
S  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
S  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
S  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
S  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
S  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
S} SYSCFG_TypeDef;
S
S/** 
S  * @brief Inter-integrated Circuit Interface
S  */
S
Stypedef struct
S{
S  __IO uint16_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
S  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                   */
S  __IO uint16_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
S  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                   */
S  __IO uint16_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
S  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                   */
S  __IO uint16_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
S  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                   */
S  __IO uint16_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
S  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                   */
S  __IO uint16_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
S  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                   */
S  __IO uint16_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
S  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                   */
S  __IO uint16_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
S  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                   */
S  __IO uint16_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
S  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                   */
S  __IO uint16_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
S  uint16_t      RESERVED9;  /*!< Reserved, 0x26                                   */
S} I2C_TypeDef;
S
S#if defined(STM32F446xx)
S/**
S  * @brief Inter-integrated Circuit Interface
S  */
S
Stypedef struct
S{
S  __IO uint32_t CR1;      /*!< FMPI2C Control register 1,            Address offset: 0x00 */
S  __IO uint32_t CR2;      /*!< FMPI2C Control register 2,            Address offset: 0x04 */
S  __IO uint32_t OAR1;     /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */
S  __IO uint32_t OAR2;     /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */
S  __IO uint32_t TIMINGR;  /*!< FMPI2C Timing register,               Address offset: 0x10 */
S  __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register,              Address offset: 0x14 */
S  __IO uint32_t ISR;      /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
S  __IO uint32_t ICR;      /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */
S  __IO uint32_t PECR;     /*!< FMPI2C PEC register,                  Address offset: 0x20 */
S  __IO uint32_t RXDR;     /*!< FMPI2C Receive data register,         Address offset: 0x24 */
S  __IO uint32_t TXDR;     /*!< FMPI2C Transmit data register,        Address offset: 0x28 */
S}FMPI2C_TypeDef;
S#endif /* STM32F446xx */
S
S/** 
S  * @brief Independent WATCHDOG
S  */
S
Stypedef struct
S{
S  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
S  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
S  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
S  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
S} IWDG_TypeDef;
S
S/** 
S  * @brief LCD-TFT Display Controller
S  */
S  
Stypedef struct
S{
S  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
S  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
S  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
S  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
S  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
S  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
S  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
S  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
S  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
S  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
S  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
S  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
S  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
S  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
S  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
S  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
S  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                       Address offset: 0x48 */
S} LTDC_TypeDef;  
S
S/** 
S  * @brief LCD-TFT Display layer x Controller
S  */
S  
Stypedef struct
S{  
S  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
S  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
S  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
S  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
S  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
S  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
S  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
S  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
S  uint32_t      RESERVED0[2];  /*!< Reserved */
S  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
S  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
S  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
S  uint32_t      RESERVED1[3];  /*!< Reserved */
S  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
S
S} LTDC_Layer_TypeDef;
S
S/** 
S  * @brief Power Control
S  */
S
Stypedef struct
S{
S  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
S  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
S} PWR_TypeDef;
S
S/** 
S  * @brief Reset and Clock Control
S  */
S
Stypedef struct
S{
S  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
S  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
S  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
S  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
S  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
S  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
S  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
S  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
S  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
S  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
S  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
S  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
S  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
S  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
S  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
S  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
S  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
S  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
S  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
S  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
S  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
S  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
S  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
S  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
S  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
S  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
S  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
S  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
S  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
S  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
S  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
S  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
S  __IO uint32_t CKGATENR;      /*!< RCC Clocks Gated Enable Register,                            Address offset: 0x90 */ /* Only for STM32F446xx devices */
S  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */ /* Only for STM32F446xx devices */
S
S} RCC_TypeDef;
S
S/** 
S  * @brief Real-Time Clock
S  */
S
Stypedef struct
S{
S  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
S  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
S  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
S  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
S  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
S  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
S  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
S  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
S  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
S  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
S  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
S  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
S  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
S  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
S  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
S  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
S  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
S  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
S  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
S  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
S  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
S  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
S  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
S  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
S  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
S  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
S  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
S  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
S  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
S  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
S  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
S  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
S  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
S  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
S  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
S  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
S  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
S  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
S  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
S  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
S} RTC_TypeDef;
S
S
S/** 
S  * @brief Serial Audio Interface
S  */
S  
Stypedef struct
S{
S  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
S} SAI_TypeDef;
S
Stypedef struct
S{
S  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
S  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
S  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
S  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
S  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
S  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
S  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
S  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
S} SAI_Block_TypeDef;
S
S/** 
S  * @brief SD host Interface
S  */
S
Stypedef struct
S{
S  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
S  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
S  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
S  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
S  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
S  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
S  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
S  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
S  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
S  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
S  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
S  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
S  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
S  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
S  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
S  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
S  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
S  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
S  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
S  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
S} SDIO_TypeDef;
S
S/** 
S  * @brief Serial Peripheral Interface
S  */
S
Stypedef struct
S{
S  __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
S  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */
S  __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
S  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */
S  __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
S  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */
S  __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
S  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */
S  __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
S  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */
S  __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
S  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */
S  __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
S  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */
S  __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
S  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */
S  __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
S  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */
S} SPI_TypeDef;
S
S#if defined(STM32F446xx)
S/** 
S  * @brief SPDIFRX Interface
S  */
Stypedef struct
S{
S  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
S  __IO uint16_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
S  uint16_t        RESERVED0;    /*!< Reserved,  0x06                                          */  
S  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
S  __IO uint16_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
S  uint16_t        RESERVED1;    /*!< Reserved,  0x0E                                          */   
S  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
S  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
S   __IO uint32_t  DIR;          /*!< Debug Information register,         Address offset: 0x18 */
S  uint16_t        RESERVED2;    /*!< Reserved,  0x1A                                          */   
S} SPDIFRX_TypeDef;
S
S/** 
S  * @brief QUAD Serial Peripheral Interface
S  */
Stypedef struct
S{
S  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
S  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
S  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
S  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
S  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
S  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
S  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
S  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
S  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
S  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
S  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */                  
S  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
S  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */    
S} QUADSPI_TypeDef;
S#endif /* STM32F446xx */
S
S#if defined(STM32F446xx)
S/** 
S  * @brief SPDIF-RX Interface
S  */
Stypedef struct
S{
S  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
S  __IO uint16_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
S  uint16_t        RESERVED0;    /*!< Reserved,  0x06                                          */  
S  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
S  __IO uint16_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
S  uint16_t        RESERVED1;    /*!< Reserved,  0x0E                                          */   
S  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
S  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
S   __IO uint32_t  DIR;          /*!< Debug Information register,         Address offset: 0x18 */
S  uint16_t        RESERVED2;    /*!< Reserved,  0x1A                                          */   
S} SPDIF_TypeDef;
S#endif /* STM32F446xx */
S
S/** 
S  * @brief TIM
S  */
S
Stypedef struct
S{
S  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
S  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
S  __IO uint16_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
S  uint16_t      RESERVED1;   /*!< Reserved, 0x06                                            */
S  __IO uint16_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
S  uint16_t      RESERVED2;   /*!< Reserved, 0x0A                                            */
S  __IO uint16_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
S  uint16_t      RESERVED3;   /*!< Reserved, 0x0E                                            */
S  __IO uint16_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
S  uint16_t      RESERVED4;   /*!< Reserved, 0x12                                            */
S  __IO uint16_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
S  uint16_t      RESERVED5;   /*!< Reserved, 0x16                                            */
S  __IO uint16_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
S  uint16_t      RESERVED6;   /*!< Reserved, 0x1A                                            */
S  __IO uint16_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
S  uint16_t      RESERVED7;   /*!< Reserved, 0x1E                                            */
S  __IO uint16_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
S  uint16_t      RESERVED8;   /*!< Reserved, 0x22                                            */
S  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
S  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
S  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
S  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
S  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
S  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
S  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
S  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
S  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
S  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
S  __IO uint16_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
S  uint16_t      RESERVED11;  /*!< Reserved, 0x46                                            */
S  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
S  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
S  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
S  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
S  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
S  uint16_t      RESERVED14;  /*!< Reserved, 0x52                                            */
S} TIM_TypeDef;
S
S/** 
S  * @brief Universal Synchronous Asynchronous Receiver Transmitter
S  */
S 
Stypedef struct
S{
S  __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
S  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
S  __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
S  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
S  __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
S  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
S  __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
S  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
S  __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
S  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
S  __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
S  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
S  __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
S  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
S} USART_TypeDef;
S
S/** 
S  * @brief Window WATCHDOG
S  */
S
Stypedef struct
S{
S  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
S  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
S  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
S} WWDG_TypeDef;
S
S/** 
S  * @brief Crypto Processor
S  */
S
Stypedef struct
S{
S  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
S  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
S  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
S  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
S  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
S  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
S  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
S  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
S  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
S  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
S  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
S  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
S  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
S  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
S  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
S  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
S  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
S  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
S  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
S  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
S  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
S  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
S  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
S  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
S  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
S  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
S  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
S  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
S  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
S  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
S  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
S  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
S  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
S  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
S  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
S  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
S} CRYP_TypeDef;
S
S/** 
S  * @brief HASH
S  */
S  
Stypedef struct 
S{
S  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
S  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
S  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
S  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
S  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
S  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
S       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
S  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
S} HASH_TypeDef;
S
S/** 
S  * @brief HASH_DIGEST
S  */
S  
Stypedef struct 
S{
S  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ 
S} HASH_DIGEST_TypeDef;
S
S/** 
S  * @brief RNG
S  */
S  
Stypedef struct 
S{
S  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
S  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
S  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
S} RNG_TypeDef;
S
S/**
S  * @}
S  */
S  
S/** @addtogroup Peripheral_memory_map
S  * @{
S  */
S#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
S#define CCMDATARAM_BASE       ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
S#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
S#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
S#define SRAM3_BASE            ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region                              */
S#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
S#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
S
S#if defined(STM32F40_41xxx)
S#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address                                                */
S#endif /* STM32F40_41xxx */
S
S#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
S#define FMC_R_BASE            ((uint32_t)0xA0000000) /*!< FMC registers base address                                                 */
S#endif /* STM32F427_437xx ||  STM32F429_439xx || STM32F446xx */
S
S#if defined(STM32F446xx)
S#define QSPI_R_BASE           ((uint32_t)0xA0001000) /*!< QuadSPI registers base address                                            */
S#endif /* STM32F446xx */
S
S#define CCMDATARAM_BB_BASE    ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region  */
S#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                             */
S#define SRAM2_BB_BASE         ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region                              */
S#define SRAM3_BB_BASE         ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region                              */
S#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                                */
S#define BKPSRAM_BB_BASE       ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
S
S/* Legacy defines */
S#define SRAM_BASE             SRAM1_BASE
S#define SRAM_BB_BASE          SRAM1_BB_BASE
S
S
S/*!< Peripheral memory map */
S#define APB1PERIPH_BASE       PERIPH_BASE
S#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
S#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
S#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
S
S/*!< APB1 peripherals */
S#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
S#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
S#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
S#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
S#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
S#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
S#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
S#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
S#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
S#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
S#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
S#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
S#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)
S#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
S#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
S#if defined(STM32F446xx)
S#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000)
S#endif /* STM32F446xx */
S#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)
S#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
S#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
S#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
S#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
S#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
S#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
S#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
S#if defined(STM32F446xx)
S#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000)
S#endif /* STM32F446xx */
S#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
S#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
S#if defined(STM32F446xx)
S#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00)
S#endif /* STM32F446xx */
S#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
S#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
S#define UART7_BASE            (APB1PERIPH_BASE + 0x7800)
S#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00)
S
S/*!< APB2 peripherals */
S#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
S#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
S#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
S#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
S#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
S#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
S#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
S#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
S#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
S#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
S#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400)
S#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
S#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
S#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
S#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
S#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
S#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000)
S#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400)
S#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800)
S#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
S#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
S#if defined(STM32F446xx)
S#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00)
S#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004)
S#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)
S#endif /* STM32F446xx */
S#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800)
S#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84)
S#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104)
S
S/*!< AHB1 peripherals */
S#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
S#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
S#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
S#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
S#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
S#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
S#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
S#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
S#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
S#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400)
S#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800)
S#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
S#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
S#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
S#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
S#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
S#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
S#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
S#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
S#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
S#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
S#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
S#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
S#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
S#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
S#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
S#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
S#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
S#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
S#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
S#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
S#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
S#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
S#define ETH_MAC_BASE          (ETH_BASE)
S#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
S#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
S#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
S#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000)
S
S/*!< AHB2 peripherals */
S#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
S#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000)
S#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400)
S#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710)
S#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
S
S#if defined(STM32F40_41xxx)
S/*!< FSMC Bankx registers base address */
S#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
S#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
S#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)
S#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)
S#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
S#endif /* STM32F40_41xxx */
S
S#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
S/*!< FMC Bankx registers base address */
S#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000)
S#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104)
S#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060)
S#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080)
S#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0)
S#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140)
S#endif /* STM32F427_437xx ||  STM32F429_439xx || STM32F446xx */
S
S/* Debug MCU registers base address */
S#define DBGMCU_BASE           ((uint32_t )0xE0042000)
S
S/**
S  * @}
S  */
S  
S/** @addtogroup Peripheral_declaration
S  * @{
S  */
S#if defined(STM32F446xx)
S#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
S#endif /* STM32F446xx */
S#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
S#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
S#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
S#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
S#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
S#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
S#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
S#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
S#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
S#define RTC                 ((RTC_TypeDef *) RTC_BASE)
S#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
S#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
S#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
S#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
S#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
S#if defined(STM32F446xx)
S#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
S#endif /* STM32F446xx */
S#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
S#define USART2              ((USART_TypeDef *) USART2_BASE)
S#define USART3              ((USART_TypeDef *) USART3_BASE)
S#define UART4               ((USART_TypeDef *) UART4_BASE)
S#define UART5               ((USART_TypeDef *) UART5_BASE)
S#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
S#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
S#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
S#if defined(STM32F446xx)
S#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)
S#endif /* STM32F446xx */
S#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
S#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
S#if defined(STM32F446xx)
S#define CEC                 ((CEC_TypeDef *) CEC_BASE)
S#endif /* STM32F446xx */
S#define PWR                 ((PWR_TypeDef *) PWR_BASE)
S#define DAC                 ((DAC_TypeDef *) DAC_BASE)
S#define UART7               ((USART_TypeDef *) UART7_BASE)
S#define UART8               ((USART_TypeDef *) UART8_BASE)
S#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
S#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
S#define USART1              ((USART_TypeDef *) USART1_BASE)
S#define USART6              ((USART_TypeDef *) USART6_BASE)
S#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
S#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
S#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
S#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
S#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
S#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
S#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
S#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
S#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
S#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
S#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
S#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
S#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
S#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
S#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
S#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
S#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
S#if defined(STM32F446xx)
S#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
S#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
S#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
S#endif /* STM32F446xx */
S#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
S#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
S#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
S#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
S#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
S#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
S#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
S#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
S#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
S#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
S#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
S#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
S#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
S#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
S#define CRC                 ((CRC_TypeDef *) CRC_BASE)
S#define RCC                 ((RCC_TypeDef *) RCC_BASE)
S#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
S#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
S#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
S#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
S#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
S#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
S#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
S#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
S#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
S#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
S#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
S#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
S#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
S#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
S#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
S#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
S#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
S#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
S#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
S#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
S#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
S#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
S#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
S#define HASH                ((HASH_TypeDef *) HASH_BASE)
S#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
S#define RNG                 ((RNG_TypeDef *) RNG_BASE)
S
S#if defined(STM32F40_41xxx)
S#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
S#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
S#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
S#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
S#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
S#endif /* STM32F40_41xxx */
S
S#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
S#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
S#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
S#define FMC_Bank2           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
S#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
S#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
S#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
S#endif /* STM32F427_437xx ||  STM32F429_439xx || STM32F446xx */
S
S#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
S
S/**
S  * @}
S  */
S
S/** @addtogroup Exported_constants
S  * @{
S  */
S  
S  /** @addtogroup Peripheral_Registers_Bits_Definition
S  * @{
S  */
S    
S/******************************************************************************/
S/*                         Peripheral Registers_Bits_Definition               */
S/******************************************************************************/
S
S/******************************************************************************/
S/*                                                                            */
S/*                        Analog to Digital Converter                         */
S/*                                                                            */
S/******************************************************************************/
S/********************  Bit definition for ADC_SR register  ********************/
S#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!<Analog watchdog flag               */
S#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!<End of conversion                  */
S#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!<Injected channel end of conversion */
S#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!<Injected channel Start flag        */
S#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!<Regular channel Start flag         */
S#define  ADC_SR_OVR                          ((uint8_t)0x20)               /*!<Overrun flag                       */
S
S/*******************  Bit definition for ADC_CR1 register  ********************/
S#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
S#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC                              */
S#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable                     */
S#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels                */
S#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode                                             */
S#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode  */
S#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion                   */
S#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels                */
S#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels               */
S#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count)  */
S#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
S#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
S#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels           */
S#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels            */
S#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution)                            */
S#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable                              */
S  
S/*******************  Bit definition for ADC_CR2 register  ********************/
S#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF             */
S#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion              */
S#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode          */
S#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */
S#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection        */
S#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment                     */
S#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
S#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
S#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
S#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
S#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
S#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
S#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
S
S/******************  Bit definition for ADC_SMPR1 register  *******************/
S#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
S#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
S#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
S#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
S#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
S#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
S#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
S#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
S#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
S#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
S#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
S#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
S#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
S#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
S#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
S#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
S#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
S#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
S#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
S#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
S#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
S#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
S#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
S#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
S#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
S#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
S#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
S#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
S#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
S#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
S#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
S
S/******************  Bit definition for ADC_SMPR2 register  *******************/
S#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
S#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
S#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
S#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
S#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
S#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
S#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
S#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
S#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
S#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
S#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
S#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
S#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
S#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
S#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
S#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
S#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
S#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
S#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
S#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
S#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
S#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
S#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
S#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
S#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
S#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
S#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
S#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
S#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
S#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
S#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
S#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
S#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
S#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
S
S/******************  Bit definition for ADC_JOFR1 register  *******************/
S#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 1 */
S
S/******************  Bit definition for ADC_JOFR2 register  *******************/
S#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 2 */
S
S/******************  Bit definition for ADC_JOFR3 register  *******************/
S#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 3 */
S
S/******************  Bit definition for ADC_JOFR4 register  *******************/
S#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 4 */
S
S/*******************  Bit definition for ADC_HTR register  ********************/
S#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog high threshold */
S
S/*******************  Bit definition for ADC_LTR register  ********************/
S#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog low threshold */
S
S/*******************  Bit definition for ADC_SQR1 register  *******************/
S#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
S#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
S#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
S#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
S#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
S#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
S#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
S#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
S#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
S#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
S#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
S#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
S#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
S#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
S#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
S#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
S#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
S#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
S#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
S#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
S#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S/*******************  Bit definition for ADC_SQR2 register  *******************/
S#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
S#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
S#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
S#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
S#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
S#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
S#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
S#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
S#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
S#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
S#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
S#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
S#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
S#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
S#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
S#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
S#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
S#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
S#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
S#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
S#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
S#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
S#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
S#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
S#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
S#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
S#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
S#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
S
S/*******************  Bit definition for ADC_SQR3 register  *******************/
S#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
S#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
S#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
S#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
S#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
S#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
S#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
S#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
S#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
S#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
S#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
S#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
S#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
S#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
S#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
S#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
S#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
S#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
S#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
S#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
S#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
S#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
S#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
S#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
S#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
S#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
S#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
S#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
S
S/*******************  Bit definition for ADC_JSQR register  *******************/
S#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
S#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
S#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
S#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
S#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
S#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
S#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
S#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
S#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
S#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
S#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
S#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
S#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
S#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
S#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
S#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
S#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
S#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
S#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
S#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
S#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
S
S/*******************  Bit definition for ADC_JDR1 register  *******************/
S#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
S
S/*******************  Bit definition for ADC_JDR2 register  *******************/
S#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
S
S/*******************  Bit definition for ADC_JDR3 register  *******************/
S#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
S
S/*******************  Bit definition for ADC_JDR4 register  *******************/
S#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
S
S/********************  Bit definition for ADC_DR register  ********************/
S#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
S#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
S
S/*******************  Bit definition for ADC_CSR register  ********************/
S#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */
S#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */
S#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
S#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */
S#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */
S#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */
S#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */
S#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */
S#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
S#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */
S#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */
S#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */
S#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */
S#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */
S#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
S#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */
S#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */
S#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */
S
S/*******************  Bit definition for ADC_CCR register  ********************/
S#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
S#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
S#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
S#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
S#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
S#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
S#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
S#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
S#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
S
S/*******************  Bit definition for ADC_CDR register  ********************/
S#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
S#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
S
S/******************************************************************************/
S/*                                                                            */
S/*                         Controller Area Network                            */
S/*                                                                            */
S/******************************************************************************/
S/*!<CAN control and status registers */
S/*******************  Bit definition for CAN_MCR register  ********************/
S#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
S#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
S#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
S#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
S#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
S#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
S#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
S#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
S#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
S
S/*******************  Bit definition for CAN_MSR register  ********************/
S#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
S#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
S#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
S#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
S#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
S#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
S#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
S#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
S#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
S
S/*******************  Bit definition for CAN_TSR register  ********************/
S#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
S#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
S#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
S#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
S#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
S#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
S#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
S#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
S#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
S#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
S#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
S#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
S#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
S#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
S#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
S#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
S
S#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
S#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
S#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
S#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
S
S#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
S#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
S#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
S#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
S
S/*******************  Bit definition for CAN_RF0R register  *******************/
S#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
S#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
S#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
S#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
S
S/*******************  Bit definition for CAN_RF1R register  *******************/
S#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
S#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
S#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
S#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
S
S/********************  Bit definition for CAN_IER register  *******************/
S#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
S#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
S#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
S#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
S#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
S#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
S#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
S#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
S#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
S#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
S#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
S#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
S#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
S#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
S
S/********************  Bit definition for CAN_ESR register  *******************/
S#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
S#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
S#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
S
S#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
S#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
S
S#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
S#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
S
S/*******************  Bit definition for CAN_BTR register  ********************/
S#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
S#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
S#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
S#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
S#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
S#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
S
S/*!<Mailbox registers */
S/******************  Bit definition for CAN_TI0R register  ********************/
S#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
S#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
S#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
S#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
S#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
S
S/******************  Bit definition for CAN_TDT0R register  *******************/
S#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
S#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
S#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
S
S/******************  Bit definition for CAN_TDL0R register  *******************/
S#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
S#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
S#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
S#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
S
S/******************  Bit definition for CAN_TDH0R register  *******************/
S#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
S#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
S#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
S#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
S
S/*******************  Bit definition for CAN_TI1R register  *******************/
S#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
S#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
S#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
S#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
S#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
S
S/*******************  Bit definition for CAN_TDT1R register  ******************/
S#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
S#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
S#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
S
S/*******************  Bit definition for CAN_TDL1R register  ******************/
S#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
S#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
S#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
S#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
S
S/*******************  Bit definition for CAN_TDH1R register  ******************/
S#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
S#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
S#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
S#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
S
S/*******************  Bit definition for CAN_TI2R register  *******************/
S#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
S#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
S#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
S#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
S#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
S
S/*******************  Bit definition for CAN_TDT2R register  ******************/  
S#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
S#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
S#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
S
S/*******************  Bit definition for CAN_TDL2R register  ******************/
S#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
S#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
S#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
S#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
S
S/*******************  Bit definition for CAN_TDH2R register  ******************/
S#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
S#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
S#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
S#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
S
S/*******************  Bit definition for CAN_RI0R register  *******************/
S#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
S#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
S#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
S#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
S
S/*******************  Bit definition for CAN_RDT0R register  ******************/
S#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
S#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
S#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
S
S/*******************  Bit definition for CAN_RDL0R register  ******************/
S#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
S#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
S#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
S#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
S
S/*******************  Bit definition for CAN_RDH0R register  ******************/
S#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
S#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
S#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
S#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
S
S/*******************  Bit definition for CAN_RI1R register  *******************/
S#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
S#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
S#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
S#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
S
S/*******************  Bit definition for CAN_RDT1R register  ******************/
S#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
S#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
S#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
S
S/*******************  Bit definition for CAN_RDL1R register  ******************/
S#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
S#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
S#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
S#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
S
S/*******************  Bit definition for CAN_RDH1R register  ******************/
S#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
S#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
S#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
S#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
S
S/*!<CAN filter registers */
S/*******************  Bit definition for CAN_FMR register  ********************/
S#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
S
S/*******************  Bit definition for CAN_FM1R register  *******************/
S#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
S#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
S#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
S#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
S#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
S#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
S#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
S#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
S#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
S#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
S#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
S#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
S#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
S#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
S#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
S
S/*******************  Bit definition for CAN_FS1R register  *******************/
S#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
S#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
S#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
S#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
S#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
S#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
S#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
S#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
S#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
S#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
S#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
S#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
S#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
S#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
S#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
S
S/******************  Bit definition for CAN_FFA1R register  *******************/
S#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
S#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
S#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
S#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
S#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
S#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
S#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
S#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
S#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
S#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
S#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
S#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
S#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
S#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
S#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
S
S/*******************  Bit definition for CAN_FA1R register  *******************/
S#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
S#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
S#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
S#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
S#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
S#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
S#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
S#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
S#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
S#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
S#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
S#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
S#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
S#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
S#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
S
S/*******************  Bit definition for CAN_F0R1 register  *******************/
S#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F1R1 register  *******************/
S#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F2R1 register  *******************/
S#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F3R1 register  *******************/
S#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F4R1 register  *******************/
S#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F5R1 register  *******************/
S#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F6R1 register  *******************/
S#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F7R1 register  *******************/
S#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F8R1 register  *******************/
S#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F9R1 register  *******************/
S#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F10R1 register  ******************/
S#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F11R1 register  ******************/
S#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F12R1 register  ******************/
S#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F13R1 register  ******************/
S#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F0R2 register  *******************/
S#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F1R2 register  *******************/
S#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F2R2 register  *******************/
S#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F3R2 register  *******************/
S#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F4R2 register  *******************/
S#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F5R2 register  *******************/
S#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F6R2 register  *******************/
S#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F7R2 register  *******************/
S#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F8R2 register  *******************/
S#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F9R2 register  *******************/
S#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F10R2 register  ******************/
S#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F11R2 register  ******************/
S#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F12R2 register  ******************/
S#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S/*******************  Bit definition for CAN_F13R2 register  ******************/
S#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
S#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
S#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
S#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
S#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
S#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
S#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
S#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
S#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
S#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
S#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
S#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
S#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
S#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
S#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
S#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
S#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
S#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
S#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
S#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
S#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
S#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
S#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
S#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
S#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
S#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
S#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
S#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
S#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
S#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
S#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
S#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
S
S#if defined(STM32F446xx)
S/******************************************************************************/
S/*                                                                            */
S/*                          HDMI-CEC (CEC)                                    */
S/*                                                                            */
S/******************************************************************************/
S
S/*******************  Bit definition for CEC_CR register  *********************/
S#define  CEC_CR_CECEN                        ((uint32_t)0x00000001)       /*!< CEC Enable                              */
S#define  CEC_CR_TXSOM                        ((uint32_t)0x00000002)       /*!< CEC Tx Start Of Message                 */
S#define  CEC_CR_TXEOM                        ((uint32_t)0x00000004)       /*!< CEC Tx End Of Message                   */
S
S/*******************  Bit definition for CEC_CFGR register  *******************/
S#define  CEC_CFGR_SFT                        ((uint32_t)0x00000007)       /*!< CEC Signal Free Time                    */
S#define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008)       /*!< CEC Tolerance                           */
S#define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010)       /*!< CEC Rx Stop                             */
S#define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020)       /*!< CEC Bit Rising Error generation         */
S#define  CEC_CFGR_LREGEN                     ((uint32_t)0x00000040)       /*!< CEC Long Period Error generation        */
S#define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100)       /*!< CEC Signal Free Time optional           */
S#define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080)       /*!< CEC Broadcast No error generation       */
S#define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000)       /*!< CEC Own Address                         */
S#define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000)       /*!< CEC Listen mode                         */
S
S/*******************  Bit definition for CEC_TXDR register  *******************/
S#define  CEC_TXDR_TXD                        ((uint32_t)0x000000FF)       /*!< CEC Tx Data                              */
S
S/*******************  Bit definition for CEC_RXDR register  *******************/
S#define  CEC_TXDR_RXD                        ((uint32_t)0x000000FF)       /*!< CEC Rx Data                              */
S
S/*******************  Bit definition for CEC_ISR register  ********************/
S#define  CEC_ISR_RXBR                        ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received                      */
S#define  CEC_ISR_RXEND                       ((uint32_t)0x00000002)       /*!< CEC End Of Reception                      */
S#define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun                            */
S#define  CEC_ISR_BRE                         ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error                   */
S#define  CEC_ISR_SBPE                        ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error             */
S#define  CEC_ISR_LBPE                        ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error              */
S#define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge                */
S#define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost                      */
S#define  CEC_ISR_TXBR                        ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request                       */
S#define  CEC_ISR_TXEND                       ((uint32_t)0x00000200)       /*!< CEC End of Transmission                   */
S#define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun                    */
S#define  CEC_ISR_TXERR                       ((uint32_t)0x00000800)       /*!< CEC Tx-Error                              */
S#define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge                */
S
S/*******************  Bit definition for CEC_IER register  ********************/
S#define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received IT Enable            */
S#define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002)       /*!< CEC End Of Reception IT Enable            */
S#define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun IT Enable                  */
S#define  CEC_IER_BREIEIE                     ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error IT Enable         */
S#define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error IT Enable   */
S#define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error IT Enable    */
S#define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge IT Enable      */
S#define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost IT Enable            */
S#define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request  IT Enable            */
S#define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200)       /*!< CEC End of Transmission IT Enable         */
S#define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun IT Enable          */
S#define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800)       /*!< CEC Tx-Error IT Enable                    */
S#define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge IT Enable      */
S#endif /* STM32F446xx */
S
S/******************************************************************************/
S/*                                                                            */
S/*                          CRC calculation unit                              */
S/*                                                                            */
S/******************************************************************************/
S/*******************  Bit definition for CRC_DR register  *********************/
S#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
S
S
S/*******************  Bit definition for CRC_IDR register  ********************/
S#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
S
S
S/********************  Bit definition for CRC_CR register  ********************/
S#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
S
S/******************************************************************************/
S/*                                                                            */
S/*                            Crypto Processor                                */
S/*                                                                            */
S/******************************************************************************/
S/******************* Bits definition for CRYP_CR register  ********************/
S#define CRYP_CR_ALGODIR                      ((uint32_t)0x00000004)
S
S#define CRYP_CR_ALGOMODE                     ((uint32_t)0x00080038)
S#define CRYP_CR_ALGOMODE_0                   ((uint32_t)0x00000008)
S#define CRYP_CR_ALGOMODE_1                   ((uint32_t)0x00000010)
S#define CRYP_CR_ALGOMODE_2                   ((uint32_t)0x00000020)
S#define CRYP_CR_ALGOMODE_TDES_ECB            ((uint32_t)0x00000000)
S#define CRYP_CR_ALGOMODE_TDES_CBC            ((uint32_t)0x00000008)
S#define CRYP_CR_ALGOMODE_DES_ECB             ((uint32_t)0x00000010)
S#define CRYP_CR_ALGOMODE_DES_CBC             ((uint32_t)0x00000018)
S#define CRYP_CR_ALGOMODE_AES_ECB             ((uint32_t)0x00000020)
S#define CRYP_CR_ALGOMODE_AES_CBC             ((uint32_t)0x00000028)
S#define CRYP_CR_ALGOMODE_AES_CTR             ((uint32_t)0x00000030)
S#define CRYP_CR_ALGOMODE_AES_KEY             ((uint32_t)0x00000038)
S
S#define CRYP_CR_DATATYPE                     ((uint32_t)0x000000C0)
S#define CRYP_CR_DATATYPE_0                   ((uint32_t)0x00000040)
S#define CRYP_CR_DATATYPE_1                   ((uint32_t)0x00000080)
S#define CRYP_CR_KEYSIZE                      ((uint32_t)0x00000300)
S#define CRYP_CR_KEYSIZE_0                    ((uint32_t)0x00000100)
S#define CRYP_CR_KEYSIZE_1                    ((uint32_t)0x00000200)
S#define CRYP_CR_FFLUSH                       ((uint32_t)0x00004000)
S#define CRYP_CR_CRYPEN                       ((uint32_t)0x00008000)
S
S#define CRYP_CR_GCM_CCMPH                    ((uint32_t)0x00030000)
S#define CRYP_CR_GCM_CCMPH_0                  ((uint32_t)0x00010000)
S#define CRYP_CR_GCM_CCMPH_1                  ((uint32_t)0x00020000)
S#define CRYP_CR_ALGOMODE_3                   ((uint32_t)0x00080000) 
S
S/****************** Bits definition for CRYP_SR register  *********************/
S#define CRYP_SR_IFEM                         ((uint32_t)0x00000001)
S#define CRYP_SR_IFNF                         ((uint32_t)0x00000002)
S#define CRYP_SR_OFNE                         ((uint32_t)0x00000004)
S#define CRYP_SR_OFFU                         ((uint32_t)0x00000008)
S#define CRYP_SR_BUSY                         ((uint32_t)0x00000010)
S/****************** Bits definition for CRYP_DMACR register  ******************/
S#define CRYP_DMACR_DIEN                      ((uint32_t)0x00000001)
S#define CRYP_DMACR_DOEN                      ((uint32_t)0x00000002)
S/*****************  Bits definition for CRYP_IMSCR register  ******************/
S#define CRYP_IMSCR_INIM                      ((uint32_t)0x00000001)
S#define CRYP_IMSCR_OUTIM                     ((uint32_t)0x00000002)
S/****************** Bits definition for CRYP_RISR register  *******************/
S#define CRYP_RISR_OUTRIS                     ((uint32_t)0x00000001)
S#define CRYP_RISR_INRIS                      ((uint32_t)0x00000002)
S/****************** Bits definition for CRYP_MISR register  *******************/
S#define CRYP_MISR_INMIS                      ((uint32_t)0x00000001)
S#define CRYP_MISR_OUTMIS                     ((uint32_t)0x00000002)
S
S/******************************************************************************/
S/*                                                                            */
S/*                      Digital to Analog Converter                           */
S/*                                                                            */
S/******************************************************************************/
S/********************  Bit definition for DAC_CR register  ********************/
S#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
S#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
S#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
S
S#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
S#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
S#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
S#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
S
S#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
S#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
S#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
S
S#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
S#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
S#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
S#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
S#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
S
S#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
S#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
S#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
S#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
S
S#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
S#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
S#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
S
S#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
S#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
S
S/*****************  Bit definition for DAC_SWTRIGR register  ******************/
S#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
S#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
S
S/*****************  Bit definition for DAC_DHR12R1 register  ******************/
S#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
S
S/*****************  Bit definition for DAC_DHR12L1 register  ******************/
S#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
S
S/******************  Bit definition for DAC_DHR8R1 register  ******************/
S#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
S
S/*****************  Bit definition for DAC_DHR12R2 register  ******************/
S#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
S
S/*****************  Bit definition for DAC_DHR12L2 register  ******************/
S#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
S
S/******************  Bit definition for DAC_DHR8R2 register  ******************/
S#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
S
S/*****************  Bit definition for DAC_DHR12RD register  ******************/
S#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
S#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
S
S/*****************  Bit definition for DAC_DHR12LD register  ******************/
S#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
S#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
S
S/******************  Bit definition for DAC_DHR8RD register  ******************/
S#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
S#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
S
S/*******************  Bit definition for DAC_DOR1 register  *******************/
S#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
S
S/*******************  Bit definition for DAC_DOR2 register  *******************/
S#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
S
S/********************  Bit definition for DAC_SR register  ********************/
S#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
S#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
S
S/******************************************************************************/
S/*                                                                            */
S/*                                 Debug MCU                                  */
S/*                                                                            */
S/******************************************************************************/
S
S/******************************************************************************/
S/*                                                                            */
S/*                                    DCMI                                    */
S/*                                                                            */
S/******************************************************************************/
S/********************  Bits definition for DCMI_CR register  ******************/
S#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001)
S#define DCMI_CR_CM                           ((uint32_t)0x00000002)
S#define DCMI_CR_CROP                         ((uint32_t)0x00000004)
S#define DCMI_CR_JPEG                         ((uint32_t)0x00000008)
S#define DCMI_CR_ESS                          ((uint32_t)0x00000010)
S#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020)
S#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040)
S#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080)
S#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100)
S#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200)
S#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400)
S#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800)
S#define DCMI_CR_CRE                          ((uint32_t)0x00001000)
S#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000)
S
S/********************  Bits definition for DCMI_SR register  ******************/
S#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001)
S#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002)
S#define DCMI_SR_FNE                          ((uint32_t)0x00000004)
S
S/********************  Bits definition for DCMI_RISR register  ****************/
S#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001)
S#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002)
S#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004)
S#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008)
S#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010)
S
S/********************  Bits definition for DCMI_IER register  *****************/
S#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001)
S#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002)
S#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004)
S#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008)
S#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010)
S
S/********************  Bits definition for DCMI_MISR register  ****************/
S#define DCMI_MISR_FRAME_MIS                  ((uint32_t)0x00000001)
S#define DCMI_MISR_OVF_MIS                    ((uint32_t)0x00000002)
S#define DCMI_MISR_ERR_MIS                    ((uint32_t)0x00000004)
S#define DCMI_MISR_VSYNC_MIS                  ((uint32_t)0x00000008)
S#define DCMI_MISR_LINE_MIS                   ((uint32_t)0x00000010)
S
S/********************  Bits definition for DCMI_ICR register  *****************/
S#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001)
S#define DCMI_ICR_OVF_ISC                     ((uint32_t)0x00000002)
S#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004)
S#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008)
S#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010)
S
S/******************************************************************************/
S/*                                                                            */
S/*                             DMA Controller                                 */
S/*                                                                            */
S/******************************************************************************/
S/********************  Bits definition for DMA_SxCR register  *****************/ 
S#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
S#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
S#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
S#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
S#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
S#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
S#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
S#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
S#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
S#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
S#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
S#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  
S#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
S#define DMA_SxCR_PL                          ((uint32_t)0x00030000)
S#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
S#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
S#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
S#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
S#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
S#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
S#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
S#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
S#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
S#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
S#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
S#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
S#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
S#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
S#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
S#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
S#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
S#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
S#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
S#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
S#define DMA_SxCR_EN                          ((uint32_t)0x00000001)
S
S/********************  Bits definition for DMA_SxCNDTR register  **************/
S#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
S#define DMA_SxNDT_0                          ((uint32_t)0x00000001)
S#define DMA_SxNDT_1                          ((uint32_t)0x00000002)
S#define DMA_SxNDT_2                          ((uint32_t)0x00000004)
S#define DMA_SxNDT_3                          ((uint32_t)0x00000008)
S#define DMA_SxNDT_4                          ((uint32_t)0x00000010)
S#define DMA_SxNDT_5                          ((uint32_t)0x00000020)
S#define DMA_SxNDT_6                          ((uint32_t)0x00000040)
S#define DMA_SxNDT_7                          ((uint32_t)0x00000080)
S#define DMA_SxNDT_8                          ((uint32_t)0x00000100)
S#define DMA_SxNDT_9                          ((uint32_t)0x00000200)
S#define DMA_SxNDT_10                         ((uint32_t)0x00000400)
S#define DMA_SxNDT_11                         ((uint32_t)0x00000800)
S#define DMA_SxNDT_12                         ((uint32_t)0x00001000)
S#define DMA_SxNDT_13                         ((uint32_t)0x00002000)
S#define DMA_SxNDT_14                         ((uint32_t)0x00004000)
S#define DMA_SxNDT_15                         ((uint32_t)0x00008000)
S
S/********************  Bits definition for DMA_SxFCR register  ****************/ 
S#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
S#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
S#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
S#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
S#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
S#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
S#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
S#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
S#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
S
S/********************  Bits definition for DMA_LISR register  *****************/ 
S#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
S#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
S#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
S#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
S#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
S#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
S#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
S#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
S#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
S#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
S#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
S#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
S#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
S#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
S#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
S#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
S#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
S#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
S#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
S#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
S
S/********************  Bits definition for DMA_HISR register  *****************/ 
S#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
S#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
S#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
S#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
S#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
S#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
S#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
S#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
S#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
S#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
S#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
S#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
S#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
S#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
S#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
S#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
S#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
S#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
S#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
S#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
S
S/********************  Bits definition for DMA_LIFCR register  ****************/ 
S#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
S#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
S#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
S#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
S#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
S#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
S#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
S#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
S#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
S#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
S#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
S#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
S#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
S#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
S#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
S#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
S#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
S#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
S#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
S#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
S
S/********************  Bits definition for DMA_HIFCR  register  ****************/ 
S#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
S#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
S#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
S#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
S#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
S#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
S#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
S#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
S#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
S#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
S#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
S#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
S#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
S#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
S#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
S#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
S#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
S#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
S#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
S#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
S
S/******************************************************************************/
S/*                                                                            */
S/*                         AHB Master DMA2D Controller (DMA2D)                */
S/*                                                                            */
S/******************************************************************************/
S
S/********************  Bit definition for DMA2D_CR register  ******************/
S
S#define DMA2D_CR_START                     ((uint32_t)0x00000001)               /*!< Start transfer */
S#define DMA2D_CR_SUSP                      ((uint32_t)0x00000002)               /*!< Suspend transfer */
S#define DMA2D_CR_ABORT                     ((uint32_t)0x00000004)               /*!< Abort transfer */
S#define DMA2D_CR_TEIE                      ((uint32_t)0x00000100)               /*!< Transfer Error Interrupt Enable */
S#define DMA2D_CR_TCIE                      ((uint32_t)0x00000200)               /*!< Transfer Complete Interrupt Enable */
S#define DMA2D_CR_TWIE                      ((uint32_t)0x00000400)               /*!< Transfer Watermark Interrupt Enable */
S#define DMA2D_CR_CAEIE                     ((uint32_t)0x00000800)               /*!< CLUT Access Error Interrupt Enable */
S#define DMA2D_CR_CTCIE                     ((uint32_t)0x00001000)               /*!< CLUT Transfer Complete Interrupt Enable */
S#define DMA2D_CR_CEIE                      ((uint32_t)0x00002000)               /*!< Configuration Error Interrupt Enable */
S#define DMA2D_CR_MODE                      ((uint32_t)0x00030000)               /*!< DMA2D Mode */
S
S/********************  Bit definition for DMA2D_ISR register  *****************/
S
S#define DMA2D_ISR_TEIF                     ((uint32_t)0x00000001)               /*!< Transfer Error Interrupt Flag */
S#define DMA2D_ISR_TCIF                     ((uint32_t)0x00000002)               /*!< Transfer Complete Interrupt Flag */
S#define DMA2D_ISR_TWIF                     ((uint32_t)0x00000004)               /*!< Transfer Watermark Interrupt Flag */
S#define DMA2D_ISR_CAEIF                    ((uint32_t)0x00000008)               /*!< CLUT Access Error Interrupt Flag */
S#define DMA2D_ISR_CTCIF                    ((uint32_t)0x00000010)               /*!< CLUT Transfer Complete Interrupt Flag */
S#define DMA2D_ISR_CEIF                     ((uint32_t)0x00000020)               /*!< Configuration Error Interrupt Flag */
S
S/********************  Bit definition for DMA2D_IFSR register  ****************/
S
S#define DMA2D_IFSR_CTEIF                   ((uint32_t)0x00000001)               /*!< Clears Transfer Error Interrupt Flag */
S#define DMA2D_IFSR_CTCIF                   ((uint32_t)0x00000002)               /*!< Clears Transfer Complete Interrupt Flag */
S#define DMA2D_IFSR_CTWIF                   ((uint32_t)0x00000004)               /*!< Clears Transfer Watermark Interrupt Flag */
S#define DMA2D_IFSR_CCAEIF                  ((uint32_t)0x00000008)               /*!< Clears CLUT Access Error Interrupt Flag */
S#define DMA2D_IFSR_CCTCIF                  ((uint32_t)0x00000010)               /*!< Clears CLUT Transfer Complete Interrupt Flag */
S#define DMA2D_IFSR_CCEIF                   ((uint32_t)0x00000020)               /*!< Clears Configuration Error Interrupt Flag */
S
S/********************  Bit definition for DMA2D_FGMAR register  ***************/
S
S#define DMA2D_FGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
S
S/********************  Bit definition for DMA2D_FGOR register  ****************/
S
S#define DMA2D_FGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
S
S/********************  Bit definition for DMA2D_BGMAR register  ***************/
S
S#define DMA2D_BGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
S
S/********************  Bit definition for DMA2D_BGOR register  ****************/
S
S#define DMA2D_BGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */
S
S/********************  Bit definition for DMA2D_FGPFCCR register  *************/
S
S#define DMA2D_FGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */
S#define DMA2D_FGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
S#define DMA2D_FGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */
S#define DMA2D_FGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */
S#define DMA2D_FGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha mode */
S#define DMA2D_FGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */
S
S/********************  Bit definition for DMA2D_FGCOLR register  **************/
S
S#define DMA2D_FGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */
S#define DMA2D_FGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
S#define DMA2D_FGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */   
S
S/********************  Bit definition for DMA2D_BGPFCCR register  *************/
S
S#define DMA2D_BGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */
S#define DMA2D_BGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */
S#define DMA2D_BGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */
S#define DMA2D_BGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */
S#define DMA2D_BGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha Mode */
S#define DMA2D_BGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */
S
S/********************  Bit definition for DMA2D_BGCOLR register  **************/
S
S#define DMA2D_BGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */
S#define DMA2D_BGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */
S#define DMA2D_BGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */
S
S/********************  Bit definition for DMA2D_FGCMAR register  **************/
S
S#define DMA2D_FGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
S
S/********************  Bit definition for DMA2D_BGCMAR register  **************/
S
S#define DMA2D_BGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
S
S/********************  Bit definition for DMA2D_OPFCCR register  **************/
S
S#define DMA2D_OPFCCR_CM                    ((uint32_t)0x00000007)               /*!< Color mode */
S
S/********************  Bit definition for DMA2D_OCOLR register  ***************/
S
S/*!<Mode_ARGB8888/RGB888 */
S
S#define DMA2D_OCOLR_BLUE_1                 ((uint32_t)0x000000FF)               /*!< BLUE Value */
S#define DMA2D_OCOLR_GREEN_1                ((uint32_t)0x0000FF00)               /*!< GREEN Value  */
S#define DMA2D_OCOLR_RED_1                  ((uint32_t)0x00FF0000)               /*!< Red Value */
S#define DMA2D_OCOLR_ALPHA_1                ((uint32_t)0xFF000000)               /*!< Alpha Channel Value */
S
S/*!<Mode_RGB565 */
S#define DMA2D_OCOLR_BLUE_2                 ((uint32_t)0x0000001F)               /*!< BLUE Value */
S#define DMA2D_OCOLR_GREEN_2                ((uint32_t)0x000007E0)               /*!< GREEN Value  */
S#define DMA2D_OCOLR_RED_2                  ((uint32_t)0x0000F800)               /*!< Red Value */
S
S/*!<Mode_ARGB1555 */
S#define DMA2D_OCOLR_BLUE_3                 ((uint32_t)0x0000001F)               /*!< BLUE Value */
S#define DMA2D_OCOLR_GREEN_3                ((uint32_t)0x000003E0)               /*!< GREEN Value  */
S#define DMA2D_OCOLR_RED_3                  ((uint32_t)0x00007C00)               /*!< Red Value */
S#define DMA2D_OCOLR_ALPHA_3                ((uint32_t)0x00008000)               /*!< Alpha Channel Value */
S
S/*!<Mode_ARGB4444 */
S#define DMA2D_OCOLR_BLUE_4                 ((uint32_t)0x0000000F)               /*!< BLUE Value */
S#define DMA2D_OCOLR_GREEN_4                ((uint32_t)0x000000F0)               /*!< GREEN Value  */
S#define DMA2D_OCOLR_RED_4                  ((uint32_t)0x00000F00)               /*!< Red Value */
S#define DMA2D_OCOLR_ALPHA_4                ((uint32_t)0x0000F000)               /*!< Alpha Channel Value */
S
S/********************  Bit definition for DMA2D_OMAR register  ****************/
S
S#define DMA2D_OMAR_MA                      ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */
S
S/********************  Bit definition for DMA2D_OOR register  *****************/
S
S#define DMA2D_OOR_LO                       ((uint32_t)0x00003FFF)               /*!< Line Offset */
S
S/********************  Bit definition for DMA2D_NLR register  *****************/
S
S#define DMA2D_NLR_NL                       ((uint32_t)0x0000FFFF)               /*!< Number of Lines */
S#define DMA2D_NLR_PL                       ((uint32_t)0x3FFF0000)               /*!< Pixel per Lines */
S
S/********************  Bit definition for DMA2D_LWR register  *****************/
S
S#define DMA2D_LWR_LW                       ((uint32_t)0x0000FFFF)               /*!< Line Watermark */
S
S/********************  Bit definition for DMA2D_AMTCR register  ***************/
S
S#define DMA2D_AMTCR_EN                     ((uint32_t)0x00000001)               /*!< Enable */
S#define DMA2D_AMTCR_DT                     ((uint32_t)0x0000FF00)               /*!< Dead Time */
S
S
S
S/********************  Bit definition for DMA2D_FGCLUT register  **************/
S                                                                     
S/********************  Bit definition for DMA2D_BGCLUT register  **************/
S
S
S/******************************************************************************/
S/*                                                                            */
S/*                    External Interrupt/Event Controller                     */
S/*                                                                            */
S/******************************************************************************/
S/*******************  Bit definition for EXTI_IMR register  *******************/
S#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
S#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
S#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
S#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
S#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
S#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
S#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
S#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
S#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
S#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
S#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
S#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
S#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
S#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
S#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
S#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
S#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
S#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
S#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
S#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
S
S/*******************  Bit definition for EXTI_EMR register  *******************/
S#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
S#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
S#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
S#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
S#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
S#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
S#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
S#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
S#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
S#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
S#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
S#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
S#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
S#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
S#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
S#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
S#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
S#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
S#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
S#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
S
S/******************  Bit definition for EXTI_RTSR register  *******************/
S#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
S#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
S#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
S#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
S#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
S#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
S#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
S#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
S#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
S#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
S#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
S#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
S#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
S#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
S#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
S#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
S#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
S#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
S#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
S#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
S
S/******************  Bit definition for EXTI_FTSR register  *******************/
S#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
S#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
S#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
S#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
S#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
S#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
S#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
S#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
S#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
S#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
S#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
S#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
S#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
S#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
S#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
S#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
S#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
S#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
S#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
S#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
S
S/******************  Bit definition for EXTI_SWIER register  ******************/
S#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
S#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
S#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
S#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
S#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
S#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
S#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
S#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
S#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
S#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
S#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
S#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
S#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
S#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
S#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
S#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
S#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
S#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
S#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
S#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
S
S/*******************  Bit definition for EXTI_PR register  ********************/
S#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
S#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
S#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
S#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
S#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
S#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
S#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
S#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
S#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
S#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
S#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
S#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
S#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
S#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
S#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
S#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
S#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
S#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
S#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
S#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
S
S/******************************************************************************/
S/*                                                                            */
S/*                                    FLASH                                   */
S/*                                                                            */
S/******************************************************************************/
S/*******************  Bits definition for FLASH_ACR register  *****************/
S#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000F)
S#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
S#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
S#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
S#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
S#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
S#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
S#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
S#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
S#define FLASH_ACR_LATENCY_8WS                ((uint32_t)0x00000008)
S#define FLASH_ACR_LATENCY_9WS                ((uint32_t)0x00000009)
S#define FLASH_ACR_LATENCY_10WS               ((uint32_t)0x0000000A)
S#define FLASH_ACR_LATENCY_11WS               ((uint32_t)0x0000000B)
S#define FLASH_ACR_LATENCY_12WS               ((uint32_t)0x0000000C)
S#define FLASH_ACR_LATENCY_13WS               ((uint32_t)0x0000000D)
S#define FLASH_ACR_LATENCY_14WS               ((uint32_t)0x0000000E)
S#define FLASH_ACR_LATENCY_15WS               ((uint32_t)0x0000000F)
S
S#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
S#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)
S#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)
S#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)
S#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)
S#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)
S#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)
S
S/*******************  Bits definition for FLASH_SR register  ******************/
S#define FLASH_SR_EOP                         ((uint32_t)0x00000001)
S#define FLASH_SR_SOP                         ((uint32_t)0x00000002)
S#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
S#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
S#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
S#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)
S#define FLASH_SR_BSY                         ((uint32_t)0x00010000)
S
S/*******************  Bits definition for FLASH_CR register  ******************/
S#define FLASH_CR_PG                          ((uint32_t)0x00000001)
S#define FLASH_CR_SER                         ((uint32_t)0x00000002)
S#define FLASH_CR_MER                         ((uint32_t)0x00000004)
S#define FLASH_CR_MER1                        FLASH_CR_MER
S#define FLASH_CR_SNB                         ((uint32_t)0x000000F8)
S#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
S#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
S#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
S#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
S#define FLASH_CR_SNB_4                       ((uint32_t)0x00000040)
S#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300)
S#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
S#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
S#define FLASH_CR_MER2                        ((uint32_t)0x00008000)
S#define FLASH_CR_STRT                        ((uint32_t)0x00010000)
S#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
S#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
S
S/*******************  Bits definition for FLASH_OPTCR register  ***************/
S#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001)
S#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002)
S#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004)
S#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008)
S#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000C)
S#define FLASH_OPTCR_BFB2                    ((uint32_t)0x00000010)
S
S#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020)
S#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040)
S#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080)
S#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00)
S#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100)
S#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200)
S#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400)
S#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800)
S#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000)
S#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000)
S#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000)
S#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000)
S#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000)
S#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000)
S#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000)
S#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000)
S#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000)
S#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000)
S#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000)
S#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000)
S#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000)
S#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000)
S#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000)
S#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000)
S#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000)
S
S#define FLASH_OPTCR_DB1M                    ((uint32_t)0x40000000) 
S#define FLASH_OPTCR_SPRMOD                  ((uint32_t)0x80000000) 
S                                             
S/******************  Bits definition for FLASH_OPTCR1 register  ***************/
S#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000)
S#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000)
S#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000)
S#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000)
S#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000)
S#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000)
S#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000)
S#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000)
S#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000)
S#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000)
S#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000)
S#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000)
S#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000)
S
S#if defined(STM32F40_41xxx)
S/******************************************************************************/
S/*                                                                            */
S/*                       Flexible Static Memory Controller                    */
S/*                                                                            */
S/******************************************************************************/
S/******************  Bit definition for FSMC_BCR1 register  *******************/
S#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
S#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
S
S#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
S#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
S#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
S#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
S#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
S#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
S#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
S#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
S#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
S#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
S#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
S#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
S
S/******************  Bit definition for FSMC_BCR2 register  *******************/
S#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                */
S#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
S
S#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
S#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
S#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
S#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
S#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
S#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
S#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
S#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
S#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
S#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
S#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
S#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
S
S/******************  Bit definition for FSMC_BCR3 register  *******************/
S#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
S#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
S
S#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
S#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
S#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
S#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
S#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
S#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
S#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
S#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
S#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
S#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
S#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
S#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
S
S/******************  Bit definition for FSMC_BCR4 register  *******************/
S#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
S#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
S
S#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
S#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
S#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */
S#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */
S#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */
S#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */
S#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */
S#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */
S#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */
S#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */
S#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */
S#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */
S
S/******************  Bit definition for FSMC_BTR1 register  ******************/
S#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
S#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FSMC_BTR2 register  *******************/
S#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
S#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/*******************  Bit definition for FSMC_BTR3 register  *******************/
S#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
S#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FSMC_BTR4 register  *******************/
S#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
S#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FSMC_BWTR1 register  ******************/
S#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  FSMC_BWTR1_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
S#define  FSMC_BWTR1_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_BWTR1_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_BWTR1_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_BWTR1_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FSMC_BWTR2 register  ******************/
S#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  FSMC_BWTR2_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
S#define  FSMC_BWTR2_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_BWTR2_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_BWTR2_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_BWTR2_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
S#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FSMC_BWTR3 register  ******************/
S#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  FSMC_BWTR3_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
S#define  FSMC_BWTR3_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_BWTR3_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_BWTR3_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_BWTR3_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FSMC_BWTR4 register  ******************/
S#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  FSMC_BWTR4_BUSTURN                  ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
S#define  FSMC_BWTR4_BUSTURN_0                ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_BWTR4_BUSTURN_1                ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_BWTR4_BUSTURN_2                ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_BWTR4_BUSTURN_3                ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FSMC_PCR2 register  *******************/
S#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
S#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
S#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
S
S#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
S#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
S
S#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
S#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
S#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
S#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
S#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
S
S#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
S#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
S#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
S#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
S
S#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size) */
S#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
S#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
S#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
S
S/******************  Bit definition for FSMC_PCR3 register  *******************/
S#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
S#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
S#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
S
S#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
S#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
S
S#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
S#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
S#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
S#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
S#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
S
S#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
S#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
S#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
S#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
S
S#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
S#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
S#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
S#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
S
S/******************  Bit definition for FSMC_PCR4 register  *******************/
S#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
S#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
S#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
S
S#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
S#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
S
S#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
S#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
S#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
S#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
S#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
S
S#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
S#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
S#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
S#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
S
S#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
S#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
S#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
S#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
S
S/*******************  Bit definition for FSMC_SR2 register  *******************/
S#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
S#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
S#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
S#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
S#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
S#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
S#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
S
S/*******************  Bit definition for FSMC_SR3 register  *******************/
S#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
S#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
S#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
S#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
S#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
S#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
S#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
S
S/*******************  Bit definition for FSMC_SR4 register  *******************/
S#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                 */
S#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                       */
S#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status                */
S#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit   */
S#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit         */
S#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit  */
S#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
S
S/******************  Bit definition for FSMC_PMEM2 register  ******************/
S#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
S#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
S#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
S#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
S#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FSMC_PMEM3 register  ******************/
S#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
S#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
S#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
S#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
S#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FSMC_PMEM4 register  ******************/
S#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
S#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
S#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
S#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
S#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FSMC_PATT2 register  ******************/
S#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
S#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
S#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
S#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
S#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FSMC_PATT3 register  ******************/
S#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
S#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
S#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
S#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
S#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FSMC_PATT4 register  ******************/
S#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
S#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
S#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
S#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
S#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FSMC_PIO4 register  *******************/
S#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
S#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
S#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
S#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
S#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FSMC_ECCR2 register  ******************/
S#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
S
S/******************  Bit definition for FSMC_ECCR3 register  ******************/
S#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
S#endif /* STM32F40_41xxx */
S
S#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
S/******************************************************************************/
S/*                                                                            */
S/*                          Flexible Memory Controller                        */
S/*                                                                            */
S/******************************************************************************/
S/******************  Bit definition for FMC_BCR1 register  *******************/
S#define  FMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
S#define  FMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
S
S#define  FMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
S#define  FMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
S#define  FMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
S#define  FMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
S#define  FMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
S#define  FMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
S#define  FMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
S#define  FMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
S#define  FMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
S#define  FMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
S#define  FMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
S#define  FMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
S#define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000)        /*!<Continous clock enable     */
S
S/******************  Bit definition for FMC_BCR2 register  *******************/
S#define  FMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
S#define  FMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
S
S#define  FMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
S#define  FMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
S#define  FMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
S#define  FMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
S#define  FMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
S#define  FMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
S#define  FMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
S#define  FMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
S#define  FMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
S#define  FMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
S#define  FMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
S#define  FMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
S
S/******************  Bit definition for FMC_BCR3 register  *******************/
S#define  FMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
S#define  FMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
S
S#define  FMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
S#define  FMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
S#define  FMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
S#define  FMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
S#define  FMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
S#define  FMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
S#define  FMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
S#define  FMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
S#define  FMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
S#define  FMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
S#define  FMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
S#define  FMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
S
S/******************  Bit definition for FMC_BCR4 register  *******************/
S#define  FMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */
S#define  FMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */
S
S#define  FMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */
S#define  FMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
S#define  FMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */
S#define  FMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */
S#define  FMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */
S#define  FMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
S#define  FMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */
S#define  FMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */
S#define  FMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */
S#define  FMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */
S#define  FMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */
S#define  FMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */
S
S/******************  Bit definition for FMC_BTR1 register  ******************/
S#define  FMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
S#define  FMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BTR1_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BTR1_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BTR1_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BTR1_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
S#define  FMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_BTR2 register  *******************/
S#define  FMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BTR2_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BTR2_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BTR2_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BTR2_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
S#define  FMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/*******************  Bit definition for FMC_BTR3 register  *******************/
S#define  FMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BTR3_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BTR3_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BTR3_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BTR3_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
S#define  FMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_BTR4 register  *******************/
S#define  FMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BTR4_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BTR4_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BTR4_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BTR4_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
S#define  FMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S
S#define  FMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_BWTR1 register  ******************/
S#define  FMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_BWTR2 register  ******************/
S#define  FMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
S#define  FMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_BWTR3 register  ******************/
S#define  FMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_BWTR4 register  ******************/
S#define  FMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
S#define  FMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
S
S#define  FMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
S#define  FMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
S#define  FMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
S#define  FMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
S#define  FMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
S
S#define  FMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
S#define  FMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
S
S#define  FMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
S#define  FMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
S#define  FMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_PCR2 register  *******************/
S#define  FMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
S#define  FMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
S#define  FMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
S
S#define  FMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
S#define  FMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
S
S#define  FMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
S#define  FMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
S#define  FMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
S#define  FMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
S#define  FMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
S
S#define  FMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
S#define  FMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
S#define  FMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
S#define  FMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
S
S#define  FMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size)           */
S#define  FMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
S#define  FMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
S#define  FMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
S
S/******************  Bit definition for FMC_PCR3 register  *******************/
S#define  FMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
S#define  FMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
S#define  FMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
S
S#define  FMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
S#define  FMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
S
S#define  FMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
S#define  FMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
S#define  FMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
S#define  FMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
S#define  FMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
S
S#define  FMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
S#define  FMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
S#define  FMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
S#define  FMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
S
S#define  FMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
S#define  FMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
S#define  FMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
S#define  FMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
S
S/******************  Bit definition for FMC_PCR4 register  *******************/
S#define  FMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */
S#define  FMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
S#define  FMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */
S
S#define  FMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
S#define  FMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */
S
S#define  FMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */
S#define  FMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
S#define  FMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
S#define  FMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
S#define  FMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
S
S#define  FMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */
S#define  FMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
S#define  FMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
S#define  FMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
S
S#define  FMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */
S#define  FMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
S#define  FMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
S#define  FMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
S
S/*******************  Bit definition for FMC_SR2 register  *******************/
S#define  FMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
S#define  FMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
S#define  FMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
S#define  FMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
S#define  FMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
S#define  FMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
S#define  FMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
S
S/*******************  Bit definition for FMC_SR3 register  *******************/
S#define  FMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
S#define  FMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
S#define  FMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
S#define  FMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
S#define  FMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
S#define  FMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
S#define  FMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
S
S/*******************  Bit definition for FMC_SR4 register  *******************/
S#define  FMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */
S#define  FMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */
S#define  FMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */
S#define  FMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */
S#define  FMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */
S#define  FMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
S#define  FMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */
S
S/******************  Bit definition for FMC_PMEM2 register  ******************/
S#define  FMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
S#define  FMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
S#define  FMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
S#define  FMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
S#define  FMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_PMEM3 register  ******************/
S#define  FMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
S#define  FMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
S#define  FMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
S#define  FMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
S#define  FMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_PMEM4 register  ******************/
S#define  FMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
S#define  FMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
S#define  FMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
S#define  FMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
S#define  FMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_PATT2 register  ******************/
S#define  FMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
S#define  FMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
S#define  FMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
S#define  FMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
S#define  FMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_PATT3 register  ******************/
S#define  FMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
S#define  FMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
S#define  FMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
S#define  FMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
S#define  FMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_PATT4 register  ******************/
S#define  FMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
S#define  FMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
S#define  FMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
S#define  FMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
S#define  FMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_PIO4 register  *******************/
S#define  FMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
S#define  FMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  FMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  FMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  FMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  FMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  FMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
S#define  FMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  FMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  FMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  FMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
S#define  FMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
S
S#define  FMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
S#define  FMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
S#define  FMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
S#define  FMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
S#define  FMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
S#define  FMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
S#define  FMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
S
S#define  FMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
S#define  FMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
S#define  FMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
S#define  FMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
S#define  FMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
S#define  FMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
S#define  FMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
S
S/******************  Bit definition for FMC_ECCR2 register  ******************/
S#define  FMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
S
S/******************  Bit definition for FMC_ECCR3 register  ******************/
S#define  FMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
S
S/******************  Bit definition for FMC_SDCR1 register  ******************/
S#define  FMC_SDCR1_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
S#define  FMC_SDCR1_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_SDCR1_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
S
S#define  FMC_SDCR1_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
S#define  FMC_SDCR1_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FMC_SDCR1_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FMC_SDCR1_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
S#define  FMC_SDCR1_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_SDCR1_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_SDCR1_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
S
S#define  FMC_SDCR1_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
S#define  FMC_SDCR1_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
S#define  FMC_SDCR1_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
S
S#define  FMC_SDCR1_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
S
S#define  FMC_SDCR1_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDRAM clock configuration */
S#define  FMC_SDCR1_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
S#define  FMC_SDCR1_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
S
S#define  FMC_SDCR1_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
S
S#define  FMC_SDCR1_RPIPE                    ((uint32_t)0x00006000)        /*!<Write protection */
S#define  FMC_SDCR1_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FMC_SDCR1_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_SDCR2 register  ******************/
S#define  FMC_SDCR2_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */
S#define  FMC_SDCR2_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_SDCR2_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
S
S#define  FMC_SDCR2_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */
S#define  FMC_SDCR2_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  FMC_SDCR2_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  FMC_SDCR2_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */
S#define  FMC_SDCR2_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_SDCR2_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S#define  FMC_SDCR2_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */
S
S#define  FMC_SDCR2_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */
S#define  FMC_SDCR2_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */
S#define  FMC_SDCR2_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */
S
S#define  FMC_SDCR2_WP                       ((uint32_t)0x00000200)        /*!<Write protection */
S
S#define  FMC_SDCR2_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDCLK[1:0] (SDRAM clock configuration) */
S#define  FMC_SDCR2_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */
S#define  FMC_SDCR2_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */
S
S#define  FMC_SDCR2_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */
S
S#define  FMC_SDCR2_RPIPE                    ((uint32_t)0x00006000)        /*!<RPIPE[1:0](Read pipe) */
S#define  FMC_SDCR2_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */
S#define  FMC_SDCR2_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */
S
S/******************  Bit definition for FMC_SDTR1 register  ******************/
S#define  FMC_SDTR1_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
S#define  FMC_SDTR1_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_SDTR1_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_SDTR1_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_SDTR1_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
S                                            
S#define  FMC_SDTR1_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
S#define  FMC_SDTR1_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_SDTR1_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_SDTR1_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_SDTR1_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_SDTR1_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
S#define  FMC_SDTR1_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_SDTR1_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_SDTR1_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_SDTR1_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  FMC_SDTR1_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
S#define  FMC_SDTR1_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
S#define  FMC_SDTR1_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
S#define  FMC_SDTR1_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
S
S#define  FMC_SDTR1_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
S#define  FMC_SDTR1_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_SDTR1_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_SDTR1_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
S
S#define  FMC_SDTR1_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
S#define  FMC_SDTR1_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_SDTR1_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_SDTR1_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
S
S#define  FMC_SDTR1_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
S#define  FMC_SDTR1_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_SDTR1_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_SDTR1_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
S
S/******************  Bit definition for FMC_SDTR2 register  ******************/
S#define  FMC_SDTR2_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */
S#define  FMC_SDTR2_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_SDTR2_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_SDTR2_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  FMC_SDTR2_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */
S                                            
S#define  FMC_SDTR2_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */
S#define  FMC_SDTR2_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  FMC_SDTR2_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */
S#define  FMC_SDTR2_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */
S#define  FMC_SDTR2_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */
S
S#define  FMC_SDTR2_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */
S#define  FMC_SDTR2_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  FMC_SDTR2_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  FMC_SDTR2_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  FMC_SDTR2_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  FMC_SDTR2_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */
S#define  FMC_SDTR2_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
S#define  FMC_SDTR2_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
S#define  FMC_SDTR2_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
S
S#define  FMC_SDTR2_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */
S#define  FMC_SDTR2_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
S#define  FMC_SDTR2_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
S#define  FMC_SDTR2_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */
S
S#define  FMC_SDTR2_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */
S#define  FMC_SDTR2_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
S#define  FMC_SDTR2_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
S#define  FMC_SDTR2_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */
S
S#define  FMC_SDTR2_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */
S#define  FMC_SDTR2_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
S#define  FMC_SDTR2_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
S#define  FMC_SDTR2_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
S
S/******************  Bit definition for FMC_SDCMR register  ******************/
S#define  FMC_SDCMR_MODE                     ((uint32_t)0x00000007)        /*!<MODE[2:0] bits (Command mode) */
S#define  FMC_SDCMR_MODE_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  FMC_SDCMR_MODE_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  FMC_SDCMR_MODE_2                   ((uint32_t)0x00000003)        /*!<Bit 2 */
S                                            
S#define  FMC_SDCMR_CTB2                     ((uint32_t)0x00000008)        /*!<Command target 2 */
S
S#define  FMC_SDCMR_CTB1                     ((uint32_t)0x00000010)        /*!<Command target 1 */
S
S#define  FMC_SDCMR_NRFS                     ((uint32_t)0x000001E0)        /*!<NRFS[3:0] bits (Number of auto-refresh) */
S#define  FMC_SDCMR_NRFS_0                   ((uint32_t)0x00000020)        /*!<Bit 0 */
S#define  FMC_SDCMR_NRFS_1                   ((uint32_t)0x00000040)        /*!<Bit 1 */
S#define  FMC_SDCMR_NRFS_2                   ((uint32_t)0x00000080)        /*!<Bit 2 */
S#define  FMC_SDCMR_NRFS_3                   ((uint32_t)0x00000100)        /*!<Bit 3 */
S
S#define  FMC_SDCMR_MRD                      ((uint32_t)0x003FFE00)        /*!<MRD[12:0] bits (Mode register definition) */
S
S/******************  Bit definition for FMC_SDRTR register  ******************/
S#define  FMC_SDRTR_CRE                      ((uint32_t)0x00000001)        /*!<Clear refresh error flag */
S
S#define  FMC_SDRTR_COUNT                    ((uint32_t)0x00003FFE)        /*!<COUNT[12:0] bits (Refresh timer count) */
S
S#define  FMC_SDRTR_REIE                     ((uint32_t)0x00004000)        /*!<RES interupt enable */
S
S/******************  Bit definition for FMC_SDSR register  ******************/
S#define  FMC_SDSR_RE                        ((uint32_t)0x00000001)        /*!<Refresh error flag */
S
S#define  FMC_SDSR_MODES1                    ((uint32_t)0x00000006)        /*!<MODES1[1:0]bits (Status mode for bank 1) */
S#define  FMC_SDSR_MODES1_0                  ((uint32_t)0x00000002)        /*!<Bit 0 */
S#define  FMC_SDSR_MODES1_1                  ((uint32_t)0x00000004)        /*!<Bit 1 */
S
S#define  FMC_SDSR_MODES2                    ((uint32_t)0x00000018)        /*!<MODES2[1:0]bits (Status mode for bank 2) */
S#define  FMC_SDSR_MODES2_0                  ((uint32_t)0x00000008)        /*!<Bit 0 */
S#define  FMC_SDSR_MODES2_1                  ((uint32_t)0x00000010)        /*!<Bit 1 */
S
S#define  FMC_SDSR_BUSY                      ((uint32_t)0x00000020)        /*!<Busy status */
S
S#endif /* STM32F427_437xx ||  STM32F429_439xx || STM32F446xx */
S
S/******************************************************************************/
S/*                                                                            */
S/*                            General Purpose I/O                             */
S/*                                                                            */
S/******************************************************************************/
S/******************  Bits definition for GPIO_MODER register  *****************/
S#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
S#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
S#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
S
S#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
S#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
S#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
S
S#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
S#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
S#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
S
S#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
S#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
S#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
S
S#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
S#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
S#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
S
S#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
S#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
S#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
S
S#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
S#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
S#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
S
S#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
S#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
S#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
S
S#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
S#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
S#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
S
S#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
S#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
S#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
S
S#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
S#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
S#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
S
S#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
S#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
S#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
S
S#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
S#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
S#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
S
S#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
S#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
S#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
S
S#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
S#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
S#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
S
S#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
S#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
S#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
S
S/******************  Bits definition for GPIO_OTYPER register  ****************/
S#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
S#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
S#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
S#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
S#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
S#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
S#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
S#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
S#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
S#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
S#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
S#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
S#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
S#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
S#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
S#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
S
S/******************  Bits definition for GPIO_OSPEEDR register  ***************/
S#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
S#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
S#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
S
S#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
S#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
S#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
S
S#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
S#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
S#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
S
S#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
S#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
S#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
S
S#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
S#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
S#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
S
S#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
S#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
S#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
S
S#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
S#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
S#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
S
S#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
S#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
S#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
S
S#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
S#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
S#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
S
S#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
S#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
S#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
S
S#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
S#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
S#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
S
S#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
S#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
S#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
S
S#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
S#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
S#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
S
S#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
S#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
S#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
S
S#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
S#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
S#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
S
S#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
S#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
S#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
S
S/******************  Bits definition for GPIO_PUPDR register  *****************/
S#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
S#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
S#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
S
S#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
S#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
S#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
S
S#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
S#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
S#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
S
S#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
S#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
S#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
S
S#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
S#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
S#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
S
S#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
S#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
S#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
S
S#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
S#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
S#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
S
S#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
S#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
S#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
S
S#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
S#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
S#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
S
S#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
S#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
S#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
S
S#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
S#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
S#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
S
S#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
S#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
S#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
S
S#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
S#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
S#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
S
S#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
S#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
S#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
S
S#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
S#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
S#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
S
S#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
S#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
S#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
S
S/******************  Bits definition for GPIO_IDR register  *******************/
S#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
S#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
S#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
S#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
S#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
S#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
S#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
S#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
S#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
S#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
S#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
S#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
S#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
S#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
S#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
S#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
S/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
S#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
S#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
S#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
S#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
S#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
S#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
S#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
S#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
S#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
S#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
S#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
S#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
S#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
S#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
S#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
S#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
S
S/******************  Bits definition for GPIO_ODR register  *******************/
S#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
S#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
S#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
S#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
S#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
S#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
S#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
S#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
S#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
S#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
S#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
S#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
S#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
S#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
S#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
S#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
S/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
S#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
S#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
S#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
S#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
S#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
S#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
S#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
S#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
S#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
S#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
S#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
S#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
S#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
S#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
S#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
S#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
S
S/******************  Bits definition for GPIO_BSRR register  ******************/
S#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
S#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
S#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
S#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
S#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
S#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
S#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
S#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
S#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
S#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
S#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
S#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
S#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
S#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
S#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
S#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
S#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
S#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
S#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
S#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
S#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
S#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
S#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
S#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
S#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
S#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
S#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
S#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
S#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
S#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
S#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
S#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
S
S/******************************************************************************/
S/*                                                                            */
S/*                                    HASH                                    */
S/*                                                                            */
S/******************************************************************************/
S/******************  Bits definition for HASH_CR register  ********************/
S#define HASH_CR_INIT                         ((uint32_t)0x00000004)
S#define HASH_CR_DMAE                         ((uint32_t)0x00000008)
S#define HASH_CR_DATATYPE                     ((uint32_t)0x00000030)
S#define HASH_CR_DATATYPE_0                   ((uint32_t)0x00000010)
S#define HASH_CR_DATATYPE_1                   ((uint32_t)0x00000020)
S#define HASH_CR_MODE                         ((uint32_t)0x00000040)
S#define HASH_CR_ALGO                         ((uint32_t)0x00040080)
S#define HASH_CR_ALGO_0                       ((uint32_t)0x00000080)
S#define HASH_CR_ALGO_1                       ((uint32_t)0x00040000)
S#define HASH_CR_NBW                          ((uint32_t)0x00000F00)
S#define HASH_CR_NBW_0                        ((uint32_t)0x00000100)
S#define HASH_CR_NBW_1                        ((uint32_t)0x00000200)
S#define HASH_CR_NBW_2                        ((uint32_t)0x00000400)
S#define HASH_CR_NBW_3                        ((uint32_t)0x00000800)
S#define HASH_CR_DINNE                        ((uint32_t)0x00001000)
S#define HASH_CR_MDMAT                        ((uint32_t)0x00002000)
S#define HASH_CR_LKEY                         ((uint32_t)0x00010000)
S
S/******************  Bits definition for HASH_STR register  *******************/
S#define HASH_STR_NBW                         ((uint32_t)0x0000001F)
S#define HASH_STR_NBW_0                       ((uint32_t)0x00000001)
S#define HASH_STR_NBW_1                       ((uint32_t)0x00000002)
S#define HASH_STR_NBW_2                       ((uint32_t)0x00000004)
S#define HASH_STR_NBW_3                       ((uint32_t)0x00000008)
S#define HASH_STR_NBW_4                       ((uint32_t)0x00000010)
S#define HASH_STR_DCAL                        ((uint32_t)0x00000100)
S
S/******************  Bits definition for HASH_IMR register  *******************/
S#define HASH_IMR_DINIM                       ((uint32_t)0x00000001)
S#define HASH_IMR_DCIM                        ((uint32_t)0x00000002)
S
S/******************  Bits definition for HASH_SR register  ********************/
S#define HASH_SR_DINIS                        ((uint32_t)0x00000001)
S#define HASH_SR_DCIS                         ((uint32_t)0x00000002)
S#define HASH_SR_DMAS                         ((uint32_t)0x00000004)
S#define HASH_SR_BUSY                         ((uint32_t)0x00000008)
S
S/******************************************************************************/
S/*                                                                            */
S/*                      Inter-integrated Circuit Interface                    */
S/*                                                                            */
S/******************************************************************************/
S/*******************  Bit definition for I2C_CR1 register  ********************/
S#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!<Peripheral Enable                             */
S#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!<SMBus Mode                                    */
S#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!<SMBus Type                                    */
S#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!<ARP Enable                                    */
S#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!<PEC Enable                                    */
S#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!<General Call Enable                           */
S#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!<Clock Stretching Disable (Slave mode)         */
S#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!<Start Generation                              */
S#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!<Stop Generation                               */
S#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!<Acknowledge Enable                            */
S#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!<Acknowledge/PEC Position (for data reception) */
S#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!<Packet Error Checking                         */
S#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!<SMBus Alert                                   */
S#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!<Software Reset                                */
S
S/*******************  Bit definition for I2C_CR2 register  ********************/
S#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
S#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
S#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
S#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
S#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
S#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
S#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
S
S#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!<Error Interrupt Enable  */
S#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!<Event Interrupt Enable  */
S#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!<Buffer Interrupt Enable */
S#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!<DMA Requests Enable     */
S#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!<DMA Last Transfer       */
S
S/*******************  Bit definition for I2C_OAR1 register  *******************/
S#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!<Interface Address */
S#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!<Interface Address */
S
S#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!<Bit 0 */
S#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!<Bit 1 */
S#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!<Bit 2 */
S#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!<Bit 3 */
S#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!<Bit 4 */
S#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!<Bit 5 */
S#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!<Bit 6 */
S#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!<Bit 7 */
S#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!<Bit 8 */
S#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!<Bit 9 */
S
S#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!<Addressing Mode (Slave mode) */
S
S/*******************  Bit definition for I2C_OAR2 register  *******************/
S#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!<Dual addressing mode enable */
S#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!<Interface address           */
S
S/********************  Bit definition for I2C_DR register  ********************/
S#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!<8-bit Data Register         */
S
S/*******************  Bit definition for I2C_SR1 register  ********************/
S#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!<Start Bit (Master mode)                         */
S#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!<Address sent (master mode)/matched (slave mode) */
S#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!<Byte Transfer Finished                          */
S#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!<10-bit header sent (Master mode)                */
S#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!<Stop detection (Slave mode)                     */
S#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!<Data Register not Empty (receivers)             */
S#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!<Data Register Empty (transmitters)              */
S#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!<Bus Error                                       */
S#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!<Arbitration Lost (master mode)                  */
S#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!<Acknowledge Failure                             */
S#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!<Overrun/Underrun                                */
S#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!<PEC Error in reception                          */
S#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!<Timeout or Tlow Error                           */
S#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!<SMBus Alert                                     */
S
S/*******************  Bit definition for I2C_SR2 register  ********************/
S#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!<Master/Slave                              */
S#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!<Bus Busy                                  */
S#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!<Transmitter/Receiver                      */
S#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!<General Call Address (Slave mode)         */
S#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!<SMBus Device Default Address (Slave mode) */
S#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!<SMBus Host Header (Slave mode)            */
S#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!<Dual Flag (Slave mode)                    */
S#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!<Packet Error Checking Register            */
S
S/*******************  Bit definition for I2C_CCR register  ********************/
S#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!<Clock Control Register in Fast/Standard mode (Master mode) */
S#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!<Fast Mode Duty Cycle                                       */
S#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!<I2C Master Mode Selection                                  */
S
S/******************  Bit definition for I2C_TRISE register  *******************/
S#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
S
S/******************  Bit definition for I2C_FLTR register  *******************/
S#define  I2C_FLTR_DNF                     ((uint8_t)0x0F)                  /*!<Digital Noise Filter    */
S#define  I2C_FLTR_ANOFF                   ((uint8_t)0x10)                  /*!<Analog Noise Filter OFF */
S
S/******************************************************************************/
S/*                                                                            */
S/*              Fast-mode Plus Inter-integrated circuit (FMPI2C)              */
S/*                                                                            */
S/******************************************************************************/
S/*******************  Bit definition for I2C_CR1 register  *******************/
S#define  FMPI2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable                   */
S#define  FMPI2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable                 */
S#define  FMPI2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable                 */
S#define  FMPI2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable      */
S#define  FMPI2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable      */
S#define  FMPI2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable     */
S#define  FMPI2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable  */
S#define  FMPI2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable             */
S#define  FMPI2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter                */
S#define  FMPI2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF             */
S#define  FMPI2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset                      */
S#define  FMPI2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable    */
S#define  FMPI2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable       */
S#define  FMPI2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control                  */
S#define  FMPI2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable            */
S#define  FMPI2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable             */
S#define  FMPI2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable                 */
S#define  FMPI2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable           */
S#define  FMPI2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
S#define  FMPI2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable                  */
S#define  FMPI2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable                          */
S
S/******************  Bit definition for I2C_CR2 register  ********************/
S#define  FMPI2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode)                             */
S#define  FMPI2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode)                        */
S#define  FMPI2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode)                    */
S#define  FMPI2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
S#define  FMPI2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation                                        */
S#define  FMPI2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode)                           */
S#define  FMPI2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode)                            */
S#define  FMPI2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes                                         */
S#define  FMPI2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode                                      */
S#define  FMPI2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode)                        */
S#define  FMPI2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte                              */
S
S/*******************  Bit definition for I2C_OAR1 register  ******************/
S#define  FMPI2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1   */
S#define  FMPI2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
S#define  FMPI2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable     */
S
S/*******************  Bit definition for I2C_OAR2 register  *******************/
S#define  FMPI2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
S#define  FMPI2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks     */
S#define  FMPI2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable    */
S
S/*******************  Bit definition for I2C_TIMINGR register *****************/
S#define  FMPI2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode)  */
S#define  FMPI2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
S#define  FMPI2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time                */
S#define  FMPI2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time               */
S#define  FMPI2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler             */
S
S/******************* Bit definition for I2C_TIMEOUTR register *****************/
S#define  FMPI2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A                 */
S#define  FMPI2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection  */
S#define  FMPI2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable          */
S#define  FMPI2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B                 */
S#define  FMPI2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
S
S/******************  Bit definition for I2C_ISR register  *********************/
S#define  FMPI2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty    */
S#define  FMPI2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status       */
S#define  FMPI2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
S#define  FMPI2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)    */
S#define  FMPI2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag              */
S#define  FMPI2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag             */
S#define  FMPI2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
S#define  FMPI2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload        */
S#define  FMPI2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error                       */
S#define  FMPI2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost                */
S#define  FMPI2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun                */
S#define  FMPI2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception          */
S#define  FMPI2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag  */
S#define  FMPI2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert                     */
S#define  FMPI2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy                        */
S#define  FMPI2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
S#define  FMPI2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
S
S/******************  Bit definition for I2C_ICR register  *********************/
S#define  FMPI2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag  */
S#define  FMPI2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag             */
S#define  FMPI2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag   */
S#define  FMPI2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
S#define  FMPI2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
S#define  FMPI2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
S#define  FMPI2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag        */
S#define  FMPI2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag          */
S#define  FMPI2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag            */
S
S/******************  Bit definition for I2C_PECR register  ********************/
S#define  FMPI2C_PECR_PEC                        ((uint32_t)0x000000FF)        /*!< PEC register */
S
S/******************  Bit definition for I2C_RXDR register  *********************/
S#define  FMPI2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
S
S/******************  Bit definition for I2C_TXDR register  *********************/
S#define  FMPI2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
S
S/******************************************************************************/
S/*                                                                            */
S/*                           Independent WATCHDOG                             */
S/*                                                                            */
S/******************************************************************************/
S/*******************  Bit definition for IWDG_KR register  ********************/
S#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!<Key value (write only, read 0000h)  */
S
S/*******************  Bit definition for IWDG_PR register  ********************/
S#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!<PR[2:0] (Prescaler divider)         */
S#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!<Bit 0 */
S#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!<Bit 1 */
S#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!<Bit 2 */
S
S/*******************  Bit definition for IWDG_RLR register  *******************/
S#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!<Watchdog counter reload value        */
S
S/*******************  Bit definition for IWDG_SR register  ********************/
S#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!<Watchdog prescaler value update      */
S#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!<Watchdog counter reload value update */
S
S/******************************************************************************/
S/*                                                                            */
S/*                      LCD-TFT Display Controller (LTDC)                     */
S/*                                                                            */
S/******************************************************************************/
S
S/********************  Bit definition for LTDC_SSCR register  *****************/
S
S#define LTDC_SSCR_VSH                       ((uint32_t)0x000007FF)              /*!< Vertical Synchronization Height */
S#define LTDC_SSCR_HSW                       ((uint32_t)0x0FFF0000)              /*!< Horizontal Synchronization Width */
S
S/********************  Bit definition for LTDC_BPCR register  *****************/
S
S#define LTDC_BPCR_AVBP                      ((uint32_t)0x000007FF)              /*!< Accumulated Vertical Back Porch */
S#define LTDC_BPCR_AHBP                      ((uint32_t)0x0FFF0000)              /*!< Accumulated Horizontal Back Porch */
S
S/********************  Bit definition for LTDC_AWCR register  *****************/
S
S#define LTDC_AWCR_AAH                       ((uint32_t)0x000007FF)              /*!< Accumulated Active heigh */
S#define LTDC_AWCR_AAW                       ((uint32_t)0x0FFF0000)              /*!< Accumulated Active Width */
S
S/********************  Bit definition for LTDC_TWCR register  *****************/
S
S#define LTDC_TWCR_TOTALH                    ((uint32_t)0x000007FF)              /*!< Total Heigh */
S#define LTDC_TWCR_TOTALW                    ((uint32_t)0x0FFF0000)              /*!< Total Width */
S
S/********************  Bit definition for LTDC_GCR register  ******************/
S
S#define LTDC_GCR_LTDCEN                     ((uint32_t)0x00000001)              /*!< LCD-TFT controller enable bit */
S#define LTDC_GCR_DBW                        ((uint32_t)0x00000070)              /*!< Dither Blue Width */
S#define LTDC_GCR_DGW                        ((uint32_t)0x00000700)              /*!< Dither Green Width */
S#define LTDC_GCR_DRW                        ((uint32_t)0x00007000)              /*!< Dither Red Width */
S#define LTDC_GCR_DTEN                       ((uint32_t)0x00010000)              /*!< Dither Enable */
S#define LTDC_GCR_PCPOL                      ((uint32_t)0x10000000)              /*!< Pixel Clock Polarity */
S#define LTDC_GCR_DEPOL                      ((uint32_t)0x20000000)              /*!< Data Enable Polarity */
S#define LTDC_GCR_VSPOL                      ((uint32_t)0x40000000)              /*!< Vertical Synchronization Polarity */
S#define LTDC_GCR_HSPOL                      ((uint32_t)0x80000000)              /*!< Horizontal Synchronization Polarity */
S
S/********************  Bit definition for LTDC_SRCR register  *****************/
S
S#define LTDC_SRCR_IMR                      ((uint32_t)0x00000001)               /*!< Immediate Reload */
S#define LTDC_SRCR_VBR                      ((uint32_t)0x00000002)               /*!< Vertical Blanking Reload */
S
S/********************  Bit definition for LTDC_BCCR register  *****************/
S
S#define LTDC_BCCR_BCBLUE                    ((uint32_t)0x000000FF)              /*!< Background Blue value */
S#define LTDC_BCCR_BCGREEN                   ((uint32_t)0x0000FF00)              /*!< Background Green value */
S#define LTDC_BCCR_BCRED                     ((uint32_t)0x00FF0000)              /*!< Background Red value */
S
S/********************  Bit definition for LTDC_IER register  ******************/
S
S#define LTDC_IER_LIE                        ((uint32_t)0x00000001)              /*!< Line Interrupt Enable */
S#define LTDC_IER_FUIE                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Enable */
S#define LTDC_IER_TERRIE                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Enable */
S#define LTDC_IER_RRIE                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt enable */
S
S/********************  Bit definition for LTDC_ISR register  ******************/
S
S#define LTDC_ISR_LIF                        ((uint32_t)0x00000001)              /*!< Line Interrupt Flag */
S#define LTDC_ISR_FUIF                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Flag */
S#define LTDC_ISR_TERRIF                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Flag */
S#define LTDC_ISR_RRIF                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt Flag */
S
S/********************  Bit definition for LTDC_ICR register  ******************/
S
S#define LTDC_ICR_CLIF                       ((uint32_t)0x00000001)              /*!< Clears the Line Interrupt Flag */
S#define LTDC_ICR_CFUIF                      ((uint32_t)0x00000002)              /*!< Clears the FIFO Underrun Interrupt Flag */
S#define LTDC_ICR_CTERRIF                    ((uint32_t)0x00000004)              /*!< Clears the Transfer Error Interrupt Flag */
S#define LTDC_ICR_CRRIF                      ((uint32_t)0x00000008)              /*!< Clears Register Reload interrupt Flag */
S
S/********************  Bit definition for LTDC_LIPCR register  ****************/
S
S#define LTDC_LIPCR_LIPOS                    ((uint32_t)0x000007FF)              /*!< Line Interrupt Position */
S
S/********************  Bit definition for LTDC_CPSR register  *****************/
S
S#define LTDC_CPSR_CYPOS                     ((uint32_t)0x0000FFFF)              /*!< Current Y Position */
S#define LTDC_CPSR_CXPOS                     ((uint32_t)0xFFFF0000)              /*!< Current X Position */
S
S/********************  Bit definition for LTDC_CDSR register  *****************/
S
S#define LTDC_CDSR_VDES                      ((uint32_t)0x00000001)              /*!< Vertical Data Enable Status */
S#define LTDC_CDSR_HDES                      ((uint32_t)0x00000002)              /*!< Horizontal Data Enable Status */
S#define LTDC_CDSR_VSYNCS                    ((uint32_t)0x00000004)              /*!< Vertical Synchronization Status */
S#define LTDC_CDSR_HSYNCS                    ((uint32_t)0x00000008)              /*!< Horizontal Synchronization Status */
S
S/********************  Bit definition for LTDC_LxCR register  *****************/
S
S#define LTDC_LxCR_LEN                       ((uint32_t)0x00000001)              /*!< Layer Enable */
S#define LTDC_LxCR_COLKEN                    ((uint32_t)0x00000002)              /*!< Color Keying Enable */
S#define LTDC_LxCR_CLUTEN                    ((uint32_t)0x00000010)              /*!< Color Lockup Table Enable */
S
S/********************  Bit definition for LTDC_LxWHPCR register  **************/
S
S#define LTDC_LxWHPCR_WHSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Horizontal Start Position */
S#define LTDC_LxWHPCR_WHSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Horizontal Stop Position */
S
S/********************  Bit definition for LTDC_LxWVPCR register  **************/
S
S#define LTDC_LxWVPCR_WVSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Vertical Start Position */
S#define LTDC_LxWVPCR_WVSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Vertical Stop Position */
S
S/********************  Bit definition for LTDC_LxCKCR register  ***************/
S
S#define LTDC_LxCKCR_CKBLUE                  ((uint32_t)0x000000FF)              /*!< Color Key Blue value */
S#define LTDC_LxCKCR_CKGREEN                 ((uint32_t)0x0000FF00)              /*!< Color Key Green value */
S#define LTDC_LxCKCR_CKRED                   ((uint32_t)0x00FF0000)              /*!< Color Key Red value */
S
S/********************  Bit definition for LTDC_LxPFCR register  ***************/
S
S#define LTDC_LxPFCR_PF                      ((uint32_t)0x00000007)              /*!< Pixel Format */
S
S/********************  Bit definition for LTDC_LxCACR register  ***************/
S
S#define LTDC_LxCACR_CONSTA                  ((uint32_t)0x000000FF)              /*!< Constant Alpha */
S
S/********************  Bit definition for LTDC_LxDCCR register  ***************/
S
S#define LTDC_LxDCCR_DCBLUE                  ((uint32_t)0x000000FF)              /*!< Default Color Blue */
S#define LTDC_LxDCCR_DCGREEN                 ((uint32_t)0x0000FF00)              /*!< Default Color Green */
S#define LTDC_LxDCCR_DCRED                   ((uint32_t)0x00FF0000)              /*!< Default Color Red */
S#define LTDC_LxDCCR_DCALPHA                 ((uint32_t)0xFF000000)              /*!< Default Color Alpha */
S                                
S/********************  Bit definition for LTDC_LxBFCR register  ***************/
S
S#define LTDC_LxBFCR_BF2                     ((uint32_t)0x00000007)              /*!< Blending Factor 2 */
S#define LTDC_LxBFCR_BF1                     ((uint32_t)0x00000700)              /*!< Blending Factor 1 */
S
S/********************  Bit definition for LTDC_LxCFBAR register  **************/
S
S#define LTDC_LxCFBAR_CFBADD                 ((uint32_t)0xFFFFFFFF)              /*!< Color Frame Buffer Start Address */
S
S/********************  Bit definition for LTDC_LxCFBLR register  **************/
S
S#define LTDC_LxCFBLR_CFBLL                  ((uint32_t)0x00001FFF)              /*!< Color Frame Buffer Line Length */
S#define LTDC_LxCFBLR_CFBP                   ((uint32_t)0x1FFF0000)              /*!< Color Frame Buffer Pitch in bytes */
S
S/********************  Bit definition for LTDC_LxCFBLNR register  *************/
S
S#define LTDC_LxCFBLNR_CFBLNBR               ((uint32_t)0x000007FF)              /*!< Frame Buffer Line Number */
S
S/********************  Bit definition for LTDC_LxCLUTWR register  *************/
S
S#define LTDC_LxCLUTWR_BLUE                  ((uint32_t)0x000000FF)              /*!< Blue value */
S#define LTDC_LxCLUTWR_GREEN                 ((uint32_t)0x0000FF00)              /*!< Green value */
S#define LTDC_LxCLUTWR_RED                   ((uint32_t)0x00FF0000)              /*!< Red value */
S#define LTDC_LxCLUTWR_CLUTADD               ((uint32_t)0xFF000000)              /*!< CLUT address */
S
S/******************************************************************************/
S/*                                                                            */
S/*                             Power Control                                  */
S/*                                                                            */
S/******************************************************************************/
S/********************  Bit definition for PWR_CR register  ********************/
S#define  PWR_CR_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep                 */
S#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep                */
S#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag                   */
S#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag                  */
S#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable       */
S
S#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
S#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
S#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
S#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
S
S/*!< PVD level configuration */
S#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
S#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
S#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
S#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
S#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
S#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
S#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
S#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
S
S#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection                     */
S#define  PWR_CR_FPDS                         ((uint32_t)0x00000200)     /*!< Flash power down in Stop mode                              */
S#define  PWR_CR_LPUDS                        ((uint32_t)0x00000400)     /*!< Low-Power Regulator in Stop under-drive mode               */
S#define  PWR_CR_MRUDS                        ((uint32_t)0x00000800)     /*!< Main regulator in Stop under-drive mode                    */
S
S#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400)     /*!< Low-power regulator Low Voltage in Deep Sleep mode         */
S#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800)     /*!< Main regulator Low Voltage in Deep Sleep mode              */
S
S#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000)     /*!< Refer to AN4073 on how to use this bit */ 
S
S#define  PWR_CR_VOS                          ((uint32_t)0x0000C000)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
S#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000)     /*!< Bit 0 */
S#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000)     /*!< Bit 1 */
S
S#define  PWR_CR_ODEN                         ((uint32_t)0x00010000)     /*!< Over Drive enable                   */
S#define  PWR_CR_ODSWEN                       ((uint32_t)0x00020000)     /*!< Over Drive switch enabled           */
S#define  PWR_CR_UDEN                         ((uint32_t)0x000C0000)     /*!< Under Drive enable in stop mode     */
S#define  PWR_CR_UDEN_0                       ((uint32_t)0x00040000)     /*!< Bit 0                               */
S#define  PWR_CR_UDEN_1                       ((uint32_t)0x00080000)     /*!< Bit 1                               */
S
S#define  PWR_CR_FMSSR                        ((uint32_t)0x00100000)     /*!< Flash Memory Sleep System Run        */
S#define  PWR_CR_FISSR                        ((uint32_t)0x00200000)     /*!< Flash Interface Stop while System Run */
S
S/* Legacy define */
S#define  PWR_CR_PMODE                        PWR_CR_VOS
S
S/*******************  Bit definition for PWR_CSR register  ********************/
S#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag                                      */
S#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag                                     */
S#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output                                       */
S#define  PWR_CSR_BRR                         ((uint32_t)0x00000008)     /*!< Backup regulator ready                           */
S#define  PWR_CSR_WUPP                        ((uint32_t)0x00000080)     /*!< WKUP pin Polarity                                */
S#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100)     /*!< Enable WKUP pin                                  */
S#define  PWR_CSR_BRE                         ((uint32_t)0x00000200)     /*!< Backup regulator enable                          */
S#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000)     /*!< Regulator voltage scaling output selection ready */
S#define  PWR_CSR_ODRDY                       ((uint32_t)0x00010000)     /*!< Over Drive generator ready                       */
S#define  PWR_CSR_ODSWRDY                     ((uint32_t)0x00020000)     /*!< Over Drive Switch ready                          */
S#define  PWR_CSR_UDSWRDY                     ((uint32_t)0x000C0000)     /*!< Under Drive ready                                */
S
S/* Legacy define */
S#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
S
S#if defined(STM32F446xx)
S/******************************************************************************/
S/*                                                                            */
S/*                                    QUADSPI                                 */
S/*                                                                            */
S/******************************************************************************/
S/*****************  Bit definition for QUADSPI_CR register  *******************/
S#define  QUADSPI_CR_EN                           ((uint32_t)0x00000001)            /*!< Enable                             */
S#define  QUADSPI_CR_ABORT                        ((uint32_t)0x00000002)            /*!< Abort request                      */
S#define  QUADSPI_CR_DMAEN                        ((uint32_t)0x00000004)            /*!< DMA Enable                         */
S#define  QUADSPI_CR_TCEN                         ((uint32_t)0x00000008)            /*!< Timeout Counter Enable             */
S#define  QUADSPI_CR_SSHIFT                       ((uint32_t)0x00000030)            /*!< SSHIFT[1:0] Sample Shift           */
S#define  QUADSPI_CR_SSHIFT_0                     ((uint32_t)0x00000010)            /*!< Bit 0 */
S#define  QUADSPI_CR_SSHIFT_1                     ((uint32_t)0x00000020)            /*!< Bit 1 */  
S#define  QUADSPI_CR_DFM                          ((uint32_t)0x00000040)            /*!< Dual Flash Mode                    */
S#define  QUADSPI_CR_FSEL                         ((uint32_t)0x00000080)            /*!< Flash Select                       */
S#define  QUADSPI_CR_FTHRES                       ((uint32_t)0x00000F00)            /*!< FTHRES[3:0] FIFO Level             */
S#define  QUADSPI_CR_FTHRES_0                     ((uint32_t)0x00000100)            /*!< Bit 0 */
S#define  QUADSPI_CR_FTHRES_1                     ((uint32_t)0x00000200)            /*!< Bit 1 */
S#define  QUADSPI_CR_FTHRES_2                     ((uint32_t)0x00000400)            /*!< Bit 2 */
S#define  QUADSPI_CR_FTHRES_3                     ((uint32_t)0x00000800)            /*!< Bit 3 */
S#define  QUADSPI_CR_TEIE                         ((uint32_t)0x00010000)            /*!< Transfer Error Interrupt Enable    */
S#define  QUADSPI_CR_TCIE                         ((uint32_t)0x00020000)            /*!< Transfer Complete Interrupt Enable */
S#define  QUADSPI_CR_FTIE                         ((uint32_t)0x00040000)            /*!< FIFO Threshold Interrupt Enable    */
S#define  QUADSPI_CR_SMIE                         ((uint32_t)0x00080000)            /*!< Status Match Interrupt Enable      */
S#define  QUADSPI_CR_TOIE                         ((uint32_t)0x00100000)            /*!< TimeOut Interrupt Enable           */
S#define  QUADSPI_CR_APMS                         ((uint32_t)0x00400000)            /*!< Bit 1                              */
S#define  QUADSPI_CR_PMM                          ((uint32_t)0x00800000)            /*!< Polling Match Mode                 */
S#define  QUADSPI_CR_PRESCALER                    ((uint32_t)0xFF000000)            /*!< PRESCALER[7:0] Clock prescaler     */
S#define  QUADSPI_CR_PRESCALER_0                  ((uint32_t)0x01000000)            /*!< Bit 0 */
S#define  QUADSPI_CR_PRESCALER_1                  ((uint32_t)0x02000000)            /*!< Bit 1 */
S#define  QUADSPI_CR_PRESCALER_2                  ((uint32_t)0x04000000)            /*!< Bit 2 */
S#define  QUADSPI_CR_PRESCALER_3                  ((uint32_t)0x08000000)            /*!< Bit 3 */
S#define  QUADSPI_CR_PRESCALER_4                  ((uint32_t)0x10000000)            /*!< Bit 4 */
S#define  QUADSPI_CR_PRESCALER_5                  ((uint32_t)0x20000000)            /*!< Bit 5 */
S#define  QUADSPI_CR_PRESCALER_6                  ((uint32_t)0x40000000)            /*!< Bit 6 */
S#define  QUADSPI_CR_PRESCALER_7                  ((uint32_t)0x80000000)            /*!< Bit 7 */
S
S/*****************  Bit definition for QUADSPI_DCR register  ******************/
S#define  QUADSPI_DCR_CKMODE                      ((uint32_t)0x00000001)            /*!< Mode 0 / Mode 3                 */
S#define  QUADSPI_DCR_CSHT                        ((uint32_t)0x00000700)            /*!< CSHT[2:0]: ChipSelect High Time */
S#define  QUADSPI_DCR_CSHT_0                      ((uint32_t)0x00000100)            /*!< Bit 0 */
S#define  QUADSPI_DCR_CSHT_1                      ((uint32_t)0x00000200)            /*!< Bit 1 */
S#define  QUADSPI_DCR_CSHT_2                      ((uint32_t)0x00000400)            /*!< Bit 2 */
S#define  QUADSPI_DCR_FSIZE                       ((uint32_t)0x001F0000)            /*!< FSIZE[4:0]: Flash Size          */
S#define  QUADSPI_DCR_FSIZE_0                     ((uint32_t)0x00010000)            /*!< Bit 0 */
S#define  QUADSPI_DCR_FSIZE_1                     ((uint32_t)0x00020000)            /*!< Bit 1 */
S#define  QUADSPI_DCR_FSIZE_2                     ((uint32_t)0x00040000)            /*!< Bit 2 */
S#define  QUADSPI_DCR_FSIZE_3                     ((uint32_t)0x00080000)            /*!< Bit 3 */
S#define  QUADSPI_DCR_FSIZE_4                     ((uint32_t)0x00100000)            /*!< Bit 4 */
S
S/******************  Bit definition for QUADSPI_SR register  *******************/
S#define  QUADSPI_SR_TEF                          ((uint32_t)0x00000001)             /*!< Transfer Error Flag     */
S#define  QUADSPI_SR_TCF                          ((uint32_t)0x00000002)             /*!< Transfer Complete Flag  */
S#define  QUADSPI_SR_FTF                          ((uint32_t)0x00000004)             /*!< FIFO Threshlod Flag     */
S#define  QUADSPI_SR_SMF                          ((uint32_t)0x00000008)             /*!< Status Match Flag       */
S#define  QUADSPI_SR_TOF                          ((uint32_t)0x00000010)             /*!< Timeout Flag            */
S#define  QUADSPI_SR_BUSY                         ((uint32_t)0x00000020)             /*!< Busy                    */
S#define  QUADSPI_SR_FLEVEL                       ((uint32_t)0x00003F00)             /*!< FIFO Level              */
S#define  QUADSPI_SR_FLEVEL_0                     ((uint32_t)0x00000100)             /*!< Bit 0 */
S#define  QUADSPI_SR_FLEVEL_1                     ((uint32_t)0x00000200)             /*!< Bit 1 */
S#define  QUADSPI_SR_FLEVEL_2                     ((uint32_t)0x00000400)             /*!< Bit 2 */
S#define  QUADSPI_SR_FLEVEL_3                     ((uint32_t)0x00000800)             /*!< Bit 3 */
S#define  QUADSPI_SR_FLEVEL_4                     ((uint32_t)0x00001000)             /*!< Bit 4 */
S#define  QUADSPI_SR_FLEVEL_5                     ((uint32_t)0x00002000)             /*!< Bit 5 */
S
S/******************  Bit definition for QUADSPI_FCR register  ******************/
S#define  QUADSPI_FCR_CTEF                        ((uint32_t)0x00000001)             /*!< Clear Transfer Error Flag    */
S#define  QUADSPI_FCR_CTCF                        ((uint32_t)0x00000002)             /*!< Clear Transfer Complete Flag */
S#define  QUADSPI_FCR_CSMF                        ((uint32_t)0x00000008)             /*!< Clear Status Match Flag      */
S#define  QUADSPI_FCR_CTOF                        ((uint32_t)0x00000010)             /*!< Clear Timeout Flag           */
S
S/******************  Bit definition for QUADSPI_DLR register  ******************/
S#define  QUADSPI_DLR_DL                        ((uint32_t)0xFFFFFFFF)               /*!< DL[31:0]: Data Length */
S
S/******************  Bit definition for QUADSPI_CCR register  ******************/
S#define  QUADSPI_CCR_INSTRUCTION                  ((uint32_t)0x000000FF)            /*!< INSTRUCTION[7:0]: Instruction */
S#define  QUADSPI_CCR_INSTRUCTION_0                ((uint32_t)0x00000001)            /*!< Bit 0 */
S#define  QUADSPI_CCR_INSTRUCTION_1                ((uint32_t)0x00000002)            /*!< Bit 1 */
S#define  QUADSPI_CCR_INSTRUCTION_2                ((uint32_t)0x00000004)            /*!< Bit 2 */
S#define  QUADSPI_CCR_INSTRUCTION_3                ((uint32_t)0x00000008)            /*!< Bit 3 */
S#define  QUADSPI_CCR_INSTRUCTION_4                ((uint32_t)0x00000010)            /*!< Bit 4 */
S#define  QUADSPI_CCR_INSTRUCTION_5                ((uint32_t)0x00000020)            /*!< Bit 5 */
S#define  QUADSPI_CCR_INSTRUCTION_6                ((uint32_t)0x00000040)            /*!< Bit 6 */
S#define  QUADSPI_CCR_INSTRUCTION_7                ((uint32_t)0x00000080)            /*!< Bit 7 */
S#define  QUADSPI_CCR_IMODE                        ((uint32_t)0x00000300)            /*!< IMODE[1:0]: Instruction Mode */
S#define  QUADSPI_CCR_IMODE_0                      ((uint32_t)0x00000100)            /*!< Bit 0 */
S#define  QUADSPI_CCR_IMODE_1                      ((uint32_t)0x00000200)            /*!< Bit 1 */
S#define  QUADSPI_CCR_ADMODE                       ((uint32_t)0x00000C00)            /*!< ADMODE[1:0]: Address Mode */
S#define  QUADSPI_CCR_ADMODE_0                     ((uint32_t)0x00000400)            /*!< Bit 0 */
S#define  QUADSPI_CCR_ADMODE_1                     ((uint32_t)0x00000800)            /*!< Bit 1 */
S#define  QUADSPI_CCR_ADSIZE                       ((uint32_t)0x00003000)            /*!< ADSIZE[1:0]: Address Size */
S#define  QUADSPI_CCR_ADSIZE_0                     ((uint32_t)0x00001000)            /*!< Bit 0 */
S#define  QUADSPI_CCR_ADSIZE_1                     ((uint32_t)0x00002000)            /*!< Bit 1 */
S#define  QUADSPI_CCR_ABMODE                       ((uint32_t)0x0000C000)            /*!< ABMODE[1:0]: Alternate Bytes Mode */
S#define  QUADSPI_CCR_ABMODE_0                     ((uint32_t)0x00004000)            /*!< Bit 0 */
S#define  QUADSPI_CCR_ABMODE_1                     ((uint32_t)0x00008000)            /*!< Bit 1 */
S#define  QUADSPI_CCR_ABSIZE                       ((uint32_t)0x00030000)            /*!< ABSIZE[1:0]: Instruction Mode */
S#define  QUADSPI_CCR_ABSIZE_0                     ((uint32_t)0x00010000)            /*!< Bit 0 */
S#define  QUADSPI_CCR_ABSIZE_1                     ((uint32_t)0x00020000)            /*!< Bit 1 */
S#define  QUADSPI_CCR_DCYC                         ((uint32_t)0x007C0000)            /*!< DCYC[4:0]: Dummy Cycles */
S#define  QUADSPI_CCR_DCYC_0                       ((uint32_t)0x00040000)            /*!< Bit 0 */
S#define  QUADSPI_CCR_DCYC_1                       ((uint32_t)0x00080000)            /*!< Bit 1 */
S#define  QUADSPI_CCR_DCYC_2                       ((uint32_t)0x00100000)            /*!< Bit 2 */
S#define  QUADSPI_CCR_DCYC_3                       ((uint32_t)0x00200000)            /*!< Bit 3 */
S#define  QUADSPI_CCR_DCYC_4                       ((uint32_t)0x00400000)            /*!< Bit 4 */
S#define  QUADSPI_CCR_DMODE                        ((uint32_t)0x03000000)            /*!< DMODE[1:0]: Data Mode */
S#define  QUADSPI_CCR_DMODE_0                      ((uint32_t)0x01000000)            /*!< Bit 0 */
S#define  QUADSPI_CCR_DMODE_1                      ((uint32_t)0x02000000)            /*!< Bit 1 */
S#define  QUADSPI_CCR_FMODE                        ((uint32_t)0x0C000000)            /*!< FMODE[1:0]: Functional Mode */
S#define  QUADSPI_CCR_FMODE_0                      ((uint32_t)0x04000000)            /*!< Bit 0 */
S#define  QUADSPI_CCR_FMODE_1                      ((uint32_t)0x08000000)            /*!< Bit 1 */
S#define  QUADSPI_CCR_SIOO                         ((uint32_t)0x10000000)            /*!< SIOO: Send Instruction Only Once Mode */
S#define  QUADSPI_CCR_DHHC                         ((uint32_t)0x40000000)            /*!< DHHC: Delay Half Hclk Cycle */
S#define  QUADSPI_CCR_DDRM                         ((uint32_t)0x80000000)            /*!< DDRM: Double Data Rate Mode */ 
S/******************  Bit definition for QUADSPI_AR register  *******************/
S#define  QUADSPI_AR_ADDRESS                       ((uint32_t)0xFFFFFFFF)            /*!< ADDRESS[31:0]: Address */
S
S/******************  Bit definition for QUADSPI_ABR register  ******************/
S#define  QUADSPI_ABR_ALTERNATE                    ((uint32_t)0xFFFFFFFF)            /*!< ALTERNATE[31:0]: Alternate Bytes */
S
S/******************  Bit definition for QUADSPI_DR register  *******************/
S#define  QUADSPI_DR_DATA                          ((uint32_t)0xFFFFFFFF)            /*!< DATA[31:0]: Data */
S
S/******************  Bit definition for QUADSPI_PSMKR register  ****************/
S#define  QUADSPI_PSMKR_MASK                       ((uint32_t)0xFFFFFFFF)            /*!< MASK[31:0]: Status Mask */
S
S/******************  Bit definition for QUADSPI_PSMAR register  ****************/
S#define  QUADSPI_PSMAR_MATCH                      ((uint32_t)0xFFFFFFFF)            /*!< MATCH[31:0]: Status Match */
S
S/******************  Bit definition for QUADSPI_PIR register  *****************/
S#define  QUADSPI_PIR_INTERVAL                     ((uint32_t)0x0000FFFF)            /*!< INTERVAL[15:0]: Polling Interval */
S
S/******************  Bit definition for QUADSPI_LPTR register  *****************/
S#define  QUADSPI_LPTR_TIMEOUT                     ((uint32_t)0x0000FFFF)            /*!< TIMEOUT[15:0]: Timeout period */
S#endif /* STM32F446xx */
S
S/******************************************************************************/
S/*                                                                            */
S/*                         Reset and Clock Control                            */
S/*                                                                            */
S/******************************************************************************/
S/********************  Bit definition for RCC_CR register  ********************/
S#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
S#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
S
S#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
S#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
S#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
S#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
S#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
S#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
S
S#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
S#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
S#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
S#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
S#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
S#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
S#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
S#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
S#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
S
S#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
S#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
S#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
S#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
S#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
S#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
S#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)
S#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)
S#define  RCC_CR_PLLSAION                     ((uint32_t)0x10000000)
S#define  RCC_CR_PLLSAIRDY                    ((uint32_t)0x20000000)
S
S/********************  Bit definition for RCC_PLLCFGR register  ***************/
S#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
S#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
S#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
S#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
S#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
S#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
S#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
S
S#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
S#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
S#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
S#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
S#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
S#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
S#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
S#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
S#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
S#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
S
S#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
S#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
S#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
S
S#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
S#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
S#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
S
S#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
S#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
S#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
S#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
S#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
S
S#if defined(STM32F446xx)
S#define  RCC_PLLCFGR_PLLR                    ((uint32_t)0x70000000)
S#define  RCC_PLLCFGR_PLLR_0                  ((uint32_t)0x10000000)
S#define  RCC_PLLCFGR_PLLR_1                  ((uint32_t)0x20000000)
S#define  RCC_PLLCFGR_PLLR_2                  ((uint32_t)0x40000000)
S#endif /* STM32F446xx */
S
S/********************  Bit definition for RCC_CFGR register  ******************/
S/*!< SW configuration */
S#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
S#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
S#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
S
S#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
S#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
S#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL/PLLP selected as system clock */
S#if defined(STM32F446xx)
S#define  RCC_CFGR_SW_PLLR                    ((uint32_t)0x00000003)        /*!< PLL/PLLR selected as system clock */
S#endif /* STM32F446xx */
S
S/*!< SWS configuration */
S#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
S#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
S#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
S
S#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
S#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
S#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL/PLLP used as system clock       */
S#if defined(STM32F446xx)
S#define  RCC_CFGR_SWS_PLLR                   ((uint32_t)0x0000000C)        /*!< PLL/PLLR used as system clock       */
S#endif /* STM32F446xx */
S
S/*!< HPRE configuration */
S#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
S#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
S#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
S#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
S#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
S
S#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
S#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
S#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
S#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
S#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
S#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
S#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
S#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
S#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
S
S/*!< PPRE1 configuration */
S#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
S#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
S#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
S#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
S
S#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
S#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
S#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
S#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
S#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
S
S/*!< PPRE2 configuration */
S#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
S#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
S#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
S#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
S
S#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
S#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
S#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
S#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
S#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        /*!< HCLK divided by 16 */
S
S/*!< RTCPRE configuration */
S#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
S#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
S#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
S#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
S#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
S#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
S
S/*!< MCO1 configuration */
S#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
S#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
S#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
S
S#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)
S
S#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
S#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
S#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
S#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
S
S#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
S#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
S#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
S#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
S
S#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
S#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
S#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
S
S/********************  Bit definition for RCC_CIR register  *******************/
S#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
S#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
S#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
S#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
S#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
S#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)
S#define  RCC_CIR_PLLSAIRDYF                  ((uint32_t)0x00000040)
S#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
S#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
S#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
S#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
S#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
S#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
S#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)
S#define  RCC_CIR_PLLSAIRDYIE                 ((uint32_t)0x00004000)
S#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
S#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
S#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
S#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
S#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
S#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)
S#define  RCC_CIR_PLLSAIRDYC                  ((uint32_t)0x00400000)
S#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
S
S/********************  Bit definition for RCC_AHB1RSTR register  **************/
S#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
S#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
S#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
S#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)
S#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)
S#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020)
S#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040)
S#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
S#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100)
S#define  RCC_AHB1RSTR_GPIOJRST               ((uint32_t)0x00000200)
S#define  RCC_AHB1RSTR_GPIOKRST               ((uint32_t)0x00000400)
S#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
S#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
S#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
S#define  RCC_AHB1RSTR_DMA2DRST               ((uint32_t)0x00800000)
S#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000)
S#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x10000000)
S
S/********************  Bit definition for RCC_AHB2RSTR register  **************/
S#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001)
S#define  RCC_AHB2RSTR_CRYPRST                ((uint32_t)0x00000010)
S#define  RCC_AHB2RSTR_HASHRST                ((uint32_t)0x00000020)
S /* maintained for legacy purpose */
S #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
S#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040)
S#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)
S
S/********************  Bit definition for RCC_AHB3RSTR register  **************/
S#if defined(STM32F40_41xxx)
S#define  RCC_AHB3RSTR_FSMCRST                ((uint32_t)0x00000001)
S#endif /* STM32F40_41xxx */
S
S#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
S#define  RCC_AHB3RSTR_FMCRST                ((uint32_t)0x00000001)
S#endif /* STM32F427_437xx ||  STM32F429_439xx || STM32F446xx */
S#if defined(STM32F446xx)
S#define  RCC_AHB3RSTR_QSPIRST               ((uint32_t)0x00000002)
S#endif /* STM32F446xx */
S
S/********************  Bit definition for RCC_APB1RSTR register  **************/
S#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)
S#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)
S#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)
S#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
S#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)
S#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)
S#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)
S#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)
S#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)
S#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)
S#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)
S#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)
S#if defined(STM32F446xx)
S#define  RCC_APB1RSTR_SPDIFRXRST             ((uint32_t)0x00010000)
S#endif /* STM32F446xx */
S#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
S#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)
S#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)
S#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)
S#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
S#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
S#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)
S#if defined(STM32F446xx)
S#define  RCC_APB1RSTR_FMPI2C1RST             ((uint32_t)0x01000000)
S#endif /* STM32F446xx */
S#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)
S#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)
S#if defined(STM32F446xx)
S#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x08000000)
S#endif /* STM32F446xx */
S#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
S#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)
S#define  RCC_APB1RSTR_UART7RST               ((uint32_t)0x40000000)
S#define  RCC_APB1RSTR_UART8RST               ((uint32_t)0x80000000)
S
S/********************  Bit definition for RCC_APB2RSTR register  **************/
S#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
S#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002)
S#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
S#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
S#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
S#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)
S#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)
S#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000)
S#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
S#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
S#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)
S#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
S#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000)
S#define  RCC_APB2RSTR_SPI6RST                ((uint32_t)0x00200000)
S#define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00400000)
S#if defined(STM32F446xx)
S#define  RCC_APB2RSTR_SAI2RST                ((uint32_t)0x00800000)
S#endif /* STM32F446xx */
S#define  RCC_APB2RSTR_LTDCRST                ((uint32_t)0x04000000)
S
S/* Old SPI1RST bit definition, maintained for legacy purpose */
S#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
S
S/********************  Bit definition for RCC_AHB1ENR register  ***************/
S#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
S#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
S#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
S#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)
S#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)
S#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020)
S#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040)
S#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
S#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100)
S#define  RCC_AHB1ENR_GPIOJEN                 ((uint32_t)0x00000200)
S#define  RCC_AHB1ENR_GPIOKEN                 ((uint32_t)0x00000400)
S#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
S#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)
S#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000)
S#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
S#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
S#define  RCC_AHB1ENR_DMA2DEN                 ((uint32_t)0x00800000)
S#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000)
S#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000)
S#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000)
S#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000)
S#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000)
S#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000)
S
S/********************  Bit definition for RCC_AHB2ENR register  ***************/
S#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001)
S#define  RCC_AHB2ENR_CRYPEN                  ((uint32_t)0x00000010)
S#define  RCC_AHB2ENR_HASHEN                  ((uint32_t)0x00000020)
S#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040)
S#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)
S
S/********************  Bit definition for RCC_AHB3ENR register  ***************/
S
S#if defined(STM32F40_41xxx)
S#define  RCC_AHB3ENR_FSMCEN                  ((uint32_t)0x00000001)
S#endif /* STM32F40_41xxx */
S
S#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
S#define  RCC_AHB3ENR_FMCEN                  ((uint32_t)0x00000001)
S#endif /* STM32F427_437xx ||  STM32F429_439xx || STM32F446xx */
S
S#if defined(STM32F446xx)
S#define  RCC_AHB3ENR_QSPIEN                 ((uint32_t)0x00000002)
S#endif /* STM32F446xx */
S
S/********************  Bit definition for RCC_APB1ENR register  ***************/
S#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)
S#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)
S#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)
S#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
S#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)
S#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)
S#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)
S#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)
S#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)
S#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
S#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
S#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)
S#if defined(STM32F446xx)
S#define  RCC_APB1ENR_SPDIFRXEN               ((uint32_t)0x00010000)
S#endif /* STM32F446xx */
S#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
S#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)
S#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)
S#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)
S#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
S#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
S#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)
S#if defined(STM32F446xx)
S#define  RCC_APB1ENR_FMPI2C1EN               ((uint32_t)0x01000000)
S#endif /* STM32F446xx */
S#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)
S#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)
S#if defined(STM32F446xx)
S#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x08000000)
S#endif /* STM32F446xx */
S#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
S#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)
S#define  RCC_APB1ENR_UART7EN                 ((uint32_t)0x40000000)
S#define  RCC_APB1ENR_UART8EN                 ((uint32_t)0x80000000)
S
S/********************  Bit definition for RCC_APB2ENR register  ***************/
S#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
S#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002)
S#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
S#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
S#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
S#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200)
S#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400)
S#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)
S#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
S#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000)
S#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
S#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
S#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)
S#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
S#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000)
S#define  RCC_APB2ENR_SPI6EN                  ((uint32_t)0x00200000)
S#define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00400000)
S#if defined(STM32F446xx)
S#define  RCC_APB2ENR_SAI2EN                  ((uint32_t)0x00800000)
S#endif /* STM32F446xx */
S#define  RCC_APB2ENR_LTDCEN                  ((uint32_t)0x04000000)
S
S/********************  Bit definition for RCC_AHB1LPENR register  *************/
S#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
S#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
S#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
S#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)
S#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)
S#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020)
S#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040)
S#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
S#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100)
S#define  RCC_AHB1LPENR_GPIOJLPEN             ((uint32_t)0x00000200)
S#define  RCC_AHB1LPENR_GPIOKLPEN             ((uint32_t)0x00000400)
S#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
S#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
S#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
S#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)
S#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)
S#define  RCC_AHB1LPENR_SRAM3LPEN             ((uint32_t)0x00080000)
S#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
S#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
S#define  RCC_AHB1LPENR_DMA2DLPEN             ((uint32_t)0x00800000)
S#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000)
S#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000)
S#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000)
S#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000)
S#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000)
S#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000)
S
S/********************  Bit definition for RCC_AHB2LPENR register  *************/
S#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001)
S#define  RCC_AHB2LPENR_CRYPLPEN              ((uint32_t)0x00000010)
S#define  RCC_AHB2LPENR_HASHLPEN              ((uint32_t)0x00000020)
S#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040)
S#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)
S
S/********************  Bit definition for RCC_AHB3LPENR register  *************/
S#if defined(STM32F40_41xxx)
S#define  RCC_AHB3LPENR_FSMCLPEN              ((uint32_t)0x00000001)
S#endif /* STM32F40_41xxx */
S
S#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
S#define  RCC_AHB3LPENR_FMCLPEN              ((uint32_t)0x00000001)
S#endif /* STM32F427_437xx ||  STM32F429_439xx  || STM32F446xx */
S#if defined(STM32F446xx)
S#define  RCC_AHB3LPENR_QSPILPEN             ((uint32_t)0x00000002)
S#endif /* STM32F446xx */
S
S/********************  Bit definition for RCC_APB1LPENR register  *************/
S#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)
S#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)
S#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)
S#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
S#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)
S#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)
S#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040)
S#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080)
S#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100)
S#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
S#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
S#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)
S#if defined(STM32F446xx)
S#define  RCC_APB1LPENR_SPDIFRXLPEN           ((uint32_t)0x00010000)
S#endif /* STM32F446xx */
S#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
S#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)
S#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)
S#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)
S#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
S#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
S#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)
S#if defined(STM32F446xx)
S#define  RCC_APB1LPENR_FMPI2C1LPEN           ((uint32_t)0x01000000)
S#endif /* STM32F446xx */
S#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000)
S#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000)
S#if defined(STM32F446xx)
S#define  RCC_APB1LPENR_CECLPEN               ((uint32_t)0x08000000)
S#endif /* STM32F446xx */
S#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
S#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
S#define  RCC_APB1LPENR_UART7LPEN             ((uint32_t)0x40000000)
S#define  RCC_APB1LPENR_UART8LPEN             ((uint32_t)0x80000000)
S
S/********************  Bit definition for RCC_APB2LPENR register  *************/
S#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
S#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002)
S#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
S#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
S#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
S#define  RCC_APB2LPENR_ADC2PEN               ((uint32_t)0x00000200)
S#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400)
S#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)
S#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
S#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000)
S#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
S#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
S#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)
S#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
S#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000)
S#define  RCC_APB2LPENR_SPI6LPEN              ((uint32_t)0x00200000)
S#define  RCC_APB2LPENR_SAI1LPEN              ((uint32_t)0x00400000)
S#if defined(STM32F446xx)
S#define  RCC_APB2LPENR_SAI2LPEN              ((uint32_t)0x00800000)
S#endif /* STM32F446xx */
S#define  RCC_APB2LPENR_LTDCLPEN              ((uint32_t)0x04000000)
S
S/********************  Bit definition for RCC_BDCR register  ******************/
S#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
S#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
S#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
S#define  RCC_BDCR_LSEMOD                     ((uint32_t)0x00000008)
S
S#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)
S#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)
S#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)
S
S#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
S#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
S
S/********************  Bit definition for RCC_CSR register  *******************/
S#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
S#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
S#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
S#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
S#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)
S#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
S#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
S#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)
S#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
S#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
S
S/********************  Bit definition for RCC_SSCGR register  *****************/
S#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
S#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
S#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
S#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
S
S/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
S#define  RCC_PLLI2SCFGR_PLLI2SM              ((uint32_t)0x0000003F)
S#define  RCC_PLLI2SCFGR_PLLI2SM_0            ((uint32_t)0x00000001)
S#define  RCC_PLLI2SCFGR_PLLI2SM_1            ((uint32_t)0x00000002)
S#define  RCC_PLLI2SCFGR_PLLI2SM_2            ((uint32_t)0x00000004)
S#define  RCC_PLLI2SCFGR_PLLI2SM_3            ((uint32_t)0x00000008)
S#define  RCC_PLLI2SCFGR_PLLI2SM_4            ((uint32_t)0x00000010)
S#define  RCC_PLLI2SCFGR_PLLI2SM_5            ((uint32_t)0x00000020)
S
S#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)
S#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040)
S#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080)
S#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100)
S#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200)
S#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400)
S#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800)
S#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000)
S#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000)
S#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000)
S
S#if defined(STM32F446xx)
S#define  RCC_PLLI2SCFGR_PLLI2SP              ((uint32_t)0x00030000)
S#define  RCC_PLLI2SCFGR_PLLI2SP_0            ((uint32_t)0x00010000)
S#define  RCC_PLLI2SCFGR_PLLI2SP_1            ((uint32_t)0x00020000)
S#endif /* STM32F446xx */
S
S#define  RCC_PLLI2SCFGR_PLLI2SQ              ((uint32_t)0x0F000000)
S#define  RCC_PLLI2SCFGR_PLLI2SQ_0            ((uint32_t)0x01000000)
S#define  RCC_PLLI2SCFGR_PLLI2SQ_1            ((uint32_t)0x02000000)
S#define  RCC_PLLI2SCFGR_PLLI2SQ_2            ((uint32_t)0x04000000)
S#define  RCC_PLLI2SCFGR_PLLI2SQ_3            ((uint32_t)0x08000000)
S
S#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)
S#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000)
S#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000)
S#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000)
S
S/********************  Bit definition for RCC_PLLSAICFGR register  ************/
S#if defined(STM32F446xx)
S#define  RCC_PLLSAICFGR_PLLSAIM              ((uint32_t)0x0000003F)
S#define  RCC_PLLSAICFGR_PLLSAIM_0            ((uint32_t)0x00000001)
S#define  RCC_PLLSAICFGR_PLLSAIM_1            ((uint32_t)0x00000002)
S#define  RCC_PLLSAICFGR_PLLSAIM_2            ((uint32_t)0x00000004)
S#define  RCC_PLLSAICFGR_PLLSAIM_3            ((uint32_t)0x00000008)
S#define  RCC_PLLSAICFGR_PLLSAIM_4            ((uint32_t)0x00000010)
S#define  RCC_PLLSAICFGR_PLLSAIM_5            ((uint32_t)0x00000020)
S#endif /* STM32F446xx */
S
S#define  RCC_PLLSAICFGR_PLLSAIN              ((uint32_t)0x00007FC0)
S#define  RCC_PLLSAICFGR_PLLSAIN_0            ((uint32_t)0x00000040)
S#define  RCC_PLLSAICFGR_PLLSAIN_1            ((uint32_t)0x00000080)
S#define  RCC_PLLSAICFGR_PLLSAIN_2            ((uint32_t)0x00000100)
S#define  RCC_PLLSAICFGR_PLLSAIN_3            ((uint32_t)0x00000200)
S#define  RCC_PLLSAICFGR_PLLSAIN_4            ((uint32_t)0x00000400)
S#define  RCC_PLLSAICFGR_PLLSAIN_5            ((uint32_t)0x00000800)
S#define  RCC_PLLSAICFGR_PLLSAIN_6            ((uint32_t)0x00001000)
S#define  RCC_PLLSAICFGR_PLLSAIN_7            ((uint32_t)0x00002000)
S#define  RCC_PLLSAICFGR_PLLSAIN_8            ((uint32_t)0x00004000)
S
S#if defined(STM32F446xx)  
S#define  RCC_PLLSAICFGR_PLLSAIP              ((uint32_t)0x00030000)
S#define  RCC_PLLSAICFGR_PLLSAIP_0            ((uint32_t)0x00010000)
S#define  RCC_PLLSAICFGR_PLLSAIP_1            ((uint32_t)0x00020000)
S#endif /* STM32F446xx */
S
S#define  RCC_PLLSAICFGR_PLLSAIQ              ((uint32_t)0x0F000000)
S#define  RCC_PLLSAICFGR_PLLSAIQ_0            ((uint32_t)0x01000000)
S#define  RCC_PLLSAICFGR_PLLSAIQ_1            ((uint32_t)0x02000000)
S#define  RCC_PLLSAICFGR_PLLSAIQ_2            ((uint32_t)0x04000000)
S#define  RCC_PLLSAICFGR_PLLSAIQ_3            ((uint32_t)0x08000000)
S
S#define  RCC_PLLSAICFGR_PLLSAIR              ((uint32_t)0x70000000)
S#define  RCC_PLLSAICFGR_PLLSAIR_0            ((uint32_t)0x10000000)
S#define  RCC_PLLSAICFGR_PLLSAIR_1            ((uint32_t)0x20000000)
S#define  RCC_PLLSAICFGR_PLLSAIR_2            ((uint32_t)0x40000000)
S
S/********************  Bit definition for RCC_DCKCFGR register  ***************/
S#define  RCC_DCKCFGR_PLLI2SDIVQ              ((uint32_t)0x0000001F)
S#define  RCC_DCKCFGR_PLLSAIDIVQ              ((uint32_t)0x00001F00)
S#define  RCC_DCKCFGR_PLLSAIDIVR              ((uint32_t)0x00030000)
S
S#define  RCC_DCKCFGR_SAI1ASRC                ((uint32_t)0x00300000)
S#define  RCC_DCKCFGR_SAI1ASRC_0              ((uint32_t)0x00100000)
S#define  RCC_DCKCFGR_SAI1ASRC_1              ((uint32_t)0x00200000)
S#if defined(STM32F446xx)
S#define  RCC_DCKCFGR_SAI1SRC                 ((uint32_t)0x00300000)
S#define  RCC_DCKCFGR_SAI1SRC_0               ((uint32_t)0x00100000)
S#define  RCC_DCKCFGR_SAI1SRC_1               ((uint32_t)0x00200000)
S#endif /* STM32F446xx */
S
S#define  RCC_DCKCFGR_SAI1BSRC                ((uint32_t)0x00C00000)
S#define  RCC_DCKCFGR_SAI1BSRC_0              ((uint32_t)0x00400000)
S#define  RCC_DCKCFGR_SAI1BSRC_1              ((uint32_t)0x00800000)
S#if defined(STM32F446xx)
S#define  RCC_DCKCFGR_SAI2SRC                 ((uint32_t)0x00C00000)
S#define  RCC_DCKCFGR_SAI2SRC_0               ((uint32_t)0x00400000)
S#define  RCC_DCKCFGR_SAI2SRC_1               ((uint32_t)0x00800000)
S#endif /* STM32F446xx */
S
S#define  RCC_DCKCFGR_TIMPRE                  ((uint32_t)0x01000000)
S#define  RCC_DCKCFGR_CK48MSEL                ((uint32_t)0x08000000)
S
S#if defined(STM32F446xx)
S#define  RCC_DCKCFGR_I2S1SRC                 ((uint32_t)0x06000000)
S#define  RCC_DCKCFGR_I2S1SRC_0               ((uint32_t)0x02000000)
S#define  RCC_DCKCFGR_I2S1SRC_1               ((uint32_t)0x04000000)
S#define  RCC_DCKCFGR_I2S2SRC                 ((uint32_t)0x18000000)
S#define  RCC_DCKCFGR_I2S2SRC_0               ((uint32_t)0x08000000)
S#define  RCC_DCKCFGR_I2S2SRC_1               ((uint32_t)0x10000000)
S
S/********************  Bit definition for RCC_CKGATENR register  ***************/
S#define  RCC_CKGATENR_AHB2APB1_CKEN          ((uint32_t)0x00000001)
S#define  RCC_CKGATENR_AHB2APB2_CKEN          ((uint32_t)0x00000002)
S#define  RCC_CKGATENR_CM4DBG_CKEN            ((uint32_t)0x00000004)
S#define  RCC_CKGATENR_SPARE_CKEN             ((uint32_t)0x00000008)
S#define  RCC_CKGATENR_SRAM_CKEN              ((uint32_t)0x00000010)
S#define  RCC_CKGATENR_FLITF_CKEN             ((uint32_t)0x00000020)
S#define  RCC_CKGATENR_RCC_CKEN               ((uint32_t)0x00000040)
S
S/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
S#define  RCC_DCKCFGR2_FMPI2C1SEL             ((uint32_t)0x00C00000)
S#define  RCC_DCKCFGR2_FMPI2C1SEL_0           ((uint32_t)0x00400000)
S#define  RCC_DCKCFGR2_FMPI2C1SEL_1           ((uint32_t)0x00800000)
S#define  RCC_DCKCFGR2_CECSEL                 ((uint32_t)0x04000000)
S#define  RCC_DCKCFGR2_CK48MSEL               ((uint32_t)0x08000000)
S#define  RCC_DCKCFGR2_SDIOSEL                ((uint32_t)0x10000000)
S#define  RCC_DCKCFGR2_SPDIFRXSEL               ((uint32_t)0x20000000)
S#endif /* STM32F446xx */
S
S/******************************************************************************/
S/*                                                                            */
S/*                                    RNG                                     */
S/*                                                                            */
S/******************************************************************************/
S/********************  Bits definition for RNG_CR register  *******************/
S#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
S#define RNG_CR_IE                            ((uint32_t)0x00000008)
S
S/********************  Bits definition for RNG_SR register  *******************/
S#define RNG_SR_DRDY                          ((uint32_t)0x00000001)
S#define RNG_SR_CECS                          ((uint32_t)0x00000002)
S#define RNG_SR_SECS                          ((uint32_t)0x00000004)
S#define RNG_SR_CEIS                          ((uint32_t)0x00000020)
S#define RNG_SR_SEIS                          ((uint32_t)0x00000040)
S
S/******************************************************************************/
S/*                                                                            */
S/*                           Real-Time Clock (RTC)                            */
S/*                                                                            */
S/******************************************************************************/
S/********************  Bits definition for RTC_TR register  *******************/
S#define RTC_TR_PM                            ((uint32_t)0x00400000)
S#define RTC_TR_HT                            ((uint32_t)0x00300000)
S#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
S#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
S#define RTC_TR_HU                            ((uint32_t)0x000F0000)
S#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
S#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
S#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
S#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
S#define RTC_TR_MNT                           ((uint32_t)0x00007000)
S#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
S#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
S#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
S#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
S#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
S#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
S#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
S#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
S#define RTC_TR_ST                            ((uint32_t)0x00000070)
S#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
S#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
S#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
S#define RTC_TR_SU                            ((uint32_t)0x0000000F)
S#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
S#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
S#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
S#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
S
S/********************  Bits definition for RTC_DR register  *******************/
S#define RTC_DR_YT                            ((uint32_t)0x00F00000)
S#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
S#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
S#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
S#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
S#define RTC_DR_YU                            ((uint32_t)0x000F0000)
S#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
S#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
S#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
S#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
S#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
S#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
S#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
S#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
S#define RTC_DR_MT                            ((uint32_t)0x00001000)
S#define RTC_DR_MU                            ((uint32_t)0x00000F00)
S#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
S#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
S#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
S#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
S#define RTC_DR_DT                            ((uint32_t)0x00000030)
S#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
S#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
S#define RTC_DR_DU                            ((uint32_t)0x0000000F)
S#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
S#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
S#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
S#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
S
S/********************  Bits definition for RTC_CR register  *******************/
S#define RTC_CR_COE                           ((uint32_t)0x00800000)
S#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
S#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
S#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
S#define RTC_CR_POL                           ((uint32_t)0x00100000)
S#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
S#define RTC_CR_BCK                           ((uint32_t)0x00040000)
S#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
S#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
S#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
S#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
S#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
S#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
S#define RTC_CR_TSE                           ((uint32_t)0x00000800)
S#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
S#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
S#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
S#define RTC_CR_DCE                           ((uint32_t)0x00000080)
S#define RTC_CR_FMT                           ((uint32_t)0x00000040)
S#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
S#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
S#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
S#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
S#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
S#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
S#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
S
S/********************  Bits definition for RTC_ISR register  ******************/
S#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
S#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
S#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
S#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
S#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
S#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
S#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
S#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
S#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
S#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
S#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
S#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
S#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
S#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
S#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
S
S/********************  Bits definition for RTC_PRER register  *****************/
S#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
S#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00001FFF)
S
S/********************  Bits definition for RTC_WUTR register  *****************/
S#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
S
S/********************  Bits definition for RTC_CALIBR register  ***************/
S#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
S#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
S
S/********************  Bits definition for RTC_ALRMAR register  ***************/
S#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
S#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
S#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
S#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
S#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
S#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
S#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
S#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
S#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
S#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
S#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
S#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
S#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
S#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
S#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
S#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
S#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
S#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
S#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
S#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
S#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
S#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
S#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
S#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
S#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
S#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
S#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
S#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
S#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
S#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
S#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
S#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
S#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
S#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
S#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
S#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
S#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
S#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
S#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
S#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
S
S/********************  Bits definition for RTC_ALRMBR register  ***************/
S#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
S#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
S#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
S#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
S#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
S#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
S#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
S#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
S#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
S#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
S#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
S#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
S#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
S#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
S#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
S#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
S#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
S#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
S#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
S#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
S#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
S#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
S#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
S#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
S#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
S#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
S#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
S#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
S#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
S#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
S#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
S#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
S#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
S#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
S#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
S#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
S#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
S#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
S#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
S#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
S
S/********************  Bits definition for RTC_WPR register  ******************/
S#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
S
S/********************  Bits definition for RTC_SSR register  ******************/
S#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
S
S/********************  Bits definition for RTC_SHIFTR register  ***************/
S#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
S#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
S
S/********************  Bits definition for RTC_TSTR register  *****************/
S#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
S#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
S#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
S#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
S#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
S#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
S#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
S#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
S#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
S#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
S#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
S#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
S#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
S#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
S#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
S#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
S#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
S#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
S#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
S#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
S#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
S#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
S#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
S#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
S#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
S#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
S#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
S
S/********************  Bits definition for RTC_TSDR register  *****************/
S#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
S#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
S#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
S#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
S#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
S#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
S#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
S#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
S#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
S#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
S#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
S#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
S#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
S#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
S#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
S#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
S#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
S#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
S
S/********************  Bits definition for RTC_TSSSR register  ****************/
S#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
S
S/********************  Bits definition for RTC_CAL register  *****************/
S#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
S#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
S#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
S#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
S#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
S#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
S#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
S#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
S#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
S#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
S#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
S#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
S#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
S
S/********************  Bits definition for RTC_TAFCR register  ****************/
S#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
S#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)
S#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)
S#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
S#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
S#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
S#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
S#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
S#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
S#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
S#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
S#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
S#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
S#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
S#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
S#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
S#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
S#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
S
S/********************  Bits definition for RTC_ALRMASSR register  *************/
S#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
S#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
S#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
S#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
S#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
S#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
S
S/********************  Bits definition for RTC_ALRMBSSR register  *************/
S#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
S#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
S#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
S#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
S#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
S#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
S
S/********************  Bits definition for RTC_BKP0R register  ****************/
S#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP1R register  ****************/
S#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP2R register  ****************/
S#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP3R register  ****************/
S#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP4R register  ****************/
S#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP5R register  ****************/
S#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP6R register  ****************/
S#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP7R register  ****************/
S#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP8R register  ****************/
S#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP9R register  ****************/
S#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP10R register  ***************/
S#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP11R register  ***************/
S#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP12R register  ***************/
S#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP13R register  ***************/
S#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP14R register  ***************/
S#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP15R register  ***************/
S#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP16R register  ***************/
S#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP17R register  ***************/
S#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP18R register  ***************/
S#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
S
S/********************  Bits definition for RTC_BKP19R register  ***************/
S#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
S
S/******************************************************************************/
S/*                                                                            */
S/*                          Serial Audio Interface                            */
S/*                                                                            */
S/******************************************************************************/
S/********************  Bit definition for SAI_GCR register  *******************/
S#define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
S#define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
S
S#define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
S#define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010)        /*!<Bit 0 */
S#define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020)        /*!<Bit 1 */
S
S/*******************  Bit definition for SAI_xCR1 register  *******************/
S#define  SAI_xCR1_MODE                    ((uint32_t)0x00000003)        /*!<MODE[1:0] bits (Audio Block Mode)           */
S#define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S
S#define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000C)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
S#define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004)        /*!<Bit 0 */
S#define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008)        /*!<Bit 1 */
S
S#define  SAI_xCR1_DS                      ((uint32_t)0x000000E0)        /*!<DS[1:0] bits (Data Size) */
S#define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020)        /*!<Bit 0 */
S#define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040)        /*!<Bit 1 */
S#define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080)        /*!<Bit 2 */
S
S#define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100)        /*!<LSB First Configuration  */
S#define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200)        /*!<ClocK STRobing edge      */
S
S#define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00)        /*!<SYNCEN[1:0](SYNChronization ENable) */
S#define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400)        /*!<Bit 0 */
S#define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800)        /*!<Bit 1 */
S
S#define  SAI_xCR1_MONO                    ((uint32_t)0x00001000)        /*!<Mono mode                  */
S#define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000)        /*!<Output Drive               */
S#define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000)        /*!<Audio Block enable         */
S#define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000)        /*!<DMA enable                 */
S#define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000)        /*!<No Divider Configuration   */
S
S#define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00780000)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
S#define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00080000)        /*!<Bit 0  */
S#define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00100000)        /*!<Bit 1  */
S#define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00200000)        /*!<Bit 2  */
S#define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00400000)        /*!<Bit 3  */
S
S/*******************  Bit definition for SAI_xCR2 register  *******************/
S#define  SAI_xCR2_FTH                     ((uint32_t)0x00000003)        /*!<FTH[1:0](Fifo THreshold)  */
S#define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
S
S#define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008)        /*!<Fifo FLUSH                       */
S#define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010)        /*!<TRIState Management on data line */
S#define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020)        /*!<Mute mode                        */
S#define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040)        /*!<Muate value                      */
S
S#define  SAI_xCR2_MUTECNT                  ((uint32_t)0x00001F80)       /*!<MUTECNT[5:0] (MUTE counter) */
S#define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080)        /*!<Bit 0 */
S#define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100)        /*!<Bit 1 */
S#define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200)        /*!<Bit 2 */
S#define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400)        /*!<Bit 3 */
S#define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800)        /*!<Bit 4 */
S#define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000)        /*!<Bit 5 */
S
S#define  SAI_xCR2_CPL                     ((uint32_t)0x00080000)        /*!< Complement Bit             */
S
S#define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000)        /*!<COMP[1:0] (Companding mode) */
S#define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000)        /*!<Bit 0 */
S#define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000)        /*!<Bit 1 */
S
S/******************  Bit definition for SAI_xFRCR register  *******************/
S#define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FF)        /*!<FRL[1:0](Frame length)  */
S#define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
S#define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
S#define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
S#define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
S
S#define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00)        /*!<FRL[1:0] (Frame synchronization active level length)  */
S#define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800)        /*!<Bit 3 */
S#define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000)        /*!<Bit 4 */
S#define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000)        /*!<Bit 5 */
S#define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000)        /*!<Bit 6 */
S
S#define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000)        /*!< Frame Synchronization Definition */
S#define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000)        /*!<Frame Synchronization POLarity    */
S#define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000)        /*!<Frame Synchronization OFFset      */
S
S/******************  Bit definition for SAI_xSLOTR register  *******************/
S#define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001F)        /*!<FRL[4:0](First Bit Offset)  */
S#define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001)        /*!<Bit 0 */
S#define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002)        /*!<Bit 1 */
S#define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004)        /*!<Bit 2 */
S#define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008)        /*!<Bit 3 */
S#define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010)        /*!<Bit 4 */
S                                     
S#define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0)        /*!<SLOTSZ[1:0] (Slot size)  */
S#define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040)        /*!<Bit 0 */
S#define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080)        /*!<Bit 1 */
S
S#define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
S#define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100)        /*!<Bit 0 */
S#define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200)        /*!<Bit 1 */
S#define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400)        /*!<Bit 2 */
S#define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800)        /*!<Bit 3 */
S
S#define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000)        /*!<SLOTEN[15:0] (Slot Enable)  */
S
S/*******************  Bit definition for SAI_xIMR register  *******************/
S#define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001)        /*!<Overrun underrun interrupt enable                              */
S#define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002)        /*!<Mute detection interrupt enable                                */
S#define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004)        /*!<Wrong Clock Configuration interrupt enable                     */
S#define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008)        /*!<FIFO request interrupt enable                                  */
S#define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010)        /*!<Codec not ready interrupt enable                               */
S#define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020)        /*!<Anticipated frame synchronization detection interrupt enable   */
S#define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040)        /*!<Late frame synchronization detection interrupt enable          */
S
S/********************  Bit definition for SAI_xSR register  *******************/
S#define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001)         /*!<Overrun underrun                               */
S#define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002)         /*!<Mute detection                                 */
S#define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004)         /*!<Wrong Clock Configuration                      */
S#define  SAI_xSR_FREQ                     ((uint32_t)0x00000008)         /*!<FIFO request                                   */
S#define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010)         /*!<Codec not ready                                */
S#define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020)         /*!<Anticipated frame synchronization detection    */
S#define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040)         /*!<Late frame synchronization detection           */
S
S#define  SAI_xSR_FLVL                     ((uint32_t)0x00070000)         /*!<FLVL[2:0] (FIFO Level Threshold)               */
S#define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000)         /*!<Bit 0 */
S#define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000)         /*!<Bit 1 */
S#define  SAI_xSR_FLVL_2                   ((uint32_t)0x00030000)         /*!<Bit 2 */
S
S/******************  Bit definition for SAI_xCLRFR register  ******************/
S#define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001)        /*!<Clear Overrun underrun                               */
S#define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002)        /*!<Clear Mute detection                                 */
S#define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004)        /*!<Clear Wrong Clock Configuration                      */
S#define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008)        /*!<Clear FIFO request                                   */
S#define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010)        /*!<Clear Codec not ready                                */
S#define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020)        /*!<Clear Anticipated frame synchronization detection    */
S#define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040)        /*!<Clear Late frame synchronization detection           */
S
S/******************  Bit definition for SAI_xDR register  ******************/
S#define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFF)        
S
S#if defined(STM32F446xx)
S/******************************************************************************/
S/*                                                                            */
S/*                              SPDIF-RX Interface                            */
S/*                                                                            */
S/******************************************************************************/
S/********************  Bit definition for SPDIFRX_CR register  *******************/
S#define  SPDIFRX_CR_SPDIFEN                  ((uint32_t)0x00000003)        /*!<Peripheral Block Enable                      */
S#define  SPDIFRX_CR_RXDMAEN                  ((uint32_t)0x00000004)        /*!<Receiver DMA Enable for data flow            */
S#define  SPDIFRX_CR_RXSTEO                   ((uint32_t)0x00000008)        /*!<Stereo Mode                                  */
S#define  SPDIFRX_CR_DRFMT                    ((uint32_t)0x00000030)        /*!<RX Data format                               */
S#define  SPDIFRX_CR_PMSK                     ((uint32_t)0x00000040)        /*!<Mask Parity error bit                        */
S#define  SPDIFRX_CR_VMSK                     ((uint32_t)0x00000080)        /*!<Mask of Validity bit                         */
S#define  SPDIFRX_CR_CUMSK                    ((uint32_t)0x00000100)        /*!<Mask of channel status and user bits         */
S#define  SPDIFRX_CR_PTMSK                    ((uint32_t)0x00000200)        /*!<Mask of Preamble Type bits                   */
S#define  SPDIFRX_CR_CBDMAEN                  ((uint32_t)0x00000400)        /*!<Control Buffer DMA ENable for control flow   */
S#define  SPDIFRX_CR_CHSEL                    ((uint32_t)0x00000800)        /*!<Channel Selection                            */
S#define  SPDIFRX_CR_NBTR                     ((uint32_t)0x00003000)        /*!<Maximum allowed re-tries during synchronization phase */
S#define  SPDIFRX_CR_WFA                      ((uint32_t)0x00004000)        /*!<Wait For Activity     */
S#define  SPDIFRX_CR_INSEL                    ((uint32_t)0x00070000)        /*!<SPDIFRX input selection */
S
S/*******************  Bit definition for SPDIFRX_IMR register  *******************/
S#define  SPDIFRX_IMR_RXNEIE                   ((uint32_t)0x00000001)        /*!<RXNE interrupt enable                              */
S#define  SPDIFRX_IMR_CSRNEIE                  ((uint32_t)0x00000002)        /*!<Control Buffer Ready Interrupt Enable              */
S#define  SPDIFRX_IMR_PERRIE                   ((uint32_t)0x00000004)        /*!<Parity error interrupt enable                      */
S#define  SPDIFRX_IMR_OVRIE                    ((uint32_t)0x00000008)        /*!<Overrun error Interrupt Enable                     */
S#define  SPDIFRX_IMR_SBLKIE                   ((uint32_t)0x00000010)        /*!<Synchronization Block Detected Interrupt Enable    */
S#define  SPDIFRX_IMR_SYNCDIE                  ((uint32_t)0x00000020)        /*!<Synchronization Done                               */
S#define  SPDIFRX_IMR_IFEIE                    ((uint32_t)0x00000040)        /*!<Serial Interface Error Interrupt Enable            */
S
S/*******************  Bit definition for SPDIFRX_SR register  *******************/
S#define  SPDIFRX_SR_RXNE                   ((uint32_t)0x00000001)       /*!<Read data register not empty                          */
S#define  SPDIFRX_SR_CSRNE                  ((uint32_t)0x00000002)       /*!<The Control Buffer register is not empty              */
S#define  SPDIFRX_SR_PERR                   ((uint32_t)0x00000004)       /*!<Parity error                                          */
S#define  SPDIFRX_SR_OVR                    ((uint32_t)0x00000008)       /*!<Overrun error                                         */
S#define  SPDIFRX_SR_SBD                    ((uint32_t)0x00000010)       /*!<Synchronization Block Detected                        */
S#define  SPDIFRX_SR_SYNCD                  ((uint32_t)0x00000020)       /*!<Synchronization Done                                  */
S#define  SPDIFRX_SR_FERR                   ((uint32_t)0x00000040)       /*!<Framing error                                         */
S#define  SPDIFRX_SR_SERR                   ((uint32_t)0x00000080)       /*!<Synchronization error                                 */
S#define  SPDIFRX_SR_TERR                   ((uint32_t)0x00000100)       /*!<Time-out error                                        */
S#define  SPDIFRX_SR_WIDTH5                 ((uint32_t)0x7FFF0000)       /*!<Duration of 5 symbols counted with SPDIFRX_clk        */
S
S/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
S#define  SPDIFRX_IFCR_PERRCF               ((uint32_t)0x00000004)       /*!<Clears the Parity error flag                         */
S#define  SPDIFRX_IFCR_OVRCF                ((uint32_t)0x00000008)       /*!<Clears the Overrun error flag                        */
S#define  SPDIFRX_IFCR_SBDCF                ((uint32_t)0x00000010)       /*!<Clears the Synchronization Block Detected flag       */
S#define  SPDIFRX_IFCR_SYNCDCF              ((uint32_t)0x00000020)       /*!<Clears the Synchronization Done flag                 */
S
S/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
S#define  SPDIFRX_DR0_DR                    ((uint32_t)0x00FFFFFF)        /*!<Data value            */
S#define  SPDIFRX_DR0_PE                    ((uint32_t)0x01000000)        /*!<Parity Error bit      */
S#define  SPDIFRX_DR0_V                     ((uint32_t)0x02000000)        /*!<Validity bit          */
S#define  SPDIFRX_DR0_U                     ((uint32_t)0x04000000)        /*!<User bit              */
S#define  SPDIFRX_DR0_C                     ((uint32_t)0x08000000)        /*!<Channel Status bit    */
S#define  SPDIFRX_DR0_PT                    ((uint32_t)0x30000000)        /*!<Preamble Type         */
S
S/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
S#define  SPDIFRX_DR1_DR                    ((uint32_t)0xFFFFFF00)        /*!<Data value            */
S#define  SPDIFRX_DR1_PT                    ((uint32_t)0x00000030)        /*!<Preamble Type         */
S#define  SPDIFRX_DR1_C                     ((uint32_t)0x00000008)        /*!<Channel Status bit    */
S#define  SPDIFRX_DR1_U                     ((uint32_t)0x00000004)        /*!<User bit              */
S#define  SPDIFRX_DR1_V                     ((uint32_t)0x00000002)        /*!<Validity bit          */
S#define  SPDIFRX_DR1_PE                    ((uint32_t)0x00000001)        /*!<Parity Error bit      */
S
S/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
S#define  SPDIFRX_DR1_DRNL1                 ((uint32_t)0xFFFF0000)        /*!<Data value Channel B      */
S#define  SPDIFRX_DR1_DRNL2                 ((uint32_t)0x0000FFFF)        /*!<Data value Channel A      */
S
S/*******************  Bit definition for SPDIFRX_CSR register   *******************/
S#define  SPDIFRX_CSR_USR                     ((uint32_t)0x0000FFFF)        /*!<User data information           */
S#define  SPDIFRX_CSR_CS                      ((uint32_t)0x00FF0000)        /*!<Channel A status information    */
S#define  SPDIFRX_CSR_SOB                     ((uint32_t)0x01000000)        /*!<Start Of Block                  */
S
S/*******************  Bit definition for SPDIFRX_DIR register    *******************/
S#define  SPDIFRX_DIR_THI                 ((uint32_t)0x000013FF)        /*!<Threshold LOW      */
S#define  SPDIFRX_DIR_TLO                 ((uint32_t)0x1FFF0000)        /*!<Threshold HIGH     */
S#endif /* STM32F446xx */
S
S/******************************************************************************/
S/*                                                                            */
S/*                          SD host Interface                                 */
S/*                                                                            */
S/******************************************************************************/
S/******************  Bit definition for SDIO_POWER register  ******************/
S#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
S#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!<Bit 0 */
S#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!<Bit 1 */
S
S/******************  Bit definition for SDIO_CLKCR register  ******************/
S#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!<Clock divide factor             */
S#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!<Clock enable bit                */
S#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!<Power saving configuration bit  */
S#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!<Clock divider bypass enable bit */
S
S#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
S#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!<Bit 0 */
S#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!<Bit 1 */
S
S#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!<SDIO_CK dephasing selection bit */
S#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!<HW Flow Control enable          */
S
S/*******************  Bit definition for SDIO_ARG register  *******************/
S#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */
S
S/*******************  Bit definition for SDIO_CMD register  *******************/
S#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!<Command Index                               */
S
S#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
S#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!< Bit 0 */
S#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!< Bit 1 */
S
S#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!<CPSM Waits for Interrupt Request                               */
S#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
S#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit                   */
S#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!<SD I/O suspend command                                         */
S#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!<Enable CMD completion                                          */
S#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!<Not Interrupt Enable */
S#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!<CE-ATA command       */
S
S/*****************  Bit definition for SDIO_RESPCMD register  *****************/
S#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!<Response command index */
S
S/******************  Bit definition for SDIO_RESP0 register  ******************/
S#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
S
S/******************  Bit definition for SDIO_RESP1 register  ******************/
S#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
S
S/******************  Bit definition for SDIO_RESP2 register  ******************/
S#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
S
S/******************  Bit definition for SDIO_RESP3 register  ******************/
S#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
S
S/******************  Bit definition for SDIO_RESP4 register  ******************/
S#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
S
S/******************  Bit definition for SDIO_DTIMER register  *****************/
S#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */
S
S/******************  Bit definition for SDIO_DLEN register  *******************/
S#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value    */
S
S/******************  Bit definition for SDIO_DCTRL register  ******************/
S#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!<Data transfer enabled bit         */
S#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!<Data transfer direction selection */
S#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!<Data transfer mode selection      */
S#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!<DMA enabled bit                   */
S
S#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
S#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!<Bit 0 */
S#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!<Bit 1 */
S#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!<Bit 2 */
S#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!<Bit 3 */
S
S#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!<Read wait start         */
S#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!<Read wait stop          */
S#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!<Read wait mode          */
S#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!<SD I/O enable functions */
S
S/******************  Bit definition for SDIO_DCOUNT register  *****************/
S#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */
S
S/******************  Bit definition for SDIO_STA register  ********************/
S#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed)  */
S#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed)   */
S#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout                      */
S#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout                                  */
S#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error                  */
S#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error                   */
S#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed)  */
S#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required)           */
S#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
S#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!<Start bit not detected on all data signals in wide bus mode */
S#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed)   */
S#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress                  */
S#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress                     */
S#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress                      */
S#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
S#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
S#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full                            */
S#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full                             */
S#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty                           */
S#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty                            */
S#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO               */
S#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO                */
S#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDIO interrupt received                       */
S#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received for CMD61 */
S
S/*******************  Bit definition for SDIO_ICR register  *******************/
S#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */
S#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */
S#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */
S#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */
S#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */
S#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit  */
S#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit  */
S#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit  */
S#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit  */
S#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!<STBITERR flag clear bit */
S#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit  */
S#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDIOIT flag clear bit   */
S#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!<CEATAEND flag clear bit */
S
S/******************  Bit definition for SDIO_MASK register  *******************/
S#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable          */
S#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable             */
S#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable           */
S#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable              */
S#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
S#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
S#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */
S#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable              */
S#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable                  */
S#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!<Start Bit Error Interrupt Enable           */
S#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable            */
S#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable           */
S#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable      */
S#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled      */
S#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable        */
S#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable         */
S#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable              */
S#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable              */
S#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable             */
S#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable             */
S#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */
S#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */
S#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDIO Mode Interrupt Received interrupt Enable */
S#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received Interrupt Enable */
S
S/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
S#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */
S
S/******************  Bit definition for SDIO_FIFO register  *******************/
S#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */
S
S/******************************************************************************/
S/*                                                                            */
S/*                        Serial Peripheral Interface                         */
S/*                                                                            */
S/******************************************************************************/
S/*******************  Bit definition for SPI_CR1 register  ********************/
S#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!<Clock Phase      */
S#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!<Clock Polarity   */
S#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!<Master Selection */
S
S#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!<BR[2:0] bits (Baud Rate Control) */
S#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!<Bit 0 */
S#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!<Bit 1 */
S#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!<Bit 2 */
S
S#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!<SPI Enable                          */
S#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!<Frame Format                        */
S#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!<Internal slave select               */
S#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!<Software slave management           */
S#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!<Receive only                        */
S#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!<Data Frame Format                   */
S#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!<Transmit CRC next                   */
S#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!<Hardware CRC calculation enable     */
S#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!<Output enable in bidirectional mode */
S#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!<Bidirectional data mode enable      */
S
S/*******************  Bit definition for SPI_CR2 register  ********************/
S#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!<Rx Buffer DMA Enable                 */
S#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!<Tx Buffer DMA Enable                 */
S#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!<SS Output Enable                     */
S#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!<Error Interrupt Enable               */
S#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!<RX buffer Not Empty Interrupt Enable */
S#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!<Tx buffer Empty Interrupt Enable     */
S
S/********************  Bit definition for SPI_SR register  ********************/
S#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!<Receive buffer Not Empty */
S#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!<Transmit buffer Empty    */
S#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!<Channel side             */
S#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!<Underrun flag            */
S#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!<CRC Error flag           */
S#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!<Mode fault               */
S#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!<Overrun flag             */
S#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!<Busy flag                */
S
S/********************  Bit definition for SPI_DR register  ********************/
S#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!<Data Register           */
S
S/*******************  Bit definition for SPI_CRCPR register  ******************/
S#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!<CRC polynomial register */
S
S/******************  Bit definition for SPI_RXCRCR register  ******************/
S#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!<Rx CRC Register         */
S
S/******************  Bit definition for SPI_TXCRCR register  ******************/
S#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!<Tx CRC Register         */
S
S/******************  Bit definition for SPI_I2SCFGR register  *****************/
S#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
S
S#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
S#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
S#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
S
S#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity               */
S
S#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
S#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
S#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
S
S#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization                 */
S
S#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
S#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
S#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
S
S#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable         */
S#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
S
S/******************  Bit definition for SPI_I2SPR register  *******************/
S#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler         */
S#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
S#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable   */
S
S/******************************************************************************/
S/*                                                                            */
S/*                                 SYSCFG                                     */
S/*                                                                            */
S/******************************************************************************/
S/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
S#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
S#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!<Bit 0 */
S#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!<Bit 1 */
S#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004) /*!<Bit 2 */
S
S#define SYSCFG_MEMRMP_FB_MODE           ((uint32_t)0x00000100) /*!< User Flash Bank mode */
S
S#define SYSCFG_MEMRMP_SWP_FMC           ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
S#define SYSCFG_MEMRMP_SWP_FMC_0         ((uint32_t)0x00000400) /*!<Bit 0 */
S#define SYSCFG_MEMRMP_SWP_FMC_1         ((uint32_t)0x00000800) /*!<Bit 1 */
S
S
S/******************  Bit definition for SYSCFG_PMC register  ******************/
S#define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit  */
S#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */
S#define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit  */
S#define SYSCFG_PMC_ADC3DC2              ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit  */
S
S#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
S/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
S#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
S
S/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
S#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!<EXTI 0 configuration */
S#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
S#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
S#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!<EXTI 3 configuration */
S/** 
S  * @brief   EXTI0 configuration  
S  */ 
S#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!<PA[0] pin */
S#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!<PB[0] pin */
S#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!<PC[0] pin */
S#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!<PD[0] pin */
S#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!<PE[0] pin */
S#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!<PF[0] pin */
S#define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0006) /*!<PG[0] pin */
S#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0007) /*!<PH[0] pin */
S#define SYSCFG_EXTICR1_EXTI0_PI         ((uint16_t)0x0008) /*!<PI[0] pin */
S#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint16_t)0x0009) /*!<PJ[0] pin */
S#define SYSCFG_EXTICR1_EXTI0_PK         ((uint16_t)0x000A) /*!<PK[0] pin */
S
S/** 
S  * @brief   EXTI1 configuration  
S  */ 
S#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!<PA[1] pin */
S#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!<PB[1] pin */
S#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!<PC[1] pin */
S#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!<PD[1] pin */
S#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!<PE[1] pin */
S#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!<PF[1] pin */
S#define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0060) /*!<PG[1] pin */
S#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0070) /*!<PH[1] pin */
S#define SYSCFG_EXTICR1_EXTI1_PI         ((uint16_t)0x0080) /*!<PI[1] pin */
S#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint16_t)0x0090) /*!<PJ[1] pin */
S#define SYSCFG_EXTICR1_EXTI1_PK         ((uint16_t)0x00A0) /*!<PK[1] pin */
S
S/** 
S  * @brief   EXTI2 configuration  
S  */ 
S#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!<PA[2] pin */
S#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!<PB[2] pin */
S#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!<PC[2] pin */
S#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!<PD[2] pin */
S#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!<PE[2] pin */
S#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!<PF[2] pin */
S#define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0600) /*!<PG[2] pin */
S#define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0700) /*!<PH[2] pin */
S#define SYSCFG_EXTICR1_EXTI2_PI         ((uint16_t)0x0800) /*!<PI[2] pin */
S#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint16_t)0x0900) /*!<PJ[2] pin */
S#define SYSCFG_EXTICR1_EXTI2_PK         ((uint16_t)0x0A00) /*!<PK[2] pin */
S
S/** 
S  * @brief   EXTI3 configuration  
S  */ 
S#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!<PA[3] pin */
S#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!<PB[3] pin */
S#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!<PC[3] pin */
S#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!<PD[3] pin */
S#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!<PE[3] pin */
S#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!<PF[3] pin */
S#define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x6000) /*!<PG[3] pin */
S#define SYSCFG_EXTICR1_EXTI3_PH         ((uint16_t)0x7000) /*!<PH[3] pin */
S#define SYSCFG_EXTICR1_EXTI3_PI         ((uint16_t)0x8000) /*!<PI[3] pin */
S#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint16_t)0x9000) /*!<PJ[3] pin */
S#define SYSCFG_EXTICR1_EXTI3_PK         ((uint16_t)0xA000) /*!<PK[3] pin */
S
S/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
S#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!<EXTI 4 configuration */
S#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
S#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
S#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!<EXTI 7 configuration */
S/** 
S  * @brief   EXTI4 configuration  
S  */ 
S#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!<PA[4] pin */
S#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!<PB[4] pin */
S#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!<PC[4] pin */
S#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!<PD[4] pin */
S#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!<PE[4] pin */
S#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!<PF[4] pin */
S#define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0006) /*!<PG[4] pin */
S#define SYSCFG_EXTICR2_EXTI4_PH         ((uint16_t)0x0007) /*!<PH[4] pin */
S#define SYSCFG_EXTICR2_EXTI4_PI         ((uint16_t)0x0008) /*!<PI[4] pin */
S#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint16_t)0x0009) /*!<PJ[4] pin */
S#define SYSCFG_EXTICR2_EXTI4_PK         ((uint16_t)0x000A) /*!<PK[4] pin */
S
S/** 
S  * @brief   EXTI5 configuration  
S  */ 
S#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!<PA[5] pin */
S#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!<PB[5] pin */
S#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!<PC[5] pin */
S#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!<PD[5] pin */
S#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!<PE[5] pin */
S#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!<PF[5] pin */
S#define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0060) /*!<PG[5] pin */
S#define SYSCFG_EXTICR2_EXTI5_PH         ((uint16_t)0x0070) /*!<PH[5] pin */
S#define SYSCFG_EXTICR2_EXTI5_PI         ((uint16_t)0x0080) /*!<PI[5] pin */
S#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint16_t)0x0090) /*!<PJ[5] pin */
S#define SYSCFG_EXTICR2_EXTI5_PK         ((uint16_t)0x00A0) /*!<PK[5] pin */
S
S/** 
S  * @brief   EXTI6 configuration  
S  */ 
S#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!<PA[6] pin */
S#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!<PB[6] pin */
S#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!<PC[6] pin */
S#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!<PD[6] pin */
S#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!<PE[6] pin */
S#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!<PF[6] pin */
S#define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0600) /*!<PG[6] pin */
S#define SYSCFG_EXTICR2_EXTI6_PH         ((uint16_t)0x0700) /*!<PH[6] pin */
S#define SYSCFG_EXTICR2_EXTI6_PI         ((uint16_t)0x0800) /*!<PI[6] pin */
S#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint16_t)0x0900) /*!<PJ[6] pin */
S#define SYSCFG_EXTICR2_EXTI6_PK         ((uint16_t)0x0A00) /*!<PK[6] pin */
S
S/** 
S  * @brief   EXTI7 configuration  
S  */ 
S#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!<PA[7] pin */
S#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!<PB[7] pin */
S#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!<PC[7] pin */
S#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!<PD[7] pin */
S#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!<PE[7] pin */
S#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!<PF[7] pin */
S#define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x6000) /*!<PG[7] pin */
S#define SYSCFG_EXTICR2_EXTI7_PH         ((uint16_t)0x7000) /*!<PH[7] pin */
S#define SYSCFG_EXTICR2_EXTI7_PI         ((uint16_t)0x8000) /*!<PI[7] pin */
S#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint16_t)0x9000) /*!<PJ[7] pin */
S#define SYSCFG_EXTICR2_EXTI7_PK         ((uint16_t)0xA000) /*!<PK[7] pin */
S
S/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
S#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!<EXTI 8 configuration */
S#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
S#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
S#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!<EXTI 11 configuration */
S           
S/** 
S  * @brief   EXTI8 configuration  
S  */ 
S#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!<PA[8] pin */
S#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!<PB[8] pin */
S#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!<PC[8] pin */
S#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!<PD[8] pin */
S#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!<PE[8] pin */
S#define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0005) /*!<PF[8] pin */
S#define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0006) /*!<PG[8] pin */
S#define SYSCFG_EXTICR3_EXTI8_PH         ((uint16_t)0x0007) /*!<PH[8] pin */
S#define SYSCFG_EXTICR3_EXTI8_PI         ((uint16_t)0x0008) /*!<PI[8] pin */
S#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint16_t)0x0009) /*!<PJ[8] pin */
S
S/** 
S  * @brief   EXTI9 configuration  
S  */ 
S#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!<PA[9] pin */
S#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!<PB[9] pin */
S#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!<PC[9] pin */
S#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!<PD[9] pin */
S#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!<PE[9] pin */
S#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!<PF[9] pin */
S#define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0060) /*!<PG[9] pin */
S#define SYSCFG_EXTICR3_EXTI9_PH         ((uint16_t)0x0070) /*!<PH[9] pin */
S#define SYSCFG_EXTICR3_EXTI9_PI         ((uint16_t)0x0080) /*!<PI[9] pin */
S#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint16_t)0x0090) /*!<PJ[9] pin */
S
S/** 
S  * @brief   EXTI10 configuration  
S  */ 
S#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!<PA[10] pin */
S#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!<PB[10] pin */
S#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!<PC[10] pin */
S#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!<PD[10] pin */
S#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!<PE[10] pin */
S#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!<PF[10] pin */
S#define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0600) /*!<PG[10] pin */
S#define SYSCFG_EXTICR3_EXTI10_PH        ((uint16_t)0x0700) /*!<PH[10] pin */
S#define SYSCFG_EXTICR3_EXTI10_PI        ((uint16_t)0x0800) /*!<PI[10] pin */
S#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint16_t)0x0900) /*!<PJ[10] pin */
S
S/** 
S  * @brief   EXTI11 configuration  
S  */ 
S#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!<PA[11] pin */
S#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!<PB[11] pin */
S#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!<PC[11] pin */
S#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!<PD[11] pin */
S#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!<PE[11] pin */
S#define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x5000) /*!<PF[11] pin */
S#define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x6000) /*!<PG[11] pin */
S#define SYSCFG_EXTICR3_EXTI11_PH        ((uint16_t)0x7000) /*!<PH[11] pin */
S#define SYSCFG_EXTICR3_EXTI11_PI        ((uint16_t)0x8000) /*!<PI[11] pin */
S#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint16_t)0x9000) /*!<PJ[11] pin */
S
S/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
S#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!<EXTI 12 configuration */
S#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
S#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
S#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!<EXTI 15 configuration */
S/** 
S  * @brief   EXTI12 configuration  
S  */ 
S#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!<PA[12] pin */
S#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!<PB[12] pin */
S#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!<PC[12] pin */
S#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!<PD[12] pin */
S#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!<PE[12] pin */
S#define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0005) /*!<PF[12] pin */
S#define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0006) /*!<PG[12] pin */
S#define SYSCFG_EXTICR4_EXTI12_PH        ((uint16_t)0x0007) /*!<PH[12] pin */
S#define SYSCFG_EXTICR4_EXTI12_PI        ((uint16_t)0x0008) /*!<PI[12] pin */
S#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint16_t)0x0009) /*!<PJ[12] pin */
S
S/** 
S  * @brief   EXTI13 configuration  
S  */ 
S#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!<PA[13] pin */
S#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!<PB[13] pin */
S#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!<PC[13] pin */
S#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!<PD[13] pin */
S#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!<PE[13] pin */
S#define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0050) /*!<PF[13] pin */
S#define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0060) /*!<PG[13] pin */
S#define SYSCFG_EXTICR4_EXTI13_PH        ((uint16_t)0x0070) /*!<PH[13] pin */
S#define SYSCFG_EXTICR4_EXTI13_PI        ((uint16_t)0x0008) /*!<PI[13] pin */
S#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint16_t)0x0009) /*!<PJ[13] pin */
S
S/** 
S  * @brief   EXTI14 configuration  
S  */ 
S#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!<PA[14] pin */
S#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!<PB[14] pin */
S#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!<PC[14] pin */
S#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!<PD[14] pin */
S#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!<PE[14] pin */
S#define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0500) /*!<PF[14] pin */
S#define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0600) /*!<PG[14] pin */
S#define SYSCFG_EXTICR4_EXTI14_PH        ((uint16_t)0x0700) /*!<PH[14] pin */
S#define SYSCFG_EXTICR4_EXTI14_PI        ((uint16_t)0x0800) /*!<PI[14] pin */
S#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint16_t)0x0900) /*!<PJ[14] pin */
S
S/** 
S  * @brief   EXTI15 configuration  
S  */ 
S#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!<PA[15] pin */
S#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!<PB[15] pin */
S#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!<PC[15] pin */
S#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!<PD[15] pin */
S#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!<PE[15] pin */
S#define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x5000) /*!<PF[15] pin */
S#define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x6000) /*!<PG[15] pin */
S#define SYSCFG_EXTICR4_EXTI15_PH        ((uint16_t)0x7000) /*!<PH[15] pin */
S#define SYSCFG_EXTICR4_EXTI15_PI        ((uint16_t)0x8000) /*!<PI[15] pin */
S#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint16_t)0x9000) /*!<PJ[15] pin */
S
S/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
S#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
S#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */
S
S/******************************************************************************/
S/*                                                                            */
S/*                                    TIM                                     */
S/*                                                                            */
S/******************************************************************************/
S/*******************  Bit definition for TIM_CR1 register  ********************/
S#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable        */
S#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable        */
S#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
S#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode        */
S#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction             */
S
S#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
S#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
S#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
S
S#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable     */
S
S#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
S#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
S#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
S
S/*******************  Bit definition for TIM_CR2 register  ********************/
S#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control        */
S#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
S#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection            */
S
S#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
S#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
S#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
S#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
S
S#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
S#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output)  */
S#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
S#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output)  */
S#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
S#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output)  */
S#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
S#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output)  */
S
S/*******************  Bit definition for TIM_SMCR register  *******************/
S#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection)    */
S#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
S#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
S#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
S
S#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection)        */
S#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
S#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
S#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
S
S#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode                       */
S
S#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
S#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
S#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
S#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
S#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
S
S#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
S#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
S#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
S
S#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable     */
S#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
S
S/*******************  Bit definition for TIM_DIER register  *******************/
S#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
S#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable   */
S#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable   */
S#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable   */
S#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable   */
S#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable                 */
S#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable             */
S#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable               */
S#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable            */
S#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
S#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
S#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
S#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
S#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable               */
S#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable           */
S
S/********************  Bit definition for TIM_SR register  ********************/
S#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag              */
S#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag   */
S#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag   */
S#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag   */
S#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag   */
S#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag                 */
S#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag             */
S#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag               */
S#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
S#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
S#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
S#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
S
S/*******************  Bit definition for TIM_EGR register  ********************/
S#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation                         */
S#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation              */
S#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation              */
S#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation              */
S#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation              */
S#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
S#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation                        */
S#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation                          */
S
S/******************  Bit definition for TIM_CCMR1 register  *******************/
S#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
S#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
S#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
S
S#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable                 */
S#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable              */
S
S#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
S#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
S#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
S#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
S
S#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable                 */
S
S#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
S#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
S#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
S
S#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable                 */
S#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable              */
S
S#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
S#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
S#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
S#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
S
S#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
S
S/*----------------------------------------------------------------------------*/
S
S#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
S#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
S#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
S
S#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
S#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
S#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
S#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
S#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
S
S#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
S#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
S#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
S
S#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
S#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
S#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
S#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
S#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
S
S/******************  Bit definition for TIM_CCMR2 register  *******************/
S#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
S#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
S#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
S
S#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable           */
S#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable        */
S
S#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
S#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
S#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
S#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
S
S#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
S
S#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
S#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
S#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
S
S#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable    */
S#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
S
S#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
S#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
S#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
S#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
S
S#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
S
S/*----------------------------------------------------------------------------*/
S
S#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
S#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
S#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
S
S#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
S#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
S#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
S#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
S#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
S
S#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
S#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
S#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
S
S#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
S#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
S#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
S#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
S#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
S
S/*******************  Bit definition for TIM_CCER register  *******************/
S#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable                 */
S#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity               */
S#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable   */
S#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
S#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable                 */
S#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity               */
S#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable   */
S#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
S#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable                 */
S#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity               */
S#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable   */
S#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
S#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable                 */
S#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity               */
S#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
S
S/*******************  Bit definition for TIM_CNT register  ********************/
S#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value            */
S
S/*******************  Bit definition for TIM_PSC register  ********************/
S#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value          */
S
S/*******************  Bit definition for TIM_ARR register  ********************/
S#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
S
S/*******************  Bit definition for TIM_RCR register  ********************/
S#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
S
S/*******************  Bit definition for TIM_CCR1 register  *******************/
S#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value  */
S
S/*******************  Bit definition for TIM_CCR2 register  *******************/
S#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value  */
S
S/*******************  Bit definition for TIM_CCR3 register  *******************/
S#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value  */
S
S/*******************  Bit definition for TIM_CCR4 register  *******************/
S#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value  */
S
S/*******************  Bit definition for TIM_BDTR register  *******************/
S#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
S#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
S#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
S#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
S#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
S#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
S#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
S#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
S#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
S
S#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
S#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
S#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
S
S#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
S#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode  */
S#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable                      */
S#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity                    */
S#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable           */
S#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable                */
S
S/*******************  Bit definition for TIM_DCR register  ********************/
S#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
S#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
S#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
S#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
S#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
S#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
S
S#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
S#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
S#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
S#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
S#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
S#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
S
S/*******************  Bit definition for TIM_DMAR register  *******************/
S#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses                    */
S
S/*******************  Bit definition for TIM_OR register  *********************/
S#define TIM_OR_TI4_RMP                       ((uint16_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
S#define TIM_OR_TI4_RMP_0                     ((uint16_t)0x0040)            /*!<Bit 0 */
S#define TIM_OR_TI4_RMP_1                     ((uint16_t)0x0080)            /*!<Bit 1 */
S#define TIM_OR_ITR1_RMP                      ((uint16_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
S#define TIM_OR_ITR1_RMP_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
S#define TIM_OR_ITR1_RMP_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
S
S
S/******************************************************************************/
S/*                                                                            */
S/*         Universal Synchronous Asynchronous Receiver Transmitter            */
S/*                                                                            */
S/******************************************************************************/
S/*******************  Bit definition for USART_SR register  *******************/
S#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!<Parity Error                 */
S#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!<Framing Error                */
S#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!<Noise Error Flag             */
S#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!<OverRun Error                */
S#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!<IDLE line detected           */
S#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!<Read Data Register Not Empty */
S#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!<Transmission Complete        */
S#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!<Transmit Data Register Empty */
S#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!<LIN Break Detection Flag     */
S#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!<CTS Flag                     */
S
S/*******************  Bit definition for USART_DR register  *******************/
S#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!<Data value */
S
S/******************  Bit definition for USART_BRR register  *******************/
S#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!<Fraction of USARTDIV */
S#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!<Mantissa of USARTDIV */
S
S/******************  Bit definition for USART_CR1 register  *******************/
S#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!<Send Break                             */
S#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!<Receiver wakeup                        */
S#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!<Receiver Enable                        */
S#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!<Transmitter Enable                     */
S#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!<IDLE Interrupt Enable                  */
S#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!<RXNE Interrupt Enable                  */
S#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
S#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!<PE Interrupt Enable                    */
S#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!<PE Interrupt Enable                    */
S#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!<Parity Selection                       */
S#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!<Parity Control Enable                  */
S#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!<Wakeup method                          */
S#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!<Word length                            */
S#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!<USART Enable                           */
S#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!<USART Oversampling by 8 enable         */
S
S/******************  Bit definition for USART_CR2 register  *******************/
S#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!<Address of the USART node            */
S#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!<LIN Break Detection Length           */
S#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
S#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!<Last Bit Clock pulse                 */
S#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!<Clock Phase                          */
S#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!<Clock Polarity                       */
S#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!<Clock Enable                         */
S
S#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
S#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
S#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
S
S#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!<LIN mode enable */
S
S/******************  Bit definition for USART_CR3 register  *******************/
S#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!<Error Interrupt Enable      */
S#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!<IrDA mode Enable            */
S#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!<IrDA Low-Power              */
S#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!<Half-Duplex Selection       */
S#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!<Smartcard NACK enable       */
S#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!<Smartcard mode enable       */
S#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!<DMA Enable Receiver         */
S#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!<DMA Enable Transmitter      */
S#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!<RTS Enable                  */
S#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!<CTS Enable                  */
S#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!<CTS Interrupt Enable        */
S#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!<USART One bit method enable */
S
S/******************  Bit definition for USART_GTPR register  ******************/
S#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
S#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
S#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
S#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!<Bit 2 */
S#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!<Bit 3 */
S#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!<Bit 4 */
S#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!<Bit 5 */
S#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!<Bit 6 */
S#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!<Bit 7 */
S
S#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!<Guard time value */
S
S/******************************************************************************/
S/*                                                                            */
S/*                            Window WATCHDOG                                 */
S/*                                                                            */
S/******************************************************************************/
S/*******************  Bit definition for WWDG_CR register  ********************/
S#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
S#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
S#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
S#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
S#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
S#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
S#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
S#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
S
S#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
S
S/*******************  Bit definition for WWDG_CFR register  *******************/
S#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
S#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
S#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
S#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
S#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
S#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
S#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
S#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
S
S#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
S#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
S#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
S
S#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
S
S/*******************  Bit definition for WWDG_SR register  ********************/
S#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
S
S
S/******************************************************************************/
S/*                                                                            */
S/*                                DBG                                         */
S/*                                                                            */
S/******************************************************************************/
S/********************  Bit definition for DBGMCU_IDCODE register  *************/
S#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
S#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
S
S/********************  Bit definition for DBGMCU_CR register  *****************/
S#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
S#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
S#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
S#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
S
S#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
S#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
S#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
S
S/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
S#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001)
S#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002)
S#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004)
S#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)
S#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)
S#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020)
S#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040)
S#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080)
S#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100)
S#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)
S#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)
S#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)
S#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
S#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
S#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
S#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
S#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
S/* Old IWDGSTOP bit definition, maintained for legacy purpose */
S#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
S
S/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
S#define  DBGMCU_APB1_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
S#define  DBGMCU_APB1_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
S#define  DBGMCU_APB1_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
S#define  DBGMCU_APB1_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)
S#define  DBGMCU_APB1_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
S
S/******************************************************************************/
S/*                                                                            */
S/*                Ethernet MAC Registers bits definitions                     */
S/*                                                                            */
S/******************************************************************************/
S/* Bit definition for Ethernet MAC Control Register register */
S#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
S#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
S#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
S#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
S  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
S  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
S  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
S  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
S  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
S  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
S  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
S#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
S#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
S#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
S#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
S#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
S#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
S#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
S#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
S#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
S                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
S  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
S  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
S  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
S  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
S#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
S#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
S#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
S
S/* Bit definition for Ethernet MAC Frame Filter Register */
S#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
S#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
S#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
S#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
S#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
S  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
S  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
S  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
S#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
S#define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
S#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
S#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
S#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
S#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
S
S/* Bit definition for Ethernet MAC Hash Table High Register */
S#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
S
S/* Bit definition for Ethernet MAC Hash Table Low Register */
S#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
S
S/* Bit definition for Ethernet MAC MII Address Register */
S#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
S#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
S#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
S  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
S  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
S  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
S  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
S  #define ETH_MACMIIAR_CR_Div102  ((uint32_t)0x00000010)  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
S#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
S#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
S  
S/* Bit definition for Ethernet MAC MII Data Register */
S#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
S
S/* Bit definition for Ethernet MAC Flow Control Register */
S#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
S#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
S#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
S  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
S  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
S  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
S  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
S#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
S#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
S#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
S#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
S
S/* Bit definition for Ethernet MAC VLAN Tag Register */
S#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
S#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
S
S/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
S#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
S/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
S   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
S/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
S   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
S   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
S   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
S   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
S                              RSVD - Filter1 Command - RSVD - Filter0 Command
S   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
S   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
S   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
S
S/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
S#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
S#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
S#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
S#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
S#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
S#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
S#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
S
S/* Bit definition for Ethernet MAC Status Register */
S#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
S#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
S#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
S#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
S#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
S
S/* Bit definition for Ethernet MAC Interrupt Mask Register */
S#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
S#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
S
S/* Bit definition for Ethernet MAC Address0 High Register */
S#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
S
S/* Bit definition for Ethernet MAC Address0 Low Register */
S#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
S
S/* Bit definition for Ethernet MAC Address1 High Register */
S#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
S#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
S#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
S  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
S  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
S  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
S  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
S  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
S  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
S#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
S
S/* Bit definition for Ethernet MAC Address1 Low Register */
S#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
S
S/* Bit definition for Ethernet MAC Address2 High Register */
S#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
S#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
S#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
S  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
S  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
S  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
S  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
S  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
S  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
S#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
S
S/* Bit definition for Ethernet MAC Address2 Low Register */
S#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
S
S/* Bit definition for Ethernet MAC Address3 High Register */
S#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
S#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
S#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
S  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
S  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
S  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
S  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
S  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
S  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
S#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
S
S/* Bit definition for Ethernet MAC Address3 Low Register */
S#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
S
S/******************************************************************************/
S/*                Ethernet MMC Registers bits definition                      */
S/******************************************************************************/
S
S/* Bit definition for Ethernet MMC Contol Register */
S#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020)  /* MMC counter Full-Half preset */
S#define ETH_MMCCR_MCP        ((uint32_t)0x00000010)  /* MMC counter preset */
S#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
S#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
S#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
S#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
S
S/* Bit definition for Ethernet MMC Receive Interrupt Register */
S#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
S#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
S#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
S
S/* Bit definition for Ethernet MMC Transmit Interrupt Register */
S#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
S#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
S#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
S
S/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
S#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
S#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
S#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
S
S/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
S#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
S#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
S#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
S
S/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
S#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
S
S/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
S#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
S
S/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
S#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
S
S/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
S#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
S
S/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
S#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
S
S/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
S#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
S
S/******************************************************************************/
S/*               Ethernet PTP Registers bits definition                       */
S/******************************************************************************/
S
S/* Bit definition for Ethernet PTP Time Stamp Contol Register */
S#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000)  /* Time stamp clock node type */
S#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
S#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */
S#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
S#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
S#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
S#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400)  /* Time stamp PTP packet snooping for version2 format enable */
S#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200)  /* Time stamp Sub-seconds rollover */
S#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */
S
S#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
S#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
S#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
S#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
S#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
S#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
S
S/* Bit definition for Ethernet PTP Sub-Second Increment Register */
S#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
S
S/* Bit definition for Ethernet PTP Time Stamp High Register */
S#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
S
S/* Bit definition for Ethernet PTP Time Stamp Low Register */
S#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
S#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
S
S/* Bit definition for Ethernet PTP Time Stamp High Update Register */
S#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
S
S/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
S#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
S#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
S
S/* Bit definition for Ethernet PTP Time Stamp Addend Register */
S#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
S
S/* Bit definition for Ethernet PTP Target Time High Register */
S#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
S
S/* Bit definition for Ethernet PTP Target Time Low Register */
S#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
S
S/* Bit definition for Ethernet PTP Time Stamp Status Register */
S#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020)  /* Time stamp target time reached */
S#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010)  /* Time stamp seconds overflow */
S
S/******************************************************************************/
S/*                 Ethernet DMA Registers bits definition                     */
S/******************************************************************************/
S
S/* Bit definition for Ethernet DMA Bus Mode Register */
S#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
S#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
S#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
S#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
S  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
S  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
S  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
S  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
S  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
S  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
S  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
S  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
S  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
S  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
S  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
S  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
S#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
S#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
S  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
S  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
S  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
S  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
S#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
S  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
S  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
S  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
S  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
S  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
S  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
S  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
S  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
S  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
S  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
S  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
S  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
S#define ETH_DMABMR_EDE       ((uint32_t)0x00000080)  /* Enhanced Descriptor Enable */
S#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
S#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
S#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
S
S/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
S#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
S
S/* Bit definition for Ethernet DMA Receive Poll Demand Register */
S#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
S
S/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
S#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
S
S/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
S#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
S
S/* Bit definition for Ethernet DMA Status Register */
S#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
S#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
S#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
S#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
S  /* combination with EBS[2:0] for GetFlagStatus function */
S  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
S  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
S  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
S#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
S  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
S  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
S  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
S  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
S  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
S  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
S#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
S  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
S  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
S  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
S  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
S  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
S  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
S#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
S#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
S#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
S#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
S#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
S#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
S#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
S#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
S#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
S#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
S#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
S#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
S#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
S#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
S#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
S
S/* Bit definition for Ethernet DMA Operation Mode Register */
S#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
S#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
S#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
S#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
S#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
S#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
S  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
S  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
S  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
S  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
S  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
S  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
S  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
S  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
S#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
S#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
S#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
S#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
S  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
S  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
S  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
S  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
S#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
S#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
S
S/* Bit definition for Ethernet DMA Interrupt Enable Register */
S#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
S#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
S#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
S#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
S#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
S#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
S#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
S#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
S#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
S#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
S#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
S#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
S#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
S#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
S#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
S
S/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
S#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
S#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
S#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
S#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
S
S/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
S#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
S
S/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
S#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
S
S/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
S#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
S
S/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
S#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
S
S/**
S  *
S  */
S
S /**
S  * @}
S  */ 
S
S#ifdef USE_STDPERIPH_DRIVER
S  #include "stm32f4xx_conf.h"
S#endif /* USE_STDPERIPH_DRIVER */
S
S/** @addtogroup Exported_macro
S  * @{
S  */
S
S#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
S
S#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
S
S#define READ_BIT(REG, BIT)    ((REG) & (BIT))
S
S#define CLEAR_REG(REG)        ((REG) = (0x0))
S
S#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
S
S#define READ_REG(REG)         ((REG))
S
S#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
S
S/**
S  * @}
S  */
S
S#ifdef __cplusplus
S}
S#endif /* __cplusplus */
S
N#endif /* __STM32F4xx_H */
N
N/**
N  * @}
N  */
N
N  /**
N  * @}
N  */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 39 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_adc.h" 2
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup ADC
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N
N/** 
N  * @brief   ADC Init structure definition  
N  */ 
Ntypedef struct
N{
N  uint32_t ADC_Resolution;                /*!< Configures the ADC resolution dual mode. 
N                                               This parameter can be a value of @ref ADC_resolution */                                   
N  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion 
N                                               is performed in Scan (multichannels) 
N                                               or Single (one channel) mode.
N                                               This parameter can be set to ENABLE or DISABLE */ 
N  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion 
N                                               is performed in Continuous or Single mode.
N                                               This parameter can be set to ENABLE or DISABLE. */
N  uint32_t ADC_ExternalTrigConvEdge;      /*!< Select the external trigger edge and
N                                               enable the trigger of a regular group. 
N                                               This parameter can be a value of 
N                                               @ref ADC_external_trigger_edge_for_regular_channels_conversion */
N  uint32_t ADC_ExternalTrigConv;          /*!< Select the external event used to trigger 
N                                               the start of conversion of a regular group.
N                                               This parameter can be a value of 
N                                               @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
N  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data  alignment
N                                               is left or right. This parameter can be 
N                                               a value of @ref ADC_data_align */
N  uint8_t  ADC_NbrOfConversion;           /*!< Specifies the number of ADC conversions
N                                               that will be done using the sequencer for
N                                               regular channel group.
N                                               This parameter must range from 1 to 16. */
N}ADC_InitTypeDef;
N  
N/** 
N  * @brief   ADC Common Init structure definition  
N  */ 
Ntypedef struct 
N{
N  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in 
N                                               independent or multi mode. 
N                                               This parameter can be a value of @ref ADC_Common_mode */                                              
N  uint32_t ADC_Prescaler;                 /*!< Select the frequency of the clock 
N                                               to the ADC. The clock is common for all the ADCs.
N                                               This parameter can be a value of @ref ADC_Prescaler */
N  uint32_t ADC_DMAAccessMode;             /*!< Configures the Direct memory access 
N                                              mode for multi ADC mode.
N                                               This parameter can be a value of 
N                                               @ref ADC_Direct_memory_access_mode_for_multi_mode */
N  uint32_t ADC_TwoSamplingDelay;          /*!< Configures the Delay between 2 sampling phases.
N                                               This parameter can be a value of 
N                                               @ref ADC_delay_between_2_sampling_phases */
N  
N}ADC_CommonInitTypeDef;
N
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup ADC_Exported_Constants
N  * @{
N  */ 
N#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
N                                   ((PERIPH) == ADC2) || \
N                                   ((PERIPH) == ADC3))  
X#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) ||                                    ((PERIPH) == ADC2) ||                                    ((PERIPH) == ADC3))  
N
N/** @defgroup ADC_Common_mode 
N  * @{
N  */ 
N#define ADC_Mode_Independent                       ((uint32_t)0x00000000)       
N#define ADC_DualMode_RegSimult_InjecSimult         ((uint32_t)0x00000001)
N#define ADC_DualMode_RegSimult_AlterTrig           ((uint32_t)0x00000002)
N#define ADC_DualMode_InjecSimult                   ((uint32_t)0x00000005)
N#define ADC_DualMode_RegSimult                     ((uint32_t)0x00000006)
N#define ADC_DualMode_Interl                        ((uint32_t)0x00000007)
N#define ADC_DualMode_AlterTrig                     ((uint32_t)0x00000009)
N#define ADC_TripleMode_RegSimult_InjecSimult       ((uint32_t)0x00000011)
N#define ADC_TripleMode_RegSimult_AlterTrig         ((uint32_t)0x00000012)
N#define ADC_TripleMode_InjecSimult                 ((uint32_t)0x00000015)
N#define ADC_TripleMode_RegSimult                   ((uint32_t)0x00000016)
N#define ADC_TripleMode_Interl                      ((uint32_t)0x00000017)
N#define ADC_TripleMode_AlterTrig                   ((uint32_t)0x00000019)
N#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
N                           ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
N                           ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
N                           ((MODE) == ADC_DualMode_InjecSimult) || \
N                           ((MODE) == ADC_DualMode_RegSimult) || \
N                           ((MODE) == ADC_DualMode_Interl) || \
N                           ((MODE) == ADC_DualMode_AlterTrig) || \
N                           ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
N                           ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
N                           ((MODE) == ADC_TripleMode_InjecSimult) || \
N                           ((MODE) == ADC_TripleMode_RegSimult) || \
N                           ((MODE) == ADC_TripleMode_Interl) || \
N                           ((MODE) == ADC_TripleMode_AlterTrig))
X#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) ||                            ((MODE) == ADC_DualMode_RegSimult_InjecSimult) ||                            ((MODE) == ADC_DualMode_RegSimult_AlterTrig) ||                            ((MODE) == ADC_DualMode_InjecSimult) ||                            ((MODE) == ADC_DualMode_RegSimult) ||                            ((MODE) == ADC_DualMode_Interl) ||                            ((MODE) == ADC_DualMode_AlterTrig) ||                            ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) ||                            ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) ||                            ((MODE) == ADC_TripleMode_InjecSimult) ||                            ((MODE) == ADC_TripleMode_RegSimult) ||                            ((MODE) == ADC_TripleMode_Interl) ||                            ((MODE) == ADC_TripleMode_AlterTrig))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_Prescaler 
N  * @{
N  */ 
N#define ADC_Prescaler_Div2                         ((uint32_t)0x00000000)
N#define ADC_Prescaler_Div4                         ((uint32_t)0x00010000)
N#define ADC_Prescaler_Div6                         ((uint32_t)0x00020000)
N#define ADC_Prescaler_Div8                         ((uint32_t)0x00030000)
N#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
N                                     ((PRESCALER) == ADC_Prescaler_Div4) || \
N                                     ((PRESCALER) == ADC_Prescaler_Div6) || \
N                                     ((PRESCALER) == ADC_Prescaler_Div8))
X#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) ||                                      ((PRESCALER) == ADC_Prescaler_Div4) ||                                      ((PRESCALER) == ADC_Prescaler_Div6) ||                                      ((PRESCALER) == ADC_Prescaler_Div8))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode 
N  * @{
N  */ 
N#define ADC_DMAAccessMode_Disabled      ((uint32_t)0x00000000)     /* DMA mode disabled */
N#define ADC_DMAAccessMode_1             ((uint32_t)0x00004000)     /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
N#define ADC_DMAAccessMode_2             ((uint32_t)0x00008000)     /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
N#define ADC_DMAAccessMode_3             ((uint32_t)0x0000C000)     /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
N#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
N                                      ((MODE) == ADC_DMAAccessMode_1) || \
N                                      ((MODE) == ADC_DMAAccessMode_2) || \
N                                      ((MODE) == ADC_DMAAccessMode_3))
X#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) ||                                       ((MODE) == ADC_DMAAccessMode_1) ||                                       ((MODE) == ADC_DMAAccessMode_2) ||                                       ((MODE) == ADC_DMAAccessMode_3))
N                                     
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_delay_between_2_sampling_phases 
N  * @{
N  */ 
N#define ADC_TwoSamplingDelay_5Cycles               ((uint32_t)0x00000000)
N#define ADC_TwoSamplingDelay_6Cycles               ((uint32_t)0x00000100)
N#define ADC_TwoSamplingDelay_7Cycles               ((uint32_t)0x00000200)
N#define ADC_TwoSamplingDelay_8Cycles               ((uint32_t)0x00000300)
N#define ADC_TwoSamplingDelay_9Cycles               ((uint32_t)0x00000400)
N#define ADC_TwoSamplingDelay_10Cycles              ((uint32_t)0x00000500)
N#define ADC_TwoSamplingDelay_11Cycles              ((uint32_t)0x00000600)
N#define ADC_TwoSamplingDelay_12Cycles              ((uint32_t)0x00000700)
N#define ADC_TwoSamplingDelay_13Cycles              ((uint32_t)0x00000800)
N#define ADC_TwoSamplingDelay_14Cycles              ((uint32_t)0x00000900)
N#define ADC_TwoSamplingDelay_15Cycles              ((uint32_t)0x00000A00)
N#define ADC_TwoSamplingDelay_16Cycles              ((uint32_t)0x00000B00)
N#define ADC_TwoSamplingDelay_17Cycles              ((uint32_t)0x00000C00)
N#define ADC_TwoSamplingDelay_18Cycles              ((uint32_t)0x00000D00)
N#define ADC_TwoSamplingDelay_19Cycles              ((uint32_t)0x00000E00)
N#define ADC_TwoSamplingDelay_20Cycles              ((uint32_t)0x00000F00)
N#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
N                                      ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
X#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_6Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_7Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_8Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_9Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_10Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_11Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_12Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_13Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_14Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_15Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_16Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_17Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_18Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_19Cycles) ||                                       ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
N                                     
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_resolution 
N  * @{
N  */ 
N#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
N#define ADC_Resolution_10b                         ((uint32_t)0x01000000)
N#define ADC_Resolution_8b                          ((uint32_t)0x02000000)
N#define ADC_Resolution_6b                          ((uint32_t)0x03000000)
N#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
N                                       ((RESOLUTION) == ADC_Resolution_10b) || \
N                                       ((RESOLUTION) == ADC_Resolution_8b) || \
N                                       ((RESOLUTION) == ADC_Resolution_6b))
X#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) ||                                        ((RESOLUTION) == ADC_Resolution_10b) ||                                        ((RESOLUTION) == ADC_Resolution_8b) ||                                        ((RESOLUTION) == ADC_Resolution_6b))
N                                      
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion 
N  * @{
N  */ 
N#define ADC_ExternalTrigConvEdge_None          ((uint32_t)0x00000000)
N#define ADC_ExternalTrigConvEdge_Rising        ((uint32_t)0x10000000)
N#define ADC_ExternalTrigConvEdge_Falling       ((uint32_t)0x20000000)
N#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
N#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
N                             ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
N                             ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
N                             ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
X#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) ||                              ((EDGE) == ADC_ExternalTrigConvEdge_Rising) ||                              ((EDGE) == ADC_ExternalTrigConvEdge_Falling) ||                              ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion 
N  * @{
N  */ 
N#define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000)
N#define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x01000000)
N#define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x02000000)
N#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x03000000)
N#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x04000000)
N#define ADC_ExternalTrigConv_T2_CC4                ((uint32_t)0x05000000)
N#define ADC_ExternalTrigConv_T2_TRGO               ((uint32_t)0x06000000)
N#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x07000000)
N#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x08000000)
N#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x09000000)
N#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x0A000000)
N#define ADC_ExternalTrigConv_T5_CC2                ((uint32_t)0x0B000000)
N#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x0C000000)
N#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x0D000000)
N#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x0E000000)
N#define ADC_ExternalTrigConv_Ext_IT11              ((uint32_t)0x0F000000)
N#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
N                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
X#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) ||                                   ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_data_align 
N  * @{
N  */ 
N#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
N#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
N#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
N                                  ((ALIGN) == ADC_DataAlign_Left))
X#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) ||                                   ((ALIGN) == ADC_DataAlign_Left))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_channels 
N  * @{
N  */ 
N#define ADC_Channel_0                               ((uint8_t)0x00)
N#define ADC_Channel_1                               ((uint8_t)0x01)
N#define ADC_Channel_2                               ((uint8_t)0x02)
N#define ADC_Channel_3                               ((uint8_t)0x03)
N#define ADC_Channel_4                               ((uint8_t)0x04)
N#define ADC_Channel_5                               ((uint8_t)0x05)
N#define ADC_Channel_6                               ((uint8_t)0x06)
N#define ADC_Channel_7                               ((uint8_t)0x07)
N#define ADC_Channel_8                               ((uint8_t)0x08)
N#define ADC_Channel_9                               ((uint8_t)0x09)
N#define ADC_Channel_10                              ((uint8_t)0x0A)
N#define ADC_Channel_11                              ((uint8_t)0x0B)
N#define ADC_Channel_12                              ((uint8_t)0x0C)
N#define ADC_Channel_13                              ((uint8_t)0x0D)
N#define ADC_Channel_14                              ((uint8_t)0x0E)
N#define ADC_Channel_15                              ((uint8_t)0x0F)
N#define ADC_Channel_16                              ((uint8_t)0x10)
N#define ADC_Channel_17                              ((uint8_t)0x11)
N#define ADC_Channel_18                              ((uint8_t)0x12)
N
N#if defined (STM32F40_41xxx)
X#if 1L
N#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE)
X#if 0L || 0L || 0L || 0L
S#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_18)
N#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
N
N#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
N#define ADC_Channel_Vbat                            ((uint8_t)ADC_Channel_18)
N
N#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
N                                 ((CHANNEL) == ADC_Channel_1) || \
N                                 ((CHANNEL) == ADC_Channel_2) || \
N                                 ((CHANNEL) == ADC_Channel_3) || \
N                                 ((CHANNEL) == ADC_Channel_4) || \
N                                 ((CHANNEL) == ADC_Channel_5) || \
N                                 ((CHANNEL) == ADC_Channel_6) || \
N                                 ((CHANNEL) == ADC_Channel_7) || \
N                                 ((CHANNEL) == ADC_Channel_8) || \
N                                 ((CHANNEL) == ADC_Channel_9) || \
N                                 ((CHANNEL) == ADC_Channel_10) || \
N                                 ((CHANNEL) == ADC_Channel_11) || \
N                                 ((CHANNEL) == ADC_Channel_12) || \
N                                 ((CHANNEL) == ADC_Channel_13) || \
N                                 ((CHANNEL) == ADC_Channel_14) || \
N                                 ((CHANNEL) == ADC_Channel_15) || \
N                                 ((CHANNEL) == ADC_Channel_16) || \
N                                 ((CHANNEL) == ADC_Channel_17) || \
N                                 ((CHANNEL) == ADC_Channel_18))
X#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) ||                                  ((CHANNEL) == ADC_Channel_1) ||                                  ((CHANNEL) == ADC_Channel_2) ||                                  ((CHANNEL) == ADC_Channel_3) ||                                  ((CHANNEL) == ADC_Channel_4) ||                                  ((CHANNEL) == ADC_Channel_5) ||                                  ((CHANNEL) == ADC_Channel_6) ||                                  ((CHANNEL) == ADC_Channel_7) ||                                  ((CHANNEL) == ADC_Channel_8) ||                                  ((CHANNEL) == ADC_Channel_9) ||                                  ((CHANNEL) == ADC_Channel_10) ||                                  ((CHANNEL) == ADC_Channel_11) ||                                  ((CHANNEL) == ADC_Channel_12) ||                                  ((CHANNEL) == ADC_Channel_13) ||                                  ((CHANNEL) == ADC_Channel_14) ||                                  ((CHANNEL) == ADC_Channel_15) ||                                  ((CHANNEL) == ADC_Channel_16) ||                                  ((CHANNEL) == ADC_Channel_17) ||                                  ((CHANNEL) == ADC_Channel_18))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_sampling_times 
N  * @{
N  */ 
N#define ADC_SampleTime_3Cycles                    ((uint8_t)0x00)
N#define ADC_SampleTime_15Cycles                   ((uint8_t)0x01)
N#define ADC_SampleTime_28Cycles                   ((uint8_t)0x02)
N#define ADC_SampleTime_56Cycles                   ((uint8_t)0x03)
N#define ADC_SampleTime_84Cycles                   ((uint8_t)0x04)
N#define ADC_SampleTime_112Cycles                  ((uint8_t)0x05)
N#define ADC_SampleTime_144Cycles                  ((uint8_t)0x06)
N#define ADC_SampleTime_480Cycles                  ((uint8_t)0x07)
N#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
N                                  ((TIME) == ADC_SampleTime_15Cycles) || \
N                                  ((TIME) == ADC_SampleTime_28Cycles) || \
N                                  ((TIME) == ADC_SampleTime_56Cycles) || \
N                                  ((TIME) == ADC_SampleTime_84Cycles) || \
N                                  ((TIME) == ADC_SampleTime_112Cycles) || \
N                                  ((TIME) == ADC_SampleTime_144Cycles) || \
N                                  ((TIME) == ADC_SampleTime_480Cycles))
X#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) ||                                   ((TIME) == ADC_SampleTime_15Cycles) ||                                   ((TIME) == ADC_SampleTime_28Cycles) ||                                   ((TIME) == ADC_SampleTime_56Cycles) ||                                   ((TIME) == ADC_SampleTime_84Cycles) ||                                   ((TIME) == ADC_SampleTime_112Cycles) ||                                   ((TIME) == ADC_SampleTime_144Cycles) ||                                   ((TIME) == ADC_SampleTime_480Cycles))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion 
N  * @{
N  */ 
N#define ADC_ExternalTrigInjecConvEdge_None          ((uint32_t)0x00000000)
N#define ADC_ExternalTrigInjecConvEdge_Rising        ((uint32_t)0x00100000)
N#define ADC_ExternalTrigInjecConvEdge_Falling       ((uint32_t)0x00200000)
N#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
N#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
N                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
N                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
N                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
X#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) ||                                           ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) ||                                           ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) ||                                           ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
N                                            
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion 
N  * @{
N  */ 
N#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00000000)
N#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00010000)
N#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00020000)
N#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00030000)
N#define ADC_ExternalTrigInjecConv_T3_CC2            ((uint32_t)0x00040000)
N#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00050000)
N#define ADC_ExternalTrigInjecConv_T4_CC1            ((uint32_t)0x00060000)
N#define ADC_ExternalTrigInjecConv_T4_CC2            ((uint32_t)0x00070000)
N#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00080000)
N#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00090000)
N#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x000A0000)
N#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x000B0000)
N#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x000C0000)
N#define ADC_ExternalTrigInjecConv_T8_CC3            ((uint32_t)0x000D0000)
N#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x000E0000)
N#define ADC_ExternalTrigInjecConv_Ext_IT15          ((uint32_t)0x000F0000)
N#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
N                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
X#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) ||                                         ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_injected_channel_selection 
N  * @{
N  */ 
N#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
N#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
N#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
N#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
N#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
N                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
N                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
N                                          ((CHANNEL) == ADC_InjectedChannel_4))
X#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) ||                                           ((CHANNEL) == ADC_InjectedChannel_2) ||                                           ((CHANNEL) == ADC_InjectedChannel_3) ||                                           ((CHANNEL) == ADC_InjectedChannel_4))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_analog_watchdog_selection 
N  * @{
N  */ 
N#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
N#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
N#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
N#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
N#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
N#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
N#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
N#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
N                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
N                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
N                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
N                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
N                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
N                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
X#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) ||                                           ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) ||                                           ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) ||                                           ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) ||                                           ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) ||                                           ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) ||                                           ((WATCHDOG) == ADC_AnalogWatchdog_None))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_interrupts_definition 
N  * @{
N  */ 
N#define ADC_IT_EOC                                 ((uint16_t)0x0205)  
N#define ADC_IT_AWD                                 ((uint16_t)0x0106)  
N#define ADC_IT_JEOC                                ((uint16_t)0x0407)  
N#define ADC_IT_OVR                                 ((uint16_t)0x201A)  
N#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
N                       ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) 
X#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) ||                        ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) 
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_flags_definition 
N  * @{
N  */ 
N#define ADC_FLAG_AWD                               ((uint8_t)0x01)
N#define ADC_FLAG_EOC                               ((uint8_t)0x02)
N#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
N#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
N#define ADC_FLAG_STRT                              ((uint8_t)0x10)
N#define ADC_FLAG_OVR                               ((uint8_t)0x20)   
N  
N#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))   
N#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
N                               ((FLAG) == ADC_FLAG_EOC) || \
N                               ((FLAG) == ADC_FLAG_JEOC) || \
N                               ((FLAG)== ADC_FLAG_JSTRT) || \
N                               ((FLAG) == ADC_FLAG_STRT) || \
N                               ((FLAG)== ADC_FLAG_OVR))     
X#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) ||                                ((FLAG) == ADC_FLAG_EOC) ||                                ((FLAG) == ADC_FLAG_JEOC) ||                                ((FLAG)== ADC_FLAG_JSTRT) ||                                ((FLAG) == ADC_FLAG_STRT) ||                                ((FLAG)== ADC_FLAG_OVR))     
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_thresholds 
N  * @{
N  */ 
N#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_injected_offset 
N  * @{
N  */ 
N#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_injected_length 
N  * @{
N  */ 
N#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_injected_rank 
N  * @{
N  */ 
N#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_regular_length 
N  * @{
N  */ 
N#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_regular_rank 
N  * @{
N  */ 
N#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup ADC_regular_discontinuous_mode_number 
N  * @{
N  */ 
N#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
N/**
N  * @}
N  */ 
N
N
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/  
N
N/*  Function used to set the ADC configuration to the default reset state *****/  
Nvoid ADC_DeInit(void);
N
N/* Initialization and Configuration functions *********************************/
Nvoid ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
Nvoid ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
Nvoid ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
Nvoid ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
Nvoid ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
N
N/* Analog Watchdog configuration functions ************************************/
Nvoid ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
Nvoid ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
Nvoid ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
N
N/* Temperature Sensor, Vrefint and VBAT management functions ******************/
Nvoid ADC_TempSensorVrefintCmd(FunctionalState NewState);
Nvoid ADC_VBATCmd(FunctionalState NewState);
N
N/* Regular Channels Configuration functions ***********************************/
Nvoid ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
Nvoid ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
NFlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
Nvoid ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
Nvoid ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
Nvoid ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
Nvoid ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
Nuint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
Nuint32_t ADC_GetMultiModeConversionValue(void);
N
N/* Regular Channels DMA Configuration functions *******************************/
Nvoid ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
Nvoid ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
Nvoid ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
N
N/* Injected channels Configuration functions **********************************/
Nvoid ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
Nvoid ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
Nvoid ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
Nvoid ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
Nvoid ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
Nvoid ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
NFlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
Nvoid ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
Nvoid ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
Nuint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
N
N/* Interrupts and flags management functions **********************************/
Nvoid ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
NFlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
Nvoid ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
NITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
Nvoid ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_ADC_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 35 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_crc.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_crc.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_crc.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the CRC firmware 
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_CRC_H
N#define __STM32F4xx_CRC_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup CRC
N  * @{
N  */
N
N/* Exported types ------------------------------------------------------------*/
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup CRC_Exported_Constants
N  * @{
N  */
N
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/  
N
Nvoid CRC_ResetDR(void);
Nuint32_t CRC_CalcCRC(uint32_t Data);
Nuint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
Nuint32_t CRC_GetCRC(void);
Nvoid CRC_SetIDRegister(uint8_t IDValue);
Nuint8_t CRC_GetIDRegister(void);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __STM32F4xx_CRC_H */
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 36 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_dbgmcu.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_dbgmcu.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_dbgmcu.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the DBGMCU firmware library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_DBGMCU_H
N#define __STM32F4xx_DBGMCU_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup DBGMCU
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup DBGMCU_Exported_Constants
N  * @{
N  */ 
N#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
N#define DBGMCU_STOP                  ((uint32_t)0x00000002)
N#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
N#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
N
N#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000001)
N#define DBGMCU_TIM3_STOP             ((uint32_t)0x00000002)
N#define DBGMCU_TIM4_STOP             ((uint32_t)0x00000004)
N#define DBGMCU_TIM5_STOP             ((uint32_t)0x00000008)
N#define DBGMCU_TIM6_STOP             ((uint32_t)0x00000010)
N#define DBGMCU_TIM7_STOP             ((uint32_t)0x00000020)
N#define DBGMCU_TIM12_STOP            ((uint32_t)0x00000040)
N#define DBGMCU_TIM13_STOP            ((uint32_t)0x00000080)
N#define DBGMCU_TIM14_STOP            ((uint32_t)0x00000100)
N#define DBGMCU_RTC_STOP              ((uint32_t)0x00000400)
N#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000800)
N#define DBGMCU_IWDG_STOP             ((uint32_t)0x00001000)
N#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)
N#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)
N#define DBGMCU_I2C3_SMBUS_TIMEOUT    ((uint32_t)0x00800000)
N#define DBGMCU_CAN1_STOP             ((uint32_t)0x02000000)
N#define DBGMCU_CAN2_STOP             ((uint32_t)0x04000000)
N#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
N
N#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000001)
N#define DBGMCU_TIM8_STOP             ((uint32_t)0x00000002)
N#define DBGMCU_TIM9_STOP             ((uint32_t)0x00010000)
N#define DBGMCU_TIM10_STOP            ((uint32_t)0x00020000)
N#define DBGMCU_TIM11_STOP            ((uint32_t)0x00040000)
N#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
Nuint32_t DBGMCU_GetREVID(void);
Nuint32_t DBGMCU_GetDEVID(void);
Nvoid DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
Nvoid DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
Nvoid DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __STM32F4xx_DBGMCU_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 37 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_dma.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_dma.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_dma.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the DMA firmware 
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************  
N  */ 
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_DMA_H
N#define __STM32F4xx_DMA_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup DMA
N  * @{
N  */
N
N/* Exported types ------------------------------------------------------------*/
N
N/** 
N  * @brief  DMA Init structure definition
N  */
N
Ntypedef struct
N{
N  uint32_t DMA_Channel;            /*!< Specifies the channel used for the specified stream. 
N                                        This parameter can be a value of @ref DMA_channel */
N 
N  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
N
N  uint32_t DMA_Memory0BaseAddr;    /*!< Specifies the memory 0 base address for DMAy Streamx. 
N                                        This memory is the default memory used when double buffer mode is
N                                        not enabled. */
N
N  uint32_t DMA_DIR;                /*!< Specifies if the data will be transferred from memory to peripheral, 
N                                        from memory to memory or from peripheral to memory.
N                                        This parameter can be a value of @ref DMA_data_transfer_direction */
N
N  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Stream. 
N                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
N                                        or DMA_MemoryDataSize members depending in the transfer direction. */
N
N  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register should be incremented or not.
N                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
N
N  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register should be incremented or not.
N                                        This parameter can be a value of @ref DMA_memory_incremented_mode */
N
N  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
N                                        This parameter can be a value of @ref DMA_peripheral_data_size */
N
N  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
N                                        This parameter can be a value of @ref DMA_memory_data_size */
N
N  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Streamx.
N                                        This parameter can be a value of @ref DMA_circular_normal_mode
N                                        @note The circular buffer mode cannot be used if the memory-to-memory
N                                              data transfer is configured on the selected Stream */
N
N  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Streamx.
N                                        This parameter can be a value of @ref DMA_priority_level */
N
N  uint32_t DMA_FIFOMode;          /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
N                                        This parameter can be a value of @ref DMA_fifo_direct_mode
N                                        @note The Direct mode (FIFO mode disabled) cannot be used if the 
N                                               memory-to-memory data transfer is configured on the selected Stream */
N
N  uint32_t DMA_FIFOThreshold;      /*!< Specifies the FIFO threshold level.
N                                        This parameter can be a value of @ref DMA_fifo_threshold_level */
N
N  uint32_t DMA_MemoryBurst;        /*!< Specifies the Burst transfer configuration for the memory transfers. 
N                                        It specifies the amount of data to be transferred in a single non interruptable 
N                                        transaction. This parameter can be a value of @ref DMA_memory_burst 
N                                        @note The burst mode is possible only if the address Increment mode is enabled. */
N
N  uint32_t DMA_PeripheralBurst;    /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
N                                        It specifies the amount of data to be transferred in a single non interruptable 
N                                        transaction. This parameter can be a value of @ref DMA_peripheral_burst
N                                        @note The burst mode is possible only if the address Increment mode is enabled. */  
N}DMA_InitTypeDef;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup DMA_Exported_Constants
N  * @{
N  */
N
N#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
N                                   ((PERIPH) == DMA1_Stream1) || \
N                                   ((PERIPH) == DMA1_Stream2) || \
N                                   ((PERIPH) == DMA1_Stream3) || \
N                                   ((PERIPH) == DMA1_Stream4) || \
N                                   ((PERIPH) == DMA1_Stream5) || \
N                                   ((PERIPH) == DMA1_Stream6) || \
N                                   ((PERIPH) == DMA1_Stream7) || \
N                                   ((PERIPH) == DMA2_Stream0) || \
N                                   ((PERIPH) == DMA2_Stream1) || \
N                                   ((PERIPH) == DMA2_Stream2) || \
N                                   ((PERIPH) == DMA2_Stream3) || \
N                                   ((PERIPH) == DMA2_Stream4) || \
N                                   ((PERIPH) == DMA2_Stream5) || \
N                                   ((PERIPH) == DMA2_Stream6) || \
N                                   ((PERIPH) == DMA2_Stream7))
X#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) ||                                    ((PERIPH) == DMA1_Stream1) ||                                    ((PERIPH) == DMA1_Stream2) ||                                    ((PERIPH) == DMA1_Stream3) ||                                    ((PERIPH) == DMA1_Stream4) ||                                    ((PERIPH) == DMA1_Stream5) ||                                    ((PERIPH) == DMA1_Stream6) ||                                    ((PERIPH) == DMA1_Stream7) ||                                    ((PERIPH) == DMA2_Stream0) ||                                    ((PERIPH) == DMA2_Stream1) ||                                    ((PERIPH) == DMA2_Stream2) ||                                    ((PERIPH) == DMA2_Stream3) ||                                    ((PERIPH) == DMA2_Stream4) ||                                    ((PERIPH) == DMA2_Stream5) ||                                    ((PERIPH) == DMA2_Stream6) ||                                    ((PERIPH) == DMA2_Stream7))
N
N#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
N                                           ((CONTROLLER) == DMA2))
X#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) ||                                            ((CONTROLLER) == DMA2))
N
N/** @defgroup DMA_channel 
N  * @{
N  */ 
N#define DMA_Channel_0                     ((uint32_t)0x00000000)
N#define DMA_Channel_1                     ((uint32_t)0x02000000)
N#define DMA_Channel_2                     ((uint32_t)0x04000000)
N#define DMA_Channel_3                     ((uint32_t)0x06000000)
N#define DMA_Channel_4                     ((uint32_t)0x08000000)
N#define DMA_Channel_5                     ((uint32_t)0x0A000000)
N#define DMA_Channel_6                     ((uint32_t)0x0C000000)
N#define DMA_Channel_7                     ((uint32_t)0x0E000000)
N
N#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
N                                 ((CHANNEL) == DMA_Channel_1) || \
N                                 ((CHANNEL) == DMA_Channel_2) || \
N                                 ((CHANNEL) == DMA_Channel_3) || \
N                                 ((CHANNEL) == DMA_Channel_4) || \
N                                 ((CHANNEL) == DMA_Channel_5) || \
N                                 ((CHANNEL) == DMA_Channel_6) || \
N                                 ((CHANNEL) == DMA_Channel_7))
X#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) ||                                  ((CHANNEL) == DMA_Channel_1) ||                                  ((CHANNEL) == DMA_Channel_2) ||                                  ((CHANNEL) == DMA_Channel_3) ||                                  ((CHANNEL) == DMA_Channel_4) ||                                  ((CHANNEL) == DMA_Channel_5) ||                                  ((CHANNEL) == DMA_Channel_6) ||                                  ((CHANNEL) == DMA_Channel_7))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_data_transfer_direction 
N  * @{
N  */ 
N#define DMA_DIR_PeripheralToMemory        ((uint32_t)0x00000000)
N#define DMA_DIR_MemoryToPeripheral        ((uint32_t)0x00000040) 
N#define DMA_DIR_MemoryToMemory            ((uint32_t)0x00000080)
N
N#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
N                                     ((DIRECTION) == DMA_DIR_MemoryToPeripheral)  || \
N                                     ((DIRECTION) == DMA_DIR_MemoryToMemory)) 
X#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) ||                                      ((DIRECTION) == DMA_DIR_MemoryToPeripheral)  ||                                      ((DIRECTION) == DMA_DIR_MemoryToMemory)) 
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_data_buffer_size 
N  * @{
N  */ 
N#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_peripheral_incremented_mode 
N  * @{
N  */ 
N#define DMA_PeripheralInc_Enable          ((uint32_t)0x00000200)
N#define DMA_PeripheralInc_Disable         ((uint32_t)0x00000000)
N
N#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
N                                            ((STATE) == DMA_PeripheralInc_Disable))
X#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) ||                                             ((STATE) == DMA_PeripheralInc_Disable))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_memory_incremented_mode 
N  * @{
N  */ 
N#define DMA_MemoryInc_Enable              ((uint32_t)0x00000400)
N#define DMA_MemoryInc_Disable             ((uint32_t)0x00000000)
N
N#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
N                                        ((STATE) == DMA_MemoryInc_Disable))
X#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) ||                                         ((STATE) == DMA_MemoryInc_Disable))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_peripheral_data_size 
N  * @{
N  */ 
N#define DMA_PeripheralDataSize_Byte       ((uint32_t)0x00000000) 
N#define DMA_PeripheralDataSize_HalfWord   ((uint32_t)0x00000800) 
N#define DMA_PeripheralDataSize_Word       ((uint32_t)0x00001000)
N
N#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte)  || \
N                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
N                                           ((SIZE) == DMA_PeripheralDataSize_Word))
X#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte)  ||                                            ((SIZE) == DMA_PeripheralDataSize_HalfWord) ||                                            ((SIZE) == DMA_PeripheralDataSize_Word))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_memory_data_size 
N  * @{
N  */ 
N#define DMA_MemoryDataSize_Byte           ((uint32_t)0x00000000) 
N#define DMA_MemoryDataSize_HalfWord       ((uint32_t)0x00002000) 
N#define DMA_MemoryDataSize_Word           ((uint32_t)0x00004000)
N
N#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte)  || \
N                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
N                                       ((SIZE) == DMA_MemoryDataSize_Word ))
X#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte)  ||                                        ((SIZE) == DMA_MemoryDataSize_HalfWord) ||                                        ((SIZE) == DMA_MemoryDataSize_Word ))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_circular_normal_mode 
N  * @{
N  */ 
N#define DMA_Mode_Normal                   ((uint32_t)0x00000000) 
N#define DMA_Mode_Circular                 ((uint32_t)0x00000100)
N
N#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
N                           ((MODE) == DMA_Mode_Circular)) 
X#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) ||                            ((MODE) == DMA_Mode_Circular)) 
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_priority_level 
N  * @{
N  */ 
N#define DMA_Priority_Low                  ((uint32_t)0x00000000)
N#define DMA_Priority_Medium               ((uint32_t)0x00010000) 
N#define DMA_Priority_High                 ((uint32_t)0x00020000)
N#define DMA_Priority_VeryHigh             ((uint32_t)0x00030000)
N
N#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low )   || \
N                                   ((PRIORITY) == DMA_Priority_Medium) || \
N                                   ((PRIORITY) == DMA_Priority_High)   || \
N                                   ((PRIORITY) == DMA_Priority_VeryHigh)) 
X#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low )   ||                                    ((PRIORITY) == DMA_Priority_Medium) ||                                    ((PRIORITY) == DMA_Priority_High)   ||                                    ((PRIORITY) == DMA_Priority_VeryHigh)) 
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_fifo_direct_mode 
N  * @{
N  */ 
N#define DMA_FIFOMode_Disable              ((uint32_t)0x00000000) 
N#define DMA_FIFOMode_Enable               ((uint32_t)0x00000004)
N
N#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
N                                       ((STATE) == DMA_FIFOMode_Enable)) 
X#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) ||                                        ((STATE) == DMA_FIFOMode_Enable)) 
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_fifo_threshold_level 
N  * @{
N  */ 
N#define DMA_FIFOThreshold_1QuarterFull    ((uint32_t)0x00000000)
N#define DMA_FIFOThreshold_HalfFull        ((uint32_t)0x00000001) 
N#define DMA_FIFOThreshold_3QuartersFull   ((uint32_t)0x00000002)
N#define DMA_FIFOThreshold_Full            ((uint32_t)0x00000003)
N
N#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
N                                          ((THRESHOLD) == DMA_FIFOThreshold_HalfFull)      || \
N                                          ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
N                                          ((THRESHOLD) == DMA_FIFOThreshold_Full)) 
X#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) ||                                           ((THRESHOLD) == DMA_FIFOThreshold_HalfFull)      ||                                           ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) ||                                           ((THRESHOLD) == DMA_FIFOThreshold_Full)) 
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_memory_burst 
N  * @{
N  */ 
N#define DMA_MemoryBurst_Single            ((uint32_t)0x00000000)
N#define DMA_MemoryBurst_INC4              ((uint32_t)0x00800000)  
N#define DMA_MemoryBurst_INC8              ((uint32_t)0x01000000)
N#define DMA_MemoryBurst_INC16             ((uint32_t)0x01800000)
N
N#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
N                                    ((BURST) == DMA_MemoryBurst_INC4)  || \
N                                    ((BURST) == DMA_MemoryBurst_INC8)  || \
N                                    ((BURST) == DMA_MemoryBurst_INC16))
X#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) ||                                     ((BURST) == DMA_MemoryBurst_INC4)  ||                                     ((BURST) == DMA_MemoryBurst_INC8)  ||                                     ((BURST) == DMA_MemoryBurst_INC16))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_peripheral_burst 
N  * @{
N  */ 
N#define DMA_PeripheralBurst_Single        ((uint32_t)0x00000000)
N#define DMA_PeripheralBurst_INC4          ((uint32_t)0x00200000)  
N#define DMA_PeripheralBurst_INC8          ((uint32_t)0x00400000)
N#define DMA_PeripheralBurst_INC16         ((uint32_t)0x00600000)
N
N#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
N                                        ((BURST) == DMA_PeripheralBurst_INC4)  || \
N                                        ((BURST) == DMA_PeripheralBurst_INC8)  || \
N                                        ((BURST) == DMA_PeripheralBurst_INC16))
X#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) ||                                         ((BURST) == DMA_PeripheralBurst_INC4)  ||                                         ((BURST) == DMA_PeripheralBurst_INC8)  ||                                         ((BURST) == DMA_PeripheralBurst_INC16))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_fifo_status_level 
N  * @{
N  */
N#define DMA_FIFOStatus_Less1QuarterFull   ((uint32_t)0x00000000 << 3)
N#define DMA_FIFOStatus_1QuarterFull       ((uint32_t)0x00000001 << 3)
N#define DMA_FIFOStatus_HalfFull           ((uint32_t)0x00000002 << 3) 
N#define DMA_FIFOStatus_3QuartersFull      ((uint32_t)0x00000003 << 3)
N#define DMA_FIFOStatus_Empty              ((uint32_t)0x00000004 << 3)
N#define DMA_FIFOStatus_Full               ((uint32_t)0x00000005 << 3)
N
N#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
N                                    ((STATUS) == DMA_FIFOStatus_HalfFull)          || \
N                                    ((STATUS) == DMA_FIFOStatus_1QuarterFull)      || \
N                                    ((STATUS) == DMA_FIFOStatus_3QuartersFull)     || \
N                                    ((STATUS) == DMA_FIFOStatus_Full)              || \
N                                    ((STATUS) == DMA_FIFOStatus_Empty)) 
X#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) ||                                     ((STATUS) == DMA_FIFOStatus_HalfFull)          ||                                     ((STATUS) == DMA_FIFOStatus_1QuarterFull)      ||                                     ((STATUS) == DMA_FIFOStatus_3QuartersFull)     ||                                     ((STATUS) == DMA_FIFOStatus_Full)              ||                                     ((STATUS) == DMA_FIFOStatus_Empty)) 
N/**
N  * @}
N  */ 
N
N/** @defgroup DMA_flags_definition 
N  * @{
N  */
N#define DMA_FLAG_FEIF0                    ((uint32_t)0x10800001)
N#define DMA_FLAG_DMEIF0                   ((uint32_t)0x10800004)
N#define DMA_FLAG_TEIF0                    ((uint32_t)0x10000008)
N#define DMA_FLAG_HTIF0                    ((uint32_t)0x10000010)
N#define DMA_FLAG_TCIF0                    ((uint32_t)0x10000020)
N#define DMA_FLAG_FEIF1                    ((uint32_t)0x10000040)
N#define DMA_FLAG_DMEIF1                   ((uint32_t)0x10000100)
N#define DMA_FLAG_TEIF1                    ((uint32_t)0x10000200)
N#define DMA_FLAG_HTIF1                    ((uint32_t)0x10000400)
N#define DMA_FLAG_TCIF1                    ((uint32_t)0x10000800)
N#define DMA_FLAG_FEIF2                    ((uint32_t)0x10010000)
N#define DMA_FLAG_DMEIF2                   ((uint32_t)0x10040000)
N#define DMA_FLAG_TEIF2                    ((uint32_t)0x10080000)
N#define DMA_FLAG_HTIF2                    ((uint32_t)0x10100000)
N#define DMA_FLAG_TCIF2                    ((uint32_t)0x10200000)
N#define DMA_FLAG_FEIF3                    ((uint32_t)0x10400000)
N#define DMA_FLAG_DMEIF3                   ((uint32_t)0x11000000)
N#define DMA_FLAG_TEIF3                    ((uint32_t)0x12000000)
N#define DMA_FLAG_HTIF3                    ((uint32_t)0x14000000)
N#define DMA_FLAG_TCIF3                    ((uint32_t)0x18000000)
N#define DMA_FLAG_FEIF4                    ((uint32_t)0x20000001)
N#define DMA_FLAG_DMEIF4                   ((uint32_t)0x20000004)
N#define DMA_FLAG_TEIF4                    ((uint32_t)0x20000008)
N#define DMA_FLAG_HTIF4                    ((uint32_t)0x20000010)
N#define DMA_FLAG_TCIF4                    ((uint32_t)0x20000020)
N#define DMA_FLAG_FEIF5                    ((uint32_t)0x20000040)
N#define DMA_FLAG_DMEIF5                   ((uint32_t)0x20000100)
N#define DMA_FLAG_TEIF5                    ((uint32_t)0x20000200)
N#define DMA_FLAG_HTIF5                    ((uint32_t)0x20000400)
N#define DMA_FLAG_TCIF5                    ((uint32_t)0x20000800)
N#define DMA_FLAG_FEIF6                    ((uint32_t)0x20010000)
N#define DMA_FLAG_DMEIF6                   ((uint32_t)0x20040000)
N#define DMA_FLAG_TEIF6                    ((uint32_t)0x20080000)
N#define DMA_FLAG_HTIF6                    ((uint32_t)0x20100000)
N#define DMA_FLAG_TCIF6                    ((uint32_t)0x20200000)
N#define DMA_FLAG_FEIF7                    ((uint32_t)0x20400000)
N#define DMA_FLAG_DMEIF7                   ((uint32_t)0x21000000)
N#define DMA_FLAG_TEIF7                    ((uint32_t)0x22000000)
N#define DMA_FLAG_HTIF7                    ((uint32_t)0x24000000)
N#define DMA_FLAG_TCIF7                    ((uint32_t)0x28000000)
N
N#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
N                                 (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00))
X#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) &&                                  (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00))
N
N#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0)  || ((FLAG) == DMA_FLAG_HTIF0)  || \
N                               ((FLAG) == DMA_FLAG_TEIF0)  || ((FLAG) == DMA_FLAG_DMEIF0) || \
N                               ((FLAG) == DMA_FLAG_FEIF0)  || ((FLAG) == DMA_FLAG_TCIF1)  || \
N                               ((FLAG) == DMA_FLAG_HTIF1)  || ((FLAG) == DMA_FLAG_TEIF1)  || \
N                               ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1)  || \
N                               ((FLAG) == DMA_FLAG_TCIF2)  || ((FLAG) == DMA_FLAG_HTIF2)  || \
N                               ((FLAG) == DMA_FLAG_TEIF2)  || ((FLAG) == DMA_FLAG_DMEIF2) || \
N                               ((FLAG) == DMA_FLAG_FEIF2)  || ((FLAG) == DMA_FLAG_TCIF3)  || \
N                               ((FLAG) == DMA_FLAG_HTIF3)  || ((FLAG) == DMA_FLAG_TEIF3)  || \
N                               ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3)  || \
N                               ((FLAG) == DMA_FLAG_TCIF4)  || ((FLAG) == DMA_FLAG_HTIF4)  || \
N                               ((FLAG) == DMA_FLAG_TEIF4)  || ((FLAG) == DMA_FLAG_DMEIF4) || \
N                               ((FLAG) == DMA_FLAG_FEIF4)  || ((FLAG) == DMA_FLAG_TCIF5)  || \
N                               ((FLAG) == DMA_FLAG_HTIF5)  || ((FLAG) == DMA_FLAG_TEIF5)  || \
N                               ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5)  || \
N                               ((FLAG) == DMA_FLAG_TCIF6)  || ((FLAG) == DMA_FLAG_HTIF6)  || \
N                               ((FLAG) == DMA_FLAG_TEIF6)  || ((FLAG) == DMA_FLAG_DMEIF6) || \
N                               ((FLAG) == DMA_FLAG_FEIF6)  || ((FLAG) == DMA_FLAG_TCIF7)  || \
N                               ((FLAG) == DMA_FLAG_HTIF7)  || ((FLAG) == DMA_FLAG_TEIF7)  || \
N                               ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
X#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0)  || ((FLAG) == DMA_FLAG_HTIF0)  ||                                ((FLAG) == DMA_FLAG_TEIF0)  || ((FLAG) == DMA_FLAG_DMEIF0) ||                                ((FLAG) == DMA_FLAG_FEIF0)  || ((FLAG) == DMA_FLAG_TCIF1)  ||                                ((FLAG) == DMA_FLAG_HTIF1)  || ((FLAG) == DMA_FLAG_TEIF1)  ||                                ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1)  ||                                ((FLAG) == DMA_FLAG_TCIF2)  || ((FLAG) == DMA_FLAG_HTIF2)  ||                                ((FLAG) == DMA_FLAG_TEIF2)  || ((FLAG) == DMA_FLAG_DMEIF2) ||                                ((FLAG) == DMA_FLAG_FEIF2)  || ((FLAG) == DMA_FLAG_TCIF3)  ||                                ((FLAG) == DMA_FLAG_HTIF3)  || ((FLAG) == DMA_FLAG_TEIF3)  ||                                ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3)  ||                                ((FLAG) == DMA_FLAG_TCIF4)  || ((FLAG) == DMA_FLAG_HTIF4)  ||                                ((FLAG) == DMA_FLAG_TEIF4)  || ((FLAG) == DMA_FLAG_DMEIF4) ||                                ((FLAG) == DMA_FLAG_FEIF4)  || ((FLAG) == DMA_FLAG_TCIF5)  ||                                ((FLAG) == DMA_FLAG_HTIF5)  || ((FLAG) == DMA_FLAG_TEIF5)  ||                                ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5)  ||                                ((FLAG) == DMA_FLAG_TCIF6)  || ((FLAG) == DMA_FLAG_HTIF6)  ||                                ((FLAG) == DMA_FLAG_TEIF6)  || ((FLAG) == DMA_FLAG_DMEIF6) ||                                ((FLAG) == DMA_FLAG_FEIF6)  || ((FLAG) == DMA_FLAG_TCIF7)  ||                                ((FLAG) == DMA_FLAG_HTIF7)  || ((FLAG) == DMA_FLAG_TEIF7)  ||                                ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_interrupt_enable_definitions 
N  * @{
N  */ 
N#define DMA_IT_TC                         ((uint32_t)0x00000010)
N#define DMA_IT_HT                         ((uint32_t)0x00000008)
N#define DMA_IT_TE                         ((uint32_t)0x00000004)
N#define DMA_IT_DME                        ((uint32_t)0x00000002)
N#define DMA_IT_FE                         ((uint32_t)0x00000080)
N
N#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_interrupts_definitions 
N  * @{
N  */ 
N#define DMA_IT_FEIF0                      ((uint32_t)0x90000001)
N#define DMA_IT_DMEIF0                     ((uint32_t)0x10001004)
N#define DMA_IT_TEIF0                      ((uint32_t)0x10002008)
N#define DMA_IT_HTIF0                      ((uint32_t)0x10004010)
N#define DMA_IT_TCIF0                      ((uint32_t)0x10008020)
N#define DMA_IT_FEIF1                      ((uint32_t)0x90000040)
N#define DMA_IT_DMEIF1                     ((uint32_t)0x10001100)
N#define DMA_IT_TEIF1                      ((uint32_t)0x10002200)
N#define DMA_IT_HTIF1                      ((uint32_t)0x10004400)
N#define DMA_IT_TCIF1                      ((uint32_t)0x10008800)
N#define DMA_IT_FEIF2                      ((uint32_t)0x90010000)
N#define DMA_IT_DMEIF2                     ((uint32_t)0x10041000)
N#define DMA_IT_TEIF2                      ((uint32_t)0x10082000)
N#define DMA_IT_HTIF2                      ((uint32_t)0x10104000)
N#define DMA_IT_TCIF2                      ((uint32_t)0x10208000)
N#define DMA_IT_FEIF3                      ((uint32_t)0x90400000)
N#define DMA_IT_DMEIF3                     ((uint32_t)0x11001000)
N#define DMA_IT_TEIF3                      ((uint32_t)0x12002000)
N#define DMA_IT_HTIF3                      ((uint32_t)0x14004000)
N#define DMA_IT_TCIF3                      ((uint32_t)0x18008000)
N#define DMA_IT_FEIF4                      ((uint32_t)0xA0000001)
N#define DMA_IT_DMEIF4                     ((uint32_t)0x20001004)
N#define DMA_IT_TEIF4                      ((uint32_t)0x20002008)
N#define DMA_IT_HTIF4                      ((uint32_t)0x20004010)
N#define DMA_IT_TCIF4                      ((uint32_t)0x20008020)
N#define DMA_IT_FEIF5                      ((uint32_t)0xA0000040)
N#define DMA_IT_DMEIF5                     ((uint32_t)0x20001100)
N#define DMA_IT_TEIF5                      ((uint32_t)0x20002200)
N#define DMA_IT_HTIF5                      ((uint32_t)0x20004400)
N#define DMA_IT_TCIF5                      ((uint32_t)0x20008800)
N#define DMA_IT_FEIF6                      ((uint32_t)0xA0010000)
N#define DMA_IT_DMEIF6                     ((uint32_t)0x20041000)
N#define DMA_IT_TEIF6                      ((uint32_t)0x20082000)
N#define DMA_IT_HTIF6                      ((uint32_t)0x20104000)
N#define DMA_IT_TCIF6                      ((uint32_t)0x20208000)
N#define DMA_IT_FEIF7                      ((uint32_t)0xA0400000)
N#define DMA_IT_DMEIF7                     ((uint32_t)0x21001000)
N#define DMA_IT_TEIF7                      ((uint32_t)0x22002000)
N#define DMA_IT_HTIF7                      ((uint32_t)0x24004000)
N#define DMA_IT_TCIF7                      ((uint32_t)0x28008000)
N
N#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
N                             (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
N                             (((IT) & 0x40820082) == 0x00))
X#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) &&                              (((IT) & 0x30000000) != 0) && ((IT) != 0x00) &&                              (((IT) & 0x40820082) == 0x00))
N
N#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0)  || \
N                           ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
N                           ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1)  || \
N                           ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1)  || \
N                           ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1)  || \
N                           ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2)  || \
N                           ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
N                           ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3)  || \
N                           ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3)  || \
N                           ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3)  || \
N                           ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4)  || \
N                           ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
N                           ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5)  || \
N                           ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5)  || \
N                           ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5)  || \
N                           ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6)  || \
N                           ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
N                           ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7)  || \
N                           ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7)  || \
N                           ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
X#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0)  ||                            ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) ||                            ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1)  ||                            ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1)  ||                            ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1)  ||                            ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2)  ||                            ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) ||                            ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3)  ||                            ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3)  ||                            ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3)  ||                            ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4)  ||                            ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) ||                            ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5)  ||                            ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5)  ||                            ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5)  ||                            ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6)  ||                            ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) ||                            ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7)  ||                            ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7)  ||                            ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_peripheral_increment_offset 
N  * @{
N  */ 
N#define DMA_PINCOS_Psize                  ((uint32_t)0x00000000)
N#define DMA_PINCOS_WordAligned            ((uint32_t)0x00008000)
N
N#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
N                                  ((SIZE) == DMA_PINCOS_WordAligned))
X#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) ||                                   ((SIZE) == DMA_PINCOS_WordAligned))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_flow_controller_definitions 
N  * @{
N  */ 
N#define DMA_FlowCtrl_Memory               ((uint32_t)0x00000000)
N#define DMA_FlowCtrl_Peripheral           ((uint32_t)0x00000020)
N
N#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
N                                ((CTRL) == DMA_FlowCtrl_Peripheral))
X#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) ||                                 ((CTRL) == DMA_FlowCtrl_Peripheral))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DMA_memory_targets_definitions 
N  * @{
N  */ 
N#define DMA_Memory_0                      ((uint32_t)0x00000000)
N#define DMA_Memory_1                      ((uint32_t)0x00080000)
N
N#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N
N/*  Function used to set the DMA configuration to the default reset state *****/ 
Nvoid DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
N
N/* Initialization and Configuration functions *********************************/
Nvoid DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
Nvoid DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
Nvoid DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
N
N/* Optional Configuration functions *******************************************/
Nvoid DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
Nvoid DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
N
N/* Data Counter functions *****************************************************/
Nvoid DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
Nuint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
N
N/* Double Buffer mode functions ***********************************************/
Nvoid DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
N                                uint32_t DMA_CurrentMemory);
Nvoid DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
Nvoid DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
N                            uint32_t DMA_MemoryTarget);
Nuint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
N
N/* Interrupts and flags management functions **********************************/
NFunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
Nuint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
NFlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
Nvoid DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
Nvoid DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
NITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
Nvoid DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_DMA_H */
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 38 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_exti.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_exti.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_exti.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the EXTI firmware
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_EXTI_H
N#define __STM32F4xx_EXTI_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup EXTI
N  * @{
N  */
N
N/* Exported types ------------------------------------------------------------*/
N
N/** 
N  * @brief  EXTI mode enumeration  
N  */
N
Ntypedef enum
N{
N  EXTI_Mode_Interrupt = 0x00,
N  EXTI_Mode_Event = 0x04
N}EXTIMode_TypeDef;
N
N#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
N
N/** 
N  * @brief  EXTI Trigger enumeration  
N  */
N
Ntypedef enum
N{
N  EXTI_Trigger_Rising = 0x08,
N  EXTI_Trigger_Falling = 0x0C,  
N  EXTI_Trigger_Rising_Falling = 0x10
N}EXTITrigger_TypeDef;
N
N#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
N                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
N                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
X#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) ||                                   ((TRIGGER) == EXTI_Trigger_Falling) ||                                   ((TRIGGER) == EXTI_Trigger_Rising_Falling))
N/** 
N  * @brief  EXTI Init Structure definition  
N  */
N
Ntypedef struct
N{
N  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
N                                         This parameter can be any combination value of @ref EXTI_Lines */
N   
N  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
N                                         This parameter can be a value of @ref EXTIMode_TypeDef */
N
N  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
N                                         This parameter can be a value of @ref EXTITrigger_TypeDef */
N
N  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
N                                         This parameter can be set either to ENABLE or DISABLE */ 
N}EXTI_InitTypeDef;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup EXTI_Exported_Constants
N  * @{
N  */
N
N/** @defgroup EXTI_Lines 
N  * @{
N  */
N
N#define EXTI_Line0       ((uint32_t)0x00001)     /*!< External interrupt line 0 */
N#define EXTI_Line1       ((uint32_t)0x00002)     /*!< External interrupt line 1 */
N#define EXTI_Line2       ((uint32_t)0x00004)     /*!< External interrupt line 2 */
N#define EXTI_Line3       ((uint32_t)0x00008)     /*!< External interrupt line 3 */
N#define EXTI_Line4       ((uint32_t)0x00010)     /*!< External interrupt line 4 */
N#define EXTI_Line5       ((uint32_t)0x00020)     /*!< External interrupt line 5 */
N#define EXTI_Line6       ((uint32_t)0x00040)     /*!< External interrupt line 6 */
N#define EXTI_Line7       ((uint32_t)0x00080)     /*!< External interrupt line 7 */
N#define EXTI_Line8       ((uint32_t)0x00100)     /*!< External interrupt line 8 */
N#define EXTI_Line9       ((uint32_t)0x00200)     /*!< External interrupt line 9 */
N#define EXTI_Line10      ((uint32_t)0x00400)     /*!< External interrupt line 10 */
N#define EXTI_Line11      ((uint32_t)0x00800)     /*!< External interrupt line 11 */
N#define EXTI_Line12      ((uint32_t)0x01000)     /*!< External interrupt line 12 */
N#define EXTI_Line13      ((uint32_t)0x02000)     /*!< External interrupt line 13 */
N#define EXTI_Line14      ((uint32_t)0x04000)     /*!< External interrupt line 14 */
N#define EXTI_Line15      ((uint32_t)0x08000)     /*!< External interrupt line 15 */
N#define EXTI_Line16      ((uint32_t)0x10000)     /*!< External interrupt line 16 Connected to the PVD Output */
N#define EXTI_Line17      ((uint32_t)0x20000)     /*!< External interrupt line 17 Connected to the RTC Alarm event */
N#define EXTI_Line18      ((uint32_t)0x40000)     /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */                                    
N#define EXTI_Line19      ((uint32_t)0x80000)     /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
N#define EXTI_Line20      ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event  */
N#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */                                               
N#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< External interrupt line 22 Connected to the RTC Wakeup event */                                               
N                                          
N#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
N
N#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
N                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
N                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
N                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
N                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
N                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
N                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
N                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
N                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
N                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
N                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
N                                ((LINE) == EXTI_Line22))
X#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) ||                                 ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) ||                                 ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) ||                                 ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) ||                                 ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) ||                                 ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) ||                                 ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) ||                                 ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) ||                                 ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) ||                                 ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) ||                                 ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||                                ((LINE) == EXTI_Line22))
N                    
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/
N
N/*  Function used to set the EXTI configuration to the default reset state *****/
Nvoid EXTI_DeInit(void);
N
N/* Initialization and Configuration functions *********************************/
Nvoid EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
Nvoid EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
Nvoid EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
N
N/* Interrupts and flags management functions **********************************/
NFlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
Nvoid EXTI_ClearFlag(uint32_t EXTI_Line);
NITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
Nvoid EXTI_ClearITPendingBit(uint32_t EXTI_Line);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __STM32F4xx_EXTI_H */
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 39 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_flash.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_flash.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_flash.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the FLASH 
N  *          firmware library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_FLASH_H
N#define __STM32F4xx_FLASH_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup FLASH
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N/** 
N  * @brief FLASH Status  
N  */ 
Ntypedef enum
N{ 
N  FLASH_BUSY = 1,
N  FLASH_ERROR_RD,
N  FLASH_ERROR_PGS,
N  FLASH_ERROR_PGP,
N  FLASH_ERROR_PGA,
N  FLASH_ERROR_WRP,
N  FLASH_ERROR_PROGRAM,
N  FLASH_ERROR_OPERATION,
N  FLASH_COMPLETE
N}FLASH_Status;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup FLASH_Exported_Constants
N  * @{
N  */  
N
N/** @defgroup Flash_Latency 
N  * @{
N  */ 
N#define FLASH_Latency_0                ((uint8_t)0x0000)  /*!< FLASH Zero Latency cycle      */
N#define FLASH_Latency_1                ((uint8_t)0x0001)  /*!< FLASH One Latency cycle       */
N#define FLASH_Latency_2                ((uint8_t)0x0002)  /*!< FLASH Two Latency cycles      */
N#define FLASH_Latency_3                ((uint8_t)0x0003)  /*!< FLASH Three Latency cycles    */
N#define FLASH_Latency_4                ((uint8_t)0x0004)  /*!< FLASH Four Latency cycles     */
N#define FLASH_Latency_5                ((uint8_t)0x0005)  /*!< FLASH Five Latency cycles     */
N#define FLASH_Latency_6                ((uint8_t)0x0006)  /*!< FLASH Six Latency cycles      */
N#define FLASH_Latency_7                ((uint8_t)0x0007)  /*!< FLASH Seven Latency cycles    */
N#define FLASH_Latency_8                ((uint8_t)0x0008)  /*!< FLASH Eight Latency cycles    */
N#define FLASH_Latency_9                ((uint8_t)0x0009)  /*!< FLASH Nine Latency cycles     */
N#define FLASH_Latency_10               ((uint8_t)0x000A)  /*!< FLASH Ten Latency cycles      */
N#define FLASH_Latency_11               ((uint8_t)0x000B)  /*!< FLASH Eleven Latency cycles   */
N#define FLASH_Latency_12               ((uint8_t)0x000C)  /*!< FLASH Twelve Latency cycles   */
N#define FLASH_Latency_13               ((uint8_t)0x000D)  /*!< FLASH Thirteen Latency cycles */
N#define FLASH_Latency_14               ((uint8_t)0x000E)  /*!< FLASH Fourteen Latency cycles */
N#define FLASH_Latency_15               ((uint8_t)0x000F)  /*!< FLASH Fifteen Latency cycles  */
N
N
N#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0)  || \
N                                   ((LATENCY) == FLASH_Latency_1)  || \
N                                   ((LATENCY) == FLASH_Latency_2)  || \
N                                   ((LATENCY) == FLASH_Latency_3)  || \
N                                   ((LATENCY) == FLASH_Latency_4)  || \
N                                   ((LATENCY) == FLASH_Latency_5)  || \
N                                   ((LATENCY) == FLASH_Latency_6)  || \
N                                   ((LATENCY) == FLASH_Latency_7)  || \
N                                   ((LATENCY) == FLASH_Latency_8)  || \
N                                   ((LATENCY) == FLASH_Latency_9)  || \
N                                   ((LATENCY) == FLASH_Latency_10) || \
N                                   ((LATENCY) == FLASH_Latency_11) || \
N                                   ((LATENCY) == FLASH_Latency_12) || \
N                                   ((LATENCY) == FLASH_Latency_13) || \
N                                   ((LATENCY) == FLASH_Latency_14) || \
N                                   ((LATENCY) == FLASH_Latency_15))
X#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0)  ||                                    ((LATENCY) == FLASH_Latency_1)  ||                                    ((LATENCY) == FLASH_Latency_2)  ||                                    ((LATENCY) == FLASH_Latency_3)  ||                                    ((LATENCY) == FLASH_Latency_4)  ||                                    ((LATENCY) == FLASH_Latency_5)  ||                                    ((LATENCY) == FLASH_Latency_6)  ||                                    ((LATENCY) == FLASH_Latency_7)  ||                                    ((LATENCY) == FLASH_Latency_8)  ||                                    ((LATENCY) == FLASH_Latency_9)  ||                                    ((LATENCY) == FLASH_Latency_10) ||                                    ((LATENCY) == FLASH_Latency_11) ||                                    ((LATENCY) == FLASH_Latency_12) ||                                    ((LATENCY) == FLASH_Latency_13) ||                                    ((LATENCY) == FLASH_Latency_14) ||                                    ((LATENCY) == FLASH_Latency_15))
N/**
N  * @}
N  */ 
N
N/** @defgroup FLASH_Voltage_Range 
N  * @{
N  */ 
N#define VoltageRange_1        ((uint8_t)0x00)  /*!< Device operating range: 1.8V to 2.1V */
N#define VoltageRange_2        ((uint8_t)0x01)  /*!<Device operating range: 2.1V to 2.7V */
N#define VoltageRange_3        ((uint8_t)0x02)  /*!<Device operating range: 2.7V to 3.6V */
N#define VoltageRange_4        ((uint8_t)0x03)  /*!<Device operating range: 2.7V to 3.6V + External Vpp */
N
N#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
N                               ((RANGE) == VoltageRange_2) || \
N                               ((RANGE) == VoltageRange_3) || \
N                               ((RANGE) == VoltageRange_4))
X#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) ||                                ((RANGE) == VoltageRange_2) ||                                ((RANGE) == VoltageRange_3) ||                                ((RANGE) == VoltageRange_4))
N/**
N  * @}
N  */ 
N
N/** @defgroup FLASH_Sectors
N  * @{
N  */
N#define FLASH_Sector_0     ((uint16_t)0x0000) /*!< Sector Number 0   */
N#define FLASH_Sector_1     ((uint16_t)0x0008) /*!< Sector Number 1   */
N#define FLASH_Sector_2     ((uint16_t)0x0010) /*!< Sector Number 2   */
N#define FLASH_Sector_3     ((uint16_t)0x0018) /*!< Sector Number 3   */
N#define FLASH_Sector_4     ((uint16_t)0x0020) /*!< Sector Number 4   */
N#define FLASH_Sector_5     ((uint16_t)0x0028) /*!< Sector Number 5   */
N#define FLASH_Sector_6     ((uint16_t)0x0030) /*!< Sector Number 6   */
N#define FLASH_Sector_7     ((uint16_t)0x0038) /*!< Sector Number 7   */
N#define FLASH_Sector_8     ((uint16_t)0x0040) /*!< Sector Number 8   */
N#define FLASH_Sector_9     ((uint16_t)0x0048) /*!< Sector Number 9   */
N#define FLASH_Sector_10    ((uint16_t)0x0050) /*!< Sector Number 10  */
N#define FLASH_Sector_11    ((uint16_t)0x0058) /*!< Sector Number 11  */
N#define FLASH_Sector_12    ((uint16_t)0x0080) /*!< Sector Number 12  */
N#define FLASH_Sector_13    ((uint16_t)0x0088) /*!< Sector Number 13  */
N#define FLASH_Sector_14    ((uint16_t)0x0090) /*!< Sector Number 14  */
N#define FLASH_Sector_15    ((uint16_t)0x0098) /*!< Sector Number 15  */
N#define FLASH_Sector_16    ((uint16_t)0x00A0) /*!< Sector Number 16  */
N#define FLASH_Sector_17    ((uint16_t)0x00A8) /*!< Sector Number 17  */
N#define FLASH_Sector_18    ((uint16_t)0x00B0) /*!< Sector Number 18  */
N#define FLASH_Sector_19    ((uint16_t)0x00B8) /*!< Sector Number 19  */
N#define FLASH_Sector_20    ((uint16_t)0x00C0) /*!< Sector Number 20  */
N#define FLASH_Sector_21    ((uint16_t)0x00C8) /*!< Sector Number 21  */
N#define FLASH_Sector_22    ((uint16_t)0x00D0) /*!< Sector Number 22  */
N#define FLASH_Sector_23    ((uint16_t)0x00D8) /*!< Sector Number 23  */
N
N#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0)   || ((SECTOR) == FLASH_Sector_1)   ||\
N                                 ((SECTOR) == FLASH_Sector_2)   || ((SECTOR) == FLASH_Sector_3)   ||\
N                                 ((SECTOR) == FLASH_Sector_4)   || ((SECTOR) == FLASH_Sector_5)   ||\
N                                 ((SECTOR) == FLASH_Sector_6)   || ((SECTOR) == FLASH_Sector_7)   ||\
N                                 ((SECTOR) == FLASH_Sector_8)   || ((SECTOR) == FLASH_Sector_9)   ||\
N                                 ((SECTOR) == FLASH_Sector_10)  || ((SECTOR) == FLASH_Sector_11)  ||\
N                                 ((SECTOR) == FLASH_Sector_12)  || ((SECTOR) == FLASH_Sector_13)  ||\
N                                 ((SECTOR) == FLASH_Sector_14)  || ((SECTOR) == FLASH_Sector_15)  ||\
N                                 ((SECTOR) == FLASH_Sector_16)  || ((SECTOR) == FLASH_Sector_17)  ||\
N                                 ((SECTOR) == FLASH_Sector_18)  || ((SECTOR) == FLASH_Sector_19)  ||\
N                                 ((SECTOR) == FLASH_Sector_20)  || ((SECTOR) == FLASH_Sector_21)  ||\
N                                 ((SECTOR) == FLASH_Sector_22)  || ((SECTOR) == FLASH_Sector_23))
X#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0)   || ((SECTOR) == FLASH_Sector_1)   ||                                 ((SECTOR) == FLASH_Sector_2)   || ((SECTOR) == FLASH_Sector_3)   ||                                 ((SECTOR) == FLASH_Sector_4)   || ((SECTOR) == FLASH_Sector_5)   ||                                 ((SECTOR) == FLASH_Sector_6)   || ((SECTOR) == FLASH_Sector_7)   ||                                 ((SECTOR) == FLASH_Sector_8)   || ((SECTOR) == FLASH_Sector_9)   ||                                 ((SECTOR) == FLASH_Sector_10)  || ((SECTOR) == FLASH_Sector_11)  ||                                 ((SECTOR) == FLASH_Sector_12)  || ((SECTOR) == FLASH_Sector_13)  ||                                 ((SECTOR) == FLASH_Sector_14)  || ((SECTOR) == FLASH_Sector_15)  ||                                 ((SECTOR) == FLASH_Sector_16)  || ((SECTOR) == FLASH_Sector_17)  ||                                 ((SECTOR) == FLASH_Sector_18)  || ((SECTOR) == FLASH_Sector_19)  ||                                 ((SECTOR) == FLASH_Sector_20)  || ((SECTOR) == FLASH_Sector_21)  ||                                 ((SECTOR) == FLASH_Sector_22)  || ((SECTOR) == FLASH_Sector_23))
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
X#if 0L || 0L
S#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\
S                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))  
X#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))  
N#endif /* STM32F427_437xx || STM32F429_439xx */
N
N#if defined (STM32F40_41xxx)
X#if 1L
N#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\
N                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) 
X#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) 
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F401xx)
X#if 0L
S#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\
S                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
X#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
N#endif /* STM32F401xx */
N
N#if defined (STM32F411xE) || defined (STM32F446xx)
X#if 0L || 0L
S#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\
S                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
X#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
N#endif /* STM32F411xE */
N
N/**
N  * @}
N  */ 
N
N/** @defgroup Option_Bytes_Write_Protection 
N  * @{
N  */ 
N#define OB_WRP_Sector_0       ((uint32_t)0x00000001) /*!< Write protection of Sector0     */
N#define OB_WRP_Sector_1       ((uint32_t)0x00000002) /*!< Write protection of Sector1     */
N#define OB_WRP_Sector_2       ((uint32_t)0x00000004) /*!< Write protection of Sector2     */
N#define OB_WRP_Sector_3       ((uint32_t)0x00000008) /*!< Write protection of Sector3     */
N#define OB_WRP_Sector_4       ((uint32_t)0x00000010) /*!< Write protection of Sector4     */
N#define OB_WRP_Sector_5       ((uint32_t)0x00000020) /*!< Write protection of Sector5     */
N#define OB_WRP_Sector_6       ((uint32_t)0x00000040) /*!< Write protection of Sector6     */
N#define OB_WRP_Sector_7       ((uint32_t)0x00000080) /*!< Write protection of Sector7     */
N#define OB_WRP_Sector_8       ((uint32_t)0x00000100) /*!< Write protection of Sector8     */
N#define OB_WRP_Sector_9       ((uint32_t)0x00000200) /*!< Write protection of Sector9     */
N#define OB_WRP_Sector_10      ((uint32_t)0x00000400) /*!< Write protection of Sector10    */
N#define OB_WRP_Sector_11      ((uint32_t)0x00000800) /*!< Write protection of Sector11    */
N#define OB_WRP_Sector_12      ((uint32_t)0x00000001) /*!< Write protection of Sector12    */
N#define OB_WRP_Sector_13      ((uint32_t)0x00000002) /*!< Write protection of Sector13    */
N#define OB_WRP_Sector_14      ((uint32_t)0x00000004) /*!< Write protection of Sector14    */
N#define OB_WRP_Sector_15      ((uint32_t)0x00000008) /*!< Write protection of Sector15    */
N#define OB_WRP_Sector_16      ((uint32_t)0x00000010) /*!< Write protection of Sector16    */
N#define OB_WRP_Sector_17      ((uint32_t)0x00000020) /*!< Write protection of Sector17    */
N#define OB_WRP_Sector_18      ((uint32_t)0x00000040) /*!< Write protection of Sector18    */
N#define OB_WRP_Sector_19      ((uint32_t)0x00000080) /*!< Write protection of Sector19    */
N#define OB_WRP_Sector_20      ((uint32_t)0x00000100) /*!< Write protection of Sector20    */
N#define OB_WRP_Sector_21      ((uint32_t)0x00000200) /*!< Write protection of Sector21    */
N#define OB_WRP_Sector_22      ((uint32_t)0x00000400) /*!< Write protection of Sector22    */
N#define OB_WRP_Sector_23      ((uint32_t)0x00000800) /*!< Write protection of Sector23    */
N#define OB_WRP_Sector_All     ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
N
N#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
N/**
N  * @}
N  */
N
N/** @defgroup  Selection_Protection_Mode
N  * @{
N  */
N#define OB_PcROP_Disable   ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
N#define OB_PcROP_Enable    ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i   */
N#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable))
N/**
N  * @}
N  */
N
N/** @defgroup Option_Bytes_PC_ReadWrite_Protection 
N  * @{
N  */ 
N#define OB_PCROP_Sector_0        ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0      */
N#define OB_PCROP_Sector_1        ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1      */
N#define OB_PCROP_Sector_2        ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2      */
N#define OB_PCROP_Sector_3        ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3      */
N#define OB_PCROP_Sector_4        ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4      */
N#define OB_PCROP_Sector_5        ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5      */
N#define OB_PCROP_Sector_6        ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6      */
N#define OB_PCROP_Sector_7        ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7      */
N#define OB_PCROP_Sector_8        ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8      */
N#define OB_PCROP_Sector_9        ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9      */
N#define OB_PCROP_Sector_10       ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10     */
N#define OB_PCROP_Sector_11       ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11     */
N#define OB_PCROP_Sector_12       ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12     */
N#define OB_PCROP_Sector_13       ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13     */
N#define OB_PCROP_Sector_14       ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14     */
N#define OB_PCROP_Sector_15       ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15     */
N#define OB_PCROP_Sector_16       ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16     */
N#define OB_PCROP_Sector_17       ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17     */
N#define OB_PCROP_Sector_18       ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18     */
N#define OB_PCROP_Sector_19       ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19     */
N#define OB_PCROP_Sector_20       ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20     */
N#define OB_PCROP_Sector_21       ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21     */
N#define OB_PCROP_Sector_22       ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22     */
N#define OB_PCROP_Sector_23       ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23     */
N#define OB_PCROP_Sector_All      ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors  */
N
N#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
N/**
N  * @}
N  */
N
N/** @defgroup FLASH_Option_Bytes_Read_Protection 
N  * @{
N  */
N#define OB_RDP_Level_0   ((uint8_t)0xAA)
N#define OB_RDP_Level_1   ((uint8_t)0x55)
N/*#define OB_RDP_Level_2   ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 
N                                                  it's no more possible to go back to level 1 or 0 */
N#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
N                          ((LEVEL) == OB_RDP_Level_1))/*||\
N                          ((LEVEL) == OB_RDP_Level_2))*/
X#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||                          ((LEVEL) == OB_RDP_Level_1)) 
N/**
N  * @}
N  */ 
N
N/** @defgroup FLASH_Option_Bytes_IWatchdog 
N  * @{
N  */ 
N#define OB_IWDG_SW                     ((uint8_t)0x20)  /*!< Software IWDG selected */
N#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
N#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
N/**
N  * @}
N  */ 
N
N/** @defgroup FLASH_Option_Bytes_nRST_STOP 
N  * @{
N  */ 
N#define OB_STOP_NoRST                  ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
N#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
N#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup FLASH_Option_Bytes_nRST_STDBY 
N  * @{
N  */ 
N#define OB_STDBY_NoRST                 ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
N#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
N#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
N/**
N  * @}
N  */
N  
N/** @defgroup FLASH_BOR_Reset_Level 
N  * @{
N  */  
N#define OB_BOR_LEVEL3          ((uint8_t)0x00)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
N#define OB_BOR_LEVEL2          ((uint8_t)0x04)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
N#define OB_BOR_LEVEL1          ((uint8_t)0x08)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
N#define OB_BOR_OFF             ((uint8_t)0x0C)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
N#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
N                          ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
X#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||                          ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
N/**
N  * @}
N  */
N  
N/** @defgroup FLASH_Dual_Boot
N  * @{
N  */
N#define OB_Dual_BootEnabled   ((uint8_t)0x10) /*!< Dual Bank Boot Enable                             */
N#define OB_Dual_BootDisabled  ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
N#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled))
N/**
N  * @}
N  */
N
N/** @defgroup FLASH_Interrupts 
N  * @{
N  */ 
N#define FLASH_IT_EOP                   ((uint32_t)0x01000000)  /*!< End of FLASH Operation Interrupt source */
N#define FLASH_IT_ERR                   ((uint32_t)0x02000000)  /*!< Error Interrupt source */
N#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
N/**
N  * @}
N  */ 
N
N/** @defgroup FLASH_Flags 
N  * @{
N  */ 
N#define FLASH_FLAG_EOP                 ((uint32_t)0x00000001)  /*!< FLASH End of Operation flag               */
N#define FLASH_FLAG_OPERR               ((uint32_t)0x00000002)  /*!< FLASH operation Error flag                */
N#define FLASH_FLAG_WRPERR              ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag          */
N#define FLASH_FLAG_PGAERR              ((uint32_t)0x00000020)  /*!< FLASH Programming Alignment error flag    */
N#define FLASH_FLAG_PGPERR              ((uint32_t)0x00000040)  /*!< FLASH Programming Parallelism error flag  */
N#define FLASH_FLAG_PGSERR              ((uint32_t)0x00000080)  /*!< FLASH Programming Sequence error flag     */
N#define FLASH_FLAG_RDERR               ((uint32_t)0x00000100)  /*!< Read Protection error flag (PCROP)        */
N#define FLASH_FLAG_BSY                 ((uint32_t)0x00010000)  /*!< FLASH Busy flag                           */ 
N#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
N#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_EOP)    || ((FLAG) == FLASH_FLAG_OPERR)  || \
N                                  ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
N                                  ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
N                                  ((FLAG) == FLASH_FLAG_BSY)    || ((FLAG) == FLASH_FLAG_RDERR))
X#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_EOP)    || ((FLAG) == FLASH_FLAG_OPERR)  ||                                   ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) ||                                   ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) ||                                   ((FLAG) == FLASH_FLAG_BSY)    || ((FLAG) == FLASH_FLAG_RDERR))
N/**
N  * @}
N  */
N
N/** @defgroup FLASH_Program_Parallelism   
N  * @{
N  */
N#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000)
N#define FLASH_PSIZE_HALF_WORD      ((uint32_t)0x00000100)
N#define FLASH_PSIZE_WORD           ((uint32_t)0x00000200)
N#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)0x00000300)
N#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFF)
N/**
N  * @}
N  */ 
N
N/** @defgroup FLASH_Keys 
N  * @{
N  */ 
N#define RDP_KEY                  ((uint16_t)0x00A5)
N#define FLASH_KEY1               ((uint32_t)0x45670123)
N#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
N#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3B)
N#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7F)
N/**
N  * @}
N  */ 
N
N/** 
N  * @brief   ACR register byte 0 (Bits[7:0]) base address  
N  */ 
N#define ACR_BYTE0_ADDRESS           ((uint32_t)0x40023C00) 
N/** 
N  * @brief   OPTCR register byte 0 (Bits[7:0]) base address  
N  */ 
N#define OPTCR_BYTE0_ADDRESS         ((uint32_t)0x40023C14)
N/** 
N  * @brief   OPTCR register byte 1 (Bits[15:8]) base address  
N  */ 
N#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)
N/** 
N  * @brief   OPTCR register byte 2 (Bits[23:16]) base address  
N  */ 
N#define OPTCR_BYTE2_ADDRESS         ((uint32_t)0x40023C16)
N/** 
N  * @brief   OPTCR register byte 3 (Bits[31:24]) base address  
N  */ 
N#define OPTCR_BYTE3_ADDRESS         ((uint32_t)0x40023C17)
N
N/** 
N  * @brief   OPTCR1 register byte 0 (Bits[7:0]) base address  
N  */ 
N#define OPTCR1_BYTE2_ADDRESS         ((uint32_t)0x40023C1A)
N
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N 
N/* FLASH Interface configuration functions ************************************/
Nvoid FLASH_SetLatency(uint32_t FLASH_Latency);
Nvoid FLASH_PrefetchBufferCmd(FunctionalState NewState);
Nvoid FLASH_InstructionCacheCmd(FunctionalState NewState);
Nvoid FLASH_DataCacheCmd(FunctionalState NewState);
Nvoid FLASH_InstructionCacheReset(void);
Nvoid FLASH_DataCacheReset(void);
N
N/* FLASH Memory Programming functions *****************************************/   
Nvoid         FLASH_Unlock(void);
Nvoid         FLASH_Lock(void);
NFLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
NFLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
NFLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange);
NFLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange);
NFLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
NFLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
NFLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
NFLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
N
N/* Option Bytes Programming functions *****************************************/ 
Nvoid         FLASH_OB_Unlock(void);
Nvoid         FLASH_OB_Lock(void);
Nvoid         FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
Nvoid         FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState);
Nvoid         FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP);
Nvoid         FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState);
Nvoid         FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState);
Nvoid         FLASH_OB_RDPConfig(uint8_t OB_RDP);
Nvoid         FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
Nvoid         FLASH_OB_BORConfig(uint8_t OB_BOR);
Nvoid         FLASH_OB_BootConfig(uint8_t OB_BOOT);
NFLASH_Status FLASH_OB_Launch(void);
Nuint8_t      FLASH_OB_GetUser(void);
Nuint16_t     FLASH_OB_GetWRP(void);
Nuint16_t     FLASH_OB_GetWRP1(void);
Nuint16_t     FLASH_OB_GetPCROP(void);
Nuint16_t     FLASH_OB_GetPCROP1(void);
NFlagStatus   FLASH_OB_GetRDP(void);
Nuint8_t      FLASH_OB_GetBOR(void);
N
N/* Interrupts and flags management functions **********************************/
Nvoid         FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
NFlagStatus   FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
Nvoid         FLASH_ClearFlag(uint32_t FLASH_FLAG);
NFLASH_Status FLASH_GetStatus(void);
NFLASH_Status FLASH_WaitForLastOperation(void);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __STM32F4xx_FLASH_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 40 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_gpio.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_gpio.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_gpio.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the GPIO firmware
N  *          library.  
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_GPIO_H
N#define __STM32F4xx_GPIO_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup GPIO
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N
N#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
N                                    ((PERIPH) == GPIOB) || \
N                                    ((PERIPH) == GPIOC) || \
N                                    ((PERIPH) == GPIOD) || \
N                                    ((PERIPH) == GPIOE) || \
N                                    ((PERIPH) == GPIOF) || \
N                                    ((PERIPH) == GPIOG) || \
N                                    ((PERIPH) == GPIOH) || \
N                                    ((PERIPH) == GPIOI) || \
N                                    ((PERIPH) == GPIOJ) || \
N                                    ((PERIPH) == GPIOK))
X#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) ||                                     ((PERIPH) == GPIOB) ||                                     ((PERIPH) == GPIOC) ||                                     ((PERIPH) == GPIOD) ||                                     ((PERIPH) == GPIOE) ||                                     ((PERIPH) == GPIOF) ||                                     ((PERIPH) == GPIOG) ||                                     ((PERIPH) == GPIOH) ||                                     ((PERIPH) == GPIOI) ||                                     ((PERIPH) == GPIOJ) ||                                     ((PERIPH) == GPIOK))
N
N/** 
N  * @brief  GPIO Configuration Mode enumeration 
N  */   
Ntypedef enum
N{ 
N  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */
N  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */
N  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
N  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog Mode */
N}GPIOMode_TypeDef;
N#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) || \
N                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
X#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) ||                             ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
N
N/** 
N  * @brief  GPIO Output type enumeration 
N  */  
Ntypedef enum
N{ 
N  GPIO_OType_PP = 0x00,
N  GPIO_OType_OD = 0x01
N}GPIOOType_TypeDef;
N#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
N
N
N/** 
N  * @brief  GPIO Output Maximum frequency enumeration 
N  */  
Ntypedef enum
N{ 
N  GPIO_Low_Speed     = 0x00, /*!< Low speed    */
N  GPIO_Medium_Speed  = 0x01, /*!< Medium speed */
N  GPIO_Fast_Speed    = 0x02, /*!< Fast speed   */
N  GPIO_High_Speed    = 0x03  /*!< High speed   */
N}GPIOSpeed_TypeDef;
N
N/* Add legacy definition */
N#define  GPIO_Speed_2MHz    GPIO_Low_Speed    
N#define  GPIO_Speed_25MHz   GPIO_Medium_Speed 
N#define  GPIO_Speed_50MHz   GPIO_Fast_Speed 
N#define  GPIO_Speed_100MHz  GPIO_High_Speed  
N  
N#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
N                              ((SPEED) == GPIO_Fast_Speed)||  ((SPEED) == GPIO_High_Speed)) 
X#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) ||                               ((SPEED) == GPIO_Fast_Speed)||  ((SPEED) == GPIO_High_Speed)) 
N
N/** 
N  * @brief  GPIO Configuration PullUp PullDown enumeration 
N  */ 
Ntypedef enum
N{ 
N  GPIO_PuPd_NOPULL = 0x00,
N  GPIO_PuPd_UP     = 0x01,
N  GPIO_PuPd_DOWN   = 0x02
N}GPIOPuPd_TypeDef;
N#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
N                            ((PUPD) == GPIO_PuPd_DOWN))
X#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) ||                             ((PUPD) == GPIO_PuPd_DOWN))
N
N/** 
N  * @brief  GPIO Bit SET and Bit RESET enumeration 
N  */ 
Ntypedef enum
N{ 
N  Bit_RESET = 0,
N  Bit_SET
N}BitAction;
N#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
N
N
N/** 
N  * @brief   GPIO Init structure definition  
N  */ 
Ntypedef struct
N{
N  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
N                                       This parameter can be any value of @ref GPIO_pins_define */
N
N  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
N                                       This parameter can be a value of @ref GPIOMode_TypeDef */
N
N  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
N                                       This parameter can be a value of @ref GPIOSpeed_TypeDef */
N
N  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
N                                       This parameter can be a value of @ref GPIOOType_TypeDef */
N
N  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
N                                       This parameter can be a value of @ref GPIOPuPd_TypeDef */
N}GPIO_InitTypeDef;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup GPIO_Exported_Constants
N  * @{
N  */ 
N
N/** @defgroup GPIO_pins_define 
N  * @{
N  */ 
N#define GPIO_Pin_0                 ((uint16_t)0x0001)  /* Pin 0 selected */
N#define GPIO_Pin_1                 ((uint16_t)0x0002)  /* Pin 1 selected */
N#define GPIO_Pin_2                 ((uint16_t)0x0004)  /* Pin 2 selected */
N#define GPIO_Pin_3                 ((uint16_t)0x0008)  /* Pin 3 selected */
N#define GPIO_Pin_4                 ((uint16_t)0x0010)  /* Pin 4 selected */
N#define GPIO_Pin_5                 ((uint16_t)0x0020)  /* Pin 5 selected */
N#define GPIO_Pin_6                 ((uint16_t)0x0040)  /* Pin 6 selected */
N#define GPIO_Pin_7                 ((uint16_t)0x0080)  /* Pin 7 selected */
N#define GPIO_Pin_8                 ((uint16_t)0x0100)  /* Pin 8 selected */
N#define GPIO_Pin_9                 ((uint16_t)0x0200)  /* Pin 9 selected */
N#define GPIO_Pin_10                ((uint16_t)0x0400)  /* Pin 10 selected */
N#define GPIO_Pin_11                ((uint16_t)0x0800)  /* Pin 11 selected */
N#define GPIO_Pin_12                ((uint16_t)0x1000)  /* Pin 12 selected */
N#define GPIO_Pin_13                ((uint16_t)0x2000)  /* Pin 13 selected */
N#define GPIO_Pin_14                ((uint16_t)0x4000)  /* Pin 14 selected */
N#define GPIO_Pin_15                ((uint16_t)0x8000)  /* Pin 15 selected */
N#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /* All pins selected */
N
N#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
N#define IS_GPIO_PIN(PIN)           (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
N#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
N                              ((PIN) == GPIO_Pin_1) || \
N                              ((PIN) == GPIO_Pin_2) || \
N                              ((PIN) == GPIO_Pin_3) || \
N                              ((PIN) == GPIO_Pin_4) || \
N                              ((PIN) == GPIO_Pin_5) || \
N                              ((PIN) == GPIO_Pin_6) || \
N                              ((PIN) == GPIO_Pin_7) || \
N                              ((PIN) == GPIO_Pin_8) || \
N                              ((PIN) == GPIO_Pin_9) || \
N                              ((PIN) == GPIO_Pin_10) || \
N                              ((PIN) == GPIO_Pin_11) || \
N                              ((PIN) == GPIO_Pin_12) || \
N                              ((PIN) == GPIO_Pin_13) || \
N                              ((PIN) == GPIO_Pin_14) || \
N                              ((PIN) == GPIO_Pin_15))
X#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) ||                               ((PIN) == GPIO_Pin_1) ||                               ((PIN) == GPIO_Pin_2) ||                               ((PIN) == GPIO_Pin_3) ||                               ((PIN) == GPIO_Pin_4) ||                               ((PIN) == GPIO_Pin_5) ||                               ((PIN) == GPIO_Pin_6) ||                               ((PIN) == GPIO_Pin_7) ||                               ((PIN) == GPIO_Pin_8) ||                               ((PIN) == GPIO_Pin_9) ||                               ((PIN) == GPIO_Pin_10) ||                               ((PIN) == GPIO_Pin_11) ||                               ((PIN) == GPIO_Pin_12) ||                               ((PIN) == GPIO_Pin_13) ||                               ((PIN) == GPIO_Pin_14) ||                               ((PIN) == GPIO_Pin_15))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup GPIO_Pin_sources 
N  * @{
N  */ 
N#define GPIO_PinSource0            ((uint8_t)0x00)
N#define GPIO_PinSource1            ((uint8_t)0x01)
N#define GPIO_PinSource2            ((uint8_t)0x02)
N#define GPIO_PinSource3            ((uint8_t)0x03)
N#define GPIO_PinSource4            ((uint8_t)0x04)
N#define GPIO_PinSource5            ((uint8_t)0x05)
N#define GPIO_PinSource6            ((uint8_t)0x06)
N#define GPIO_PinSource7            ((uint8_t)0x07)
N#define GPIO_PinSource8            ((uint8_t)0x08)
N#define GPIO_PinSource9            ((uint8_t)0x09)
N#define GPIO_PinSource10           ((uint8_t)0x0A)
N#define GPIO_PinSource11           ((uint8_t)0x0B)
N#define GPIO_PinSource12           ((uint8_t)0x0C)
N#define GPIO_PinSource13           ((uint8_t)0x0D)
N#define GPIO_PinSource14           ((uint8_t)0x0E)
N#define GPIO_PinSource15           ((uint8_t)0x0F)
N
N#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
N                                       ((PINSOURCE) == GPIO_PinSource1) || \
N                                       ((PINSOURCE) == GPIO_PinSource2) || \
N                                       ((PINSOURCE) == GPIO_PinSource3) || \
N                                       ((PINSOURCE) == GPIO_PinSource4) || \
N                                       ((PINSOURCE) == GPIO_PinSource5) || \
N                                       ((PINSOURCE) == GPIO_PinSource6) || \
N                                       ((PINSOURCE) == GPIO_PinSource7) || \
N                                       ((PINSOURCE) == GPIO_PinSource8) || \
N                                       ((PINSOURCE) == GPIO_PinSource9) || \
N                                       ((PINSOURCE) == GPIO_PinSource10) || \
N                                       ((PINSOURCE) == GPIO_PinSource11) || \
N                                       ((PINSOURCE) == GPIO_PinSource12) || \
N                                       ((PINSOURCE) == GPIO_PinSource13) || \
N                                       ((PINSOURCE) == GPIO_PinSource14) || \
N                                       ((PINSOURCE) == GPIO_PinSource15))
X#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) ||                                        ((PINSOURCE) == GPIO_PinSource1) ||                                        ((PINSOURCE) == GPIO_PinSource2) ||                                        ((PINSOURCE) == GPIO_PinSource3) ||                                        ((PINSOURCE) == GPIO_PinSource4) ||                                        ((PINSOURCE) == GPIO_PinSource5) ||                                        ((PINSOURCE) == GPIO_PinSource6) ||                                        ((PINSOURCE) == GPIO_PinSource7) ||                                        ((PINSOURCE) == GPIO_PinSource8) ||                                        ((PINSOURCE) == GPIO_PinSource9) ||                                        ((PINSOURCE) == GPIO_PinSource10) ||                                        ((PINSOURCE) == GPIO_PinSource11) ||                                        ((PINSOURCE) == GPIO_PinSource12) ||                                        ((PINSOURCE) == GPIO_PinSource13) ||                                        ((PINSOURCE) == GPIO_PinSource14) ||                                        ((PINSOURCE) == GPIO_PinSource15))
N/**
N  * @}
N  */ 
N
N/** @defgroup GPIO_Alternat_function_selection_define 
N  * @{
N  */ 
N/** 
N  * @brief   AF 0 selection  
N  */ 
N#define GPIO_AF_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping */
N#define GPIO_AF_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping */
N#define GPIO_AF_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
N#define GPIO_AF_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping */
N#define GPIO_AF_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping */
N#if defined (STM32F446xx)
X#if 0L
S#define GPIO_AF0_TIM2         ((uint8_t)0x00)  /* TIM2 Alternate Function mapping */
N#endif /* STM32F446xx */
N
N/** 
N  * @brief   AF 1 selection  
N  */ 
N#define GPIO_AF_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
N#define GPIO_AF_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
N
N/** 
N  * @brief   AF 2 selection  
N  */ 
N#define GPIO_AF_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
N#define GPIO_AF_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
N#define GPIO_AF_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
N
N/** 
N  * @brief   AF 3 selection  
N  */ 
N#define GPIO_AF_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping */
N#define GPIO_AF_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping */
N#define GPIO_AF_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
N#define GPIO_AF_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
N#if defined (STM32F446xx)
X#if 0L
S#define GPIO_AF3_CEC          ((uint8_t)0x03)  /* CEC Alternate Function mapping */
N#endif /* STM32F446xx */
N/** 
N  * @brief   AF 4 selection  
N  */ 
N#define GPIO_AF_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
N#define GPIO_AF_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
N#define GPIO_AF_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
N#if defined (STM32F446xx)
X#if 0L
S#define GPIO_AF4_CEC          ((uint8_t)0x04)  /* CEC Alternate Function mapping */
S#define GPIO_AF_FMPI2C        ((uint8_t)0x04)  /* FMPI2C Alternate Function mapping */
N#endif /* STM32F446xx */
N
N/** 
N  * @brief   AF 5 selection  
N  */ 
N#define GPIO_AF_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping */
N#define GPIO_AF_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping */
N#define GPIO_AF5_SPI3         ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */
N#define GPIO_AF_SPI4          ((uint8_t)0x05)  /* SPI4/I2S4 Alternate Function mapping */
N#define GPIO_AF_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping      */
N#define GPIO_AF_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping      */
N
N/** 
N  * @brief   AF 6 selection  
N  */ 
N#define GPIO_AF_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping */
N#define GPIO_AF6_SPI2         ((uint8_t)0x06)  /* SPI2 Alternate Function mapping (Only for STM32F411xE Devices) */
N#define GPIO_AF6_SPI4         ((uint8_t)0x06)  /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
N#define GPIO_AF6_SPI5         ((uint8_t)0x06)  /* SPI5 Alternate Function mapping (Only for STM32F411xE Devices) */
N#define GPIO_AF_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping      */
N
N/** 
N  * @brief   AF 7 selection  
N  */ 
N#define GPIO_AF_USART1         ((uint8_t)0x07)  /* USART1 Alternate Function mapping  */
N#define GPIO_AF_USART2         ((uint8_t)0x07)  /* USART2 Alternate Function mapping  */
N#define GPIO_AF_USART3         ((uint8_t)0x07)  /* USART3 Alternate Function mapping  */
N#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3ext Alternate Function mapping */
N
N/** 
N  * @brief   AF 7 selection Legacy 
N  */ 
N#define GPIO_AF_I2S3ext   GPIO_AF7_SPI3
N
N/** 
N  * @brief   AF 8 selection  
N  */ 
N#define GPIO_AF_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
N#define GPIO_AF_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
N#define GPIO_AF_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
N#define GPIO_AF_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
N#define GPIO_AF_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
N#if defined (STM32F446xx)
X#if 0L
S#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping */
S#define GPIO_AF_SPDIF         ((uint8_t)0x08)   /* SPDIF Alternate Function mapping */
N#endif /* STM32F446xx */
N
N/** 
N  * @brief   AF 9 selection 
N  */ 
N#define GPIO_AF_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
N#define GPIO_AF_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
N#define GPIO_AF_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
N#define GPIO_AF_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
N#define GPIO_AF_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
N
N#define GPIO_AF9_I2C2         ((uint8_t)0x09)  /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
N#define GPIO_AF9_I2C3         ((uint8_t)0x09)  /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
N#if defined (STM32F446xx)
X#if 0L
S#define GPIO_AF9_SAI2         ((uint8_t)0x09)  /* SAI2 Alternate Function mapping */
N#endif /* STM32F446xx */
N#define GPIO_AF9_LTDC         ((uint8_t)0x09)  /* LTDC Alternate Function mapping */
N#if defined (STM32F446xx)
X#if 0L
S#define GPIO_AF9_QUADSPI      ((uint8_t)0x09)  /* QuadSPI Alternate Function mapping */
N#endif /* STM32F446xx */
N/** 
N  * @brief   AF 10 selection  
N  */ 
N#define GPIO_AF_OTG_FS         ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
N#define GPIO_AF_OTG_HS         ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
N#if defined (STM32F446xx)
X#if 0L
S#define GPIO_AF10_SAI2         ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping */
N#endif /* STM32F446xx */
N#if defined (STM32F446xx)
X#if 0L
S#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QuadSPI Alternate Function mapping */
N#endif /* STM32F446xx */
N/** 
N  * @brief   AF 11 selection  
N  */ 
N#define GPIO_AF_ETH             ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
N
N/** 
N  * @brief   AF 12 selection  
N  */ 
N#if defined (STM32F40_41xxx)
X#if 1L
N#define GPIO_AF_FSMC             ((uint8_t)0xC)  /* FSMC Alternate Function mapping                     */
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F446xx)
X#if 0L || 0L || 0L
S#define GPIO_AF_FMC              ((uint8_t)0xC)  /* FMC Alternate Function mapping                      */
N#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
N
N#define GPIO_AF_OTG_HS_FS        ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
N#define GPIO_AF_SDIO             ((uint8_t)0xC)  /* SDIO Alternate Function mapping                     */
N
N/** 
N  * @brief   AF 13 selection  
N  */ 
N#define GPIO_AF_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
N
N/** 
N  * @brief   AF 14 selection  
N  */
N#define GPIO_AF_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
N
N/** 
N  * @brief   AF 15 selection  
N  */ 
N#define GPIO_AF_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
N
N#if defined (STM32F40_41xxx)
X#if 1L
N#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     || \
N                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    || \
N                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     || \
N                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      || \
N                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      || \
N                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      || \
N                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      || \
N                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      || \
N                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     || \
N                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     || \
N                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    || \
N                          ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)     || \
N                          ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6)    || \
N                          ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)      || \
N                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    || \
N                          ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_OTG_HS_FS) || \
N                          ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_DCMI)      || \
N                          ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_FSMC))
X#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     ||                           ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    ||                           ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     ||                           ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      ||                           ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      ||                           ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      ||                           ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      ||                           ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      ||                           ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     ||                           ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     ||                           ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    ||                           ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)     ||                           ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6)    ||                           ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)      ||                           ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    ||                           ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_OTG_HS_FS) ||                           ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_DCMI)      ||                           ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_FSMC))
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F401xx)
X#if 0L
S#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     || \
S                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    || \
S                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     || \
S                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      || \
S                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      || \
S                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      || \
S                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      || \
S                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      || \
S                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     || \
S                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     || \
S                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    || \
S                          ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_USART6)    || \
S                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    || \
S                          ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_SPI4))
X#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     ||                           ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    ||                           ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     ||                           ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      ||                           ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      ||                           ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      ||                           ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      ||                           ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      ||                           ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     ||                           ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     ||                           ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    ||                           ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_USART6)    ||                           ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    ||                           ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_SPI4))
N#endif /* STM32F401xx */
N
N#if defined (STM32F411xE)
X#if 0L
S#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14))
N#endif /* STM32F411xE */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
X#if 0L || 0L
S#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     || \
S                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    || \
S                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     || \
S                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      || \
S                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      || \
S                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      || \
S                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      || \
S                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      || \
S                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     || \
S                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     || \
S                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    || \
S                          ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)     || \
S                          ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6)    || \
S                          ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)      || \
S                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    || \
S                          ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_OTG_HS_FS) || \
S                          ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_DCMI)      || \
S                          ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_SPI4)      || \
S                          ((AF) == GPIO_AF_SPI5)      || ((AF) == GPIO_AF_SPI6)      || \
S                          ((AF) == GPIO_AF_UART7)     || ((AF) == GPIO_AF_UART8)     || \
S                          ((AF) == GPIO_AF_FMC)       ||  ((AF) == GPIO_AF_SAI1)     || \
S                          ((AF) == GPIO_AF_LTDC))
X#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     ||                           ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    ||                           ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     ||                           ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      ||                           ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      ||                           ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      ||                           ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      ||                           ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      ||                           ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     ||                           ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     ||                           ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    ||                           ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)     ||                           ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6)    ||                           ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)      ||                           ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    ||                           ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_OTG_HS_FS) ||                           ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_DCMI)      ||                           ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_SPI4)      ||                           ((AF) == GPIO_AF_SPI5)      || ((AF) == GPIO_AF_SPI6)      ||                           ((AF) == GPIO_AF_UART7)     || ((AF) == GPIO_AF_UART8)     ||                           ((AF) == GPIO_AF_FMC)       ||  ((AF) == GPIO_AF_SAI1)     ||                           ((AF) == GPIO_AF_LTDC))
N#endif /* STM32F427_437xx ||  STM32F429_439xx */
N
N#if defined (STM32F446xx)
X#if 0L
S#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
N#endif /* STM32F446xx */
N
N/**
N  * @}
N  */ 
N
N/** @defgroup GPIO_Legacy 
N  * @{
N  */
N    
N#define GPIO_Mode_AIN           GPIO_Mode_AN
N
N#define GPIO_AF_OTG1_FS         GPIO_AF_OTG_FS
N#define GPIO_AF_OTG2_HS         GPIO_AF_OTG_HS
N#define GPIO_AF_OTG2_FS         GPIO_AF_OTG_HS_FS
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/
N
N/*  Function used to set the GPIO configuration to the default reset state ****/
Nvoid GPIO_DeInit(GPIO_TypeDef* GPIOx);
N
N/* Initialization and Configuration functions *********************************/
Nvoid GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
Nvoid GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
Nvoid GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
N
N/* GPIO Read and Write functions **********************************************/
Nuint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
Nuint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
Nuint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
Nuint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
Nvoid GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
Nvoid GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
Nvoid GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
Nvoid GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
Nvoid GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
N
N/* GPIO Alternate functions configuration function ****************************/
Nvoid GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_GPIO_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 41 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_i2c.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_i2c.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_i2c.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the I2C firmware 
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************  
N  */ 
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_I2C_H
N#define __STM32F4xx_I2C_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup I2C
N  * @{
N  */
N
N/* Exported types ------------------------------------------------------------*/
N
N/** 
N  * @brief  I2C Init structure definition  
N  */
N
Ntypedef struct
N{
N  uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
N                                         This parameter must be set to a value lower than 400kHz */
N
N  uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
N                                         This parameter can be a value of @ref I2C_mode */
N
N  uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
N                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
N
N  uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
N                                         This parameter can be a 7-bit or 10-bit address. */
N
N  uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
N                                         This parameter can be a value of @ref I2C_acknowledgement */
N
N  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
N                                         This parameter can be a value of @ref I2C_acknowledged_address */
N}I2C_InitTypeDef;
N
N/* Exported constants --------------------------------------------------------*/
N
N
N/** @defgroup I2C_Exported_Constants
N  * @{
N  */
N#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
N                                   ((PERIPH) == I2C2) || \
N                                   ((PERIPH) == I2C3))
X#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) ||                                    ((PERIPH) == I2C2) ||                                    ((PERIPH) == I2C3))
N
N/** @defgroup I2C_Digital_Filter
N  * @{
N  */
N
N#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
N/**
N  * @}
N  */
N
N
N/** @defgroup I2C_mode 
N  * @{
N  */
N
N#define I2C_Mode_I2C                    ((uint16_t)0x0000)
N#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
N#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
N#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
N                           ((MODE) == I2C_Mode_SMBusDevice) || \
N                           ((MODE) == I2C_Mode_SMBusHost))
X#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) ||                            ((MODE) == I2C_Mode_SMBusDevice) ||                            ((MODE) == I2C_Mode_SMBusHost))
N/**
N  * @}
N  */
N
N/** @defgroup I2C_duty_cycle_in_fast_mode 
N  * @{
N  */
N
N#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
N#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
N#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
N                                  ((CYCLE) == I2C_DutyCycle_2))
X#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) ||                                   ((CYCLE) == I2C_DutyCycle_2))
N/**
N  * @}
N  */ 
N
N/** @defgroup I2C_acknowledgement
N  * @{
N  */
N
N#define I2C_Ack_Enable                  ((uint16_t)0x0400)
N#define I2C_Ack_Disable                 ((uint16_t)0x0000)
N#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
N                                 ((STATE) == I2C_Ack_Disable))
X#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) ||                                  ((STATE) == I2C_Ack_Disable))
N/**
N  * @}
N  */
N
N/** @defgroup I2C_transfer_direction 
N  * @{
N  */
N
N#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
N#define  I2C_Direction_Receiver         ((uint8_t)0x01)
N#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
N                                     ((DIRECTION) == I2C_Direction_Receiver))
X#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) ||                                      ((DIRECTION) == I2C_Direction_Receiver))
N/**
N  * @}
N  */
N
N/** @defgroup I2C_acknowledged_address 
N  * @{
N  */
N
N#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
N#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
N#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
N                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
X#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) ||                                              ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
N/**
N  * @}
N  */ 
N
N/** @defgroup I2C_registers 
N  * @{
N  */
N
N#define I2C_Register_CR1                ((uint8_t)0x00)
N#define I2C_Register_CR2                ((uint8_t)0x04)
N#define I2C_Register_OAR1               ((uint8_t)0x08)
N#define I2C_Register_OAR2               ((uint8_t)0x0C)
N#define I2C_Register_DR                 ((uint8_t)0x10)
N#define I2C_Register_SR1                ((uint8_t)0x14)
N#define I2C_Register_SR2                ((uint8_t)0x18)
N#define I2C_Register_CCR                ((uint8_t)0x1C)
N#define I2C_Register_TRISE              ((uint8_t)0x20)
N#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
N                                   ((REGISTER) == I2C_Register_CR2) || \
N                                   ((REGISTER) == I2C_Register_OAR1) || \
N                                   ((REGISTER) == I2C_Register_OAR2) || \
N                                   ((REGISTER) == I2C_Register_DR) || \
N                                   ((REGISTER) == I2C_Register_SR1) || \
N                                   ((REGISTER) == I2C_Register_SR2) || \
N                                   ((REGISTER) == I2C_Register_CCR) || \
N                                   ((REGISTER) == I2C_Register_TRISE))
X#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) ||                                    ((REGISTER) == I2C_Register_CR2) ||                                    ((REGISTER) == I2C_Register_OAR1) ||                                    ((REGISTER) == I2C_Register_OAR2) ||                                    ((REGISTER) == I2C_Register_DR) ||                                    ((REGISTER) == I2C_Register_SR1) ||                                    ((REGISTER) == I2C_Register_SR2) ||                                    ((REGISTER) == I2C_Register_CCR) ||                                    ((REGISTER) == I2C_Register_TRISE))
N/**
N  * @}
N  */
N
N/** @defgroup I2C_NACK_position 
N  * @{
N  */
N
N#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
N#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
N#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
N                                         ((POSITION) == I2C_NACKPosition_Current))
X#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) ||                                          ((POSITION) == I2C_NACKPosition_Current))
N/**
N  * @}
N  */ 
N
N/** @defgroup I2C_SMBus_alert_pin_level 
N  * @{
N  */
N
N#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
N#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
N#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
N                                   ((ALERT) == I2C_SMBusAlert_High))
X#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) ||                                    ((ALERT) == I2C_SMBusAlert_High))
N/**
N  * @}
N  */
N
N/** @defgroup I2C_PEC_position 
N  * @{
N  */
N
N#define I2C_PECPosition_Next            ((uint16_t)0x0800)
N#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
N#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
N                                       ((POSITION) == I2C_PECPosition_Current))
X#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) ||                                        ((POSITION) == I2C_PECPosition_Current))
N/**
N  * @}
N  */ 
N
N/** @defgroup I2C_interrupts_definition 
N  * @{
N  */
N
N#define I2C_IT_BUF                      ((uint16_t)0x0400)
N#define I2C_IT_EVT                      ((uint16_t)0x0200)
N#define I2C_IT_ERR                      ((uint16_t)0x0100)
N#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
N/**
N  * @}
N  */ 
N
N/** @defgroup I2C_interrupts_definition 
N  * @{
N  */
N
N#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
N#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
N#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
N#define I2C_IT_OVR                      ((uint32_t)0x01000800)
N#define I2C_IT_AF                       ((uint32_t)0x01000400)
N#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
N#define I2C_IT_BERR                     ((uint32_t)0x01000100)
N#define I2C_IT_TXE                      ((uint32_t)0x06000080)
N#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
N#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
N#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
N#define I2C_IT_BTF                      ((uint32_t)0x02000004)
N#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
N#define I2C_IT_SB                       ((uint32_t)0x02000001)
N
N#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
N
N#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
N                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
N                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
N                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
N                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
N                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
N                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
X#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) ||                            ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) ||                            ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) ||                            ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) ||                            ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) ||                            ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) ||                            ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
N/**
N  * @}
N  */
N
N/** @defgroup I2C_flags_definition 
N  * @{
N  */
N
N/** 
N  * @brief  SR2 register flags  
N  */
N
N#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
N#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
N#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
N#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
N#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
N#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
N#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
N
N/** 
N  * @brief  SR1 register flags  
N  */
N
N#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
N#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
N#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
N#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
N#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
N#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
N#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
N#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
N#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
N#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
N#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
N#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
N#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
N#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
N
N#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
N
N#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
N                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
N                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
N                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
N                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
N                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
N                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
N                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
N                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
N                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
N                               ((FLAG) == I2C_FLAG_SB))
X#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) ||                                ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) ||                                ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) ||                                ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) ||                                ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) ||                                ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) ||                                ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) ||                                ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) ||                                ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) ||                                ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) ||                                ((FLAG) == I2C_FLAG_SB))
N/**
N  * @}
N  */
N
N/** @defgroup I2C_Events 
N  * @{
N  */
N
N/**
N ===============================================================================
N               I2C Master Events (Events grouped in order of communication)
N ===============================================================================
N */
N
N/** 
N  * @brief  Communication start
N  * 
N  * After sending the START condition (I2C_GenerateSTART() function) the master 
N  * has to wait for this event. It means that the Start condition has been correctly 
N  * released on the I2C bus (the bus is free, no other devices is communicating).
N  * 
N  */
N/* --EV5 */
N#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
N
N/** 
N  * @brief  Address Acknowledge
N  * 
N  * After checking on EV5 (start condition correctly released on the bus), the 
N  * master sends the address of the slave(s) with which it will communicate 
N  * (I2C_Send7bitAddress() function, it also determines the direction of the communication: 
N  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges 
N  * his address. If an acknowledge is sent on the bus, one of the following events will 
N  * be set:
N  * 
N  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED 
N  *     event is set.
N  *  
N  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED 
N  *     is set
N  *  
N  *  3) In case of 10-Bit addressing mode, the master (just after generating the START 
N  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 
N  *  function). Then master should wait on EV9. It means that the 10-bit addressing 
N  *  header has been correctly sent on the bus. Then master should send the second part of 
N  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master 
N  *  should wait for event EV6. 
N  *     
N  */
N
N/* --EV6 */
N#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
N#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
N/* --EV9 */
N#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
N
N/** 
N  * @brief Communication events
N  * 
N  * If a communication is established (START condition generated and slave address 
N  * acknowledged) then the master has to check on one of the following events for 
N  * communication procedures:
N  *  
N  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 
N  *    the data received from the slave (I2C_ReceiveData() function).
N  * 
N  * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 
N  *    function) then to wait on event EV8 or EV8_2.
N  *    These two events are similar: 
N  *     - EV8 means that the data has been written in the data register and is 
N  *       being shifted out.
N  *     - EV8_2 means that the data has been physically shifted out and output 
N  *       on the bus.
N  *     In most cases, using EV8 is sufficient for the application.
N  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
N  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission 
N  *     (before Stop condition generation).
N  *     
N  *  @note In case the  user software does not guarantee that this event EV7 is 
N  *        managed before the current byte end of transfer, then user may check on EV7 
N  *        and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
N  *        In this case the communication may be slower.
N  * 
N  */
N
N/* Master RECEIVER mode -----------------------------*/ 
N/* --EV7 */
N#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
N
N/* Master TRANSMITTER mode --------------------------*/
N/* --EV8 */
N#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
N/* --EV8_2 */
N#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
N
N
N/**
N ===============================================================================
N               I2C Slave Events (Events grouped in order of communication)
N ===============================================================================
N */
N
N
N/** 
N  * @brief  Communication start events
N  * 
N  * Wait on one of these events at the start of the communication. It means that 
N  * the I2C peripheral detected a Start condition on the bus (generated by master 
N  * device) followed by the peripheral address. The peripheral generates an ACK 
N  * condition on the bus (if the acknowledge feature is enabled through function 
N  * I2C_AcknowledgeConfig()) and the events listed above are set :
N  *  
N  * 1) In normal case (only one address managed by the slave), when the address 
N  *   sent by the master matches the own address of the peripheral (configured by 
N  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 
N  *   (where XXX could be TRANSMITTER or RECEIVER).
N  *    
N  * 2) In case the address sent by the master matches the second address of the 
N  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled 
N  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 
N  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
N  *   
N  * 3) In case the address sent by the master is General Call (address 0x00) and 
N  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 
N  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.   
N  * 
N  */
N
N/* --EV1  (all the events below are variants of EV1) */   
N/* 1) Case of One Single Address managed by the slave */
N#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
N#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
N
N/* 2) Case of Dual address managed by the slave */
N#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
N#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
N
N/* 3) Case of General Call enabled for the slave */
N#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
N
N/** 
N  * @brief  Communication events
N  * 
N  * Wait on one of these events when EV1 has already been checked and: 
N  * 
N  * - Slave RECEIVER mode:
N  *     - EV2: When the application is expecting a data byte to be received. 
N  *     - EV4: When the application is expecting the end of the communication: master 
N  *       sends a stop condition and data transmission is stopped.
N  *    
N  * - Slave Transmitter mode:
N  *    - EV3: When a byte has been transmitted by the slave and the application is expecting 
N  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
N  *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be 
N  *      used when the user software doesn't guarantee the EV3 is managed before the
N  *      current byte end of transfer.
N  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission 
N  *      shall end (before sending the STOP condition). In this case slave has to stop sending 
N  *      data bytes and expect a Stop condition on the bus.
N  *      
N  *  @note In case the  user software does not guarantee that the event EV2 is 
N  *        managed before the current byte end of transfer, then user may check on EV2 
N  *        and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
N  *        In this case the communication may be slower.
N  *
N  */
N
N/* Slave RECEIVER mode --------------------------*/ 
N/* --EV2 */
N#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
N/* --EV4  */
N#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
N
N/* Slave TRANSMITTER mode -----------------------*/
N/* --EV3 */
N#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
N#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
N/* --EV3_2 */
N#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
N
N/*
N ===============================================================================
N                          End of Events Description
N ===============================================================================
N */
N
N#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
N                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
N                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
N                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
N                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
N                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
N                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
N                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
N                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
N                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
N                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
N                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
N                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
N                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
N                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
N                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
N                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
N                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
N                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
N                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
X#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) ||                              ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) ||                              ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) ||                              ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) ||                              ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) ||                              ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) ||                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) ||                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) ||                              ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) ||                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) ||                              ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) ||                              ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) ||                              ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) ||                              ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) ||                              ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) ||                              ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) ||                              ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) ||                              ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) ||                              ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) ||                              ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
N/**
N  * @}
N  */
N
N/** @defgroup I2C_own_address1 
N  * @{
N  */
N
N#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
N/**
N  * @}
N  */
N
N/** @defgroup I2C_clock_speed 
N  * @{
N  */
N
N#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N
N/*  Function used to set the I2C configuration to the default reset state *****/
Nvoid I2C_DeInit(I2C_TypeDef* I2Cx);
N
N/* Initialization and Configuration functions *********************************/
Nvoid I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
Nvoid I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
Nvoid I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
Nvoid I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter);
Nvoid I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
Nvoid I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
Nvoid I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
Nvoid I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
Nvoid I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
Nvoid I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
Nvoid I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
Nvoid I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
Nvoid I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
Nvoid I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
Nvoid I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
Nvoid I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
Nvoid I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
Nvoid I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
N
N/* Data transfers functions ***************************************************/ 
Nvoid I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
Nuint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
N
N/* PEC management functions ***************************************************/ 
Nvoid I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
Nvoid I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
Nvoid I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
Nuint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
N
N/* DMA transfers management functions *****************************************/
Nvoid I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
Nvoid I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
N
N/* Interrupts, events and flags management functions **************************/
Nuint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
Nvoid I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
N
N/* 
N ===============================================================================
N                          I2C State Monitoring Functions
N ===============================================================================
N  This I2C driver provides three different ways for I2C state monitoring
N  depending on the application requirements and constraints:
N         
N   
N     1. Basic state monitoring (Using I2C_CheckEvent() function)
N     -----------------------------------------------------------
N        It compares the status registers (SR1 and SR2) content to a given event
N        (can be the combination of one or more flags).
N        It returns SUCCESS if the current status includes the given flags 
N        and returns ERROR if one or more flags are missing in the current status.
N
N          - When to use
N             - This function is suitable for most applications as well as for startup 
N               activity since the events are fully described in the product reference 
N               manual (RM0090).
N             - It is also suitable for users who need to define their own events.
N
N          - Limitations
N             - If an error occurs (ie. error flags are set besides to the monitored 
N               flags), the I2C_CheckEvent() function may return SUCCESS despite 
N               the communication hold or corrupted real state. 
N               In this case, it is advised to use error interrupts to monitor 
N               the error events and handle them in the interrupt IRQ handler.
N         
N     Note 
N         For error management, it is advised to use the following functions:
N           - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
N           - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
N             Where x is the peripheral instance (I2C1, I2C2 ...)
N           - I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the 
N             I2Cx_ER_IRQHandler() function in order to determine which error occurred.
N           - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() 
N             and/or I2C_GenerateStop() in order to clear the error flag and source 
N             and return to correct  communication status.
N             
N 
N     2. Advanced state monitoring (Using the function I2C_GetLastEvent())
N     -------------------------------------------------------------------- 
N        Using the function I2C_GetLastEvent() which returns the image of both status 
N        registers in a single word (uint32_t) (Status Register 2 value is shifted left 
N        by 16 bits and concatenated to Status Register 1).
N
N          - When to use
N             - This function is suitable for the same applications above but it 
N               allows to overcome the mentioned limitation of I2C_GetFlagStatus() 
N               function.
N             - The returned value could be compared to events already defined in 
N               this file or to custom values defined by user.
N               This function is suitable when multiple flags are monitored at the 
N               same time.
N             - At the opposite of I2C_CheckEvent() function, this function allows 
N               user to choose when an event is accepted (when all events flags are 
N               set and no other flags are set or just when the needed flags are set 
N               like I2C_CheckEvent() function.
N
N          - Limitations
N             - User may need to define his own events.
N             - Same remark concerning the error management is applicable for this 
N               function if user decides to check only regular communication flags 
N               (and ignores error flags).
N      
N 
N     3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
N     -----------------------------------------------------------------------
N     
N      Using the function I2C_GetFlagStatus() which simply returns the status of 
N      one single flag (ie. I2C_FLAG_RXNE ...). 
N
N          - When to use
N             - This function could be used for specific applications or in debug 
N               phase.
N             - It is suitable when only one flag checking is needed (most I2C 
N               events are monitored through multiple flags).
N          - Limitations: 
N             - When calling this function, the Status register is accessed. 
N               Some flags are cleared when the status register is accessed. 
N               So checking the status of one Flag, may clear other ones.
N             - Function may need to be called twice or more in order to monitor 
N               one single event.           
N */
N
N/*
N ===============================================================================
N                          1. Basic state monitoring
N ===============================================================================
N */
NErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
N/*
N ===============================================================================
N                          2. Advanced state monitoring
N ===============================================================================
N */
Nuint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
N/*
N ===============================================================================
N                          3. Flag-based state monitoring
N ===============================================================================
N */
NFlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
N
N
Nvoid I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
NITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
Nvoid I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_I2C_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 42 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_iwdg.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_iwdg.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_iwdg.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the IWDG 
N  *          firmware library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_IWDG_H
N#define __STM32F4xx_IWDG_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup IWDG
N  * @{
N  */
N
N/* Exported types ------------------------------------------------------------*/
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup IWDG_Exported_Constants
N  * @{
N  */
N  
N/** @defgroup IWDG_WriteAccess
N  * @{
N  */
N#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
N#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
N#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
N                                      ((ACCESS) == IWDG_WriteAccess_Disable))
X#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) ||                                       ((ACCESS) == IWDG_WriteAccess_Disable))
N/**
N  * @}
N  */
N
N/** @defgroup IWDG_prescaler 
N  * @{
N  */
N#define IWDG_Prescaler_4            ((uint8_t)0x00)
N#define IWDG_Prescaler_8            ((uint8_t)0x01)
N#define IWDG_Prescaler_16           ((uint8_t)0x02)
N#define IWDG_Prescaler_32           ((uint8_t)0x03)
N#define IWDG_Prescaler_64           ((uint8_t)0x04)
N#define IWDG_Prescaler_128          ((uint8_t)0x05)
N#define IWDG_Prescaler_256          ((uint8_t)0x06)
N#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
N                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
N                                      ((PRESCALER) == IWDG_Prescaler_16) || \
N                                      ((PRESCALER) == IWDG_Prescaler_32) || \
N                                      ((PRESCALER) == IWDG_Prescaler_64) || \
N                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
N                                      ((PRESCALER) == IWDG_Prescaler_256))
X#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  ||                                       ((PRESCALER) == IWDG_Prescaler_8)  ||                                       ((PRESCALER) == IWDG_Prescaler_16) ||                                       ((PRESCALER) == IWDG_Prescaler_32) ||                                       ((PRESCALER) == IWDG_Prescaler_64) ||                                       ((PRESCALER) == IWDG_Prescaler_128)||                                       ((PRESCALER) == IWDG_Prescaler_256))
N/**
N  * @}
N  */
N
N/** @defgroup IWDG_Flag 
N  * @{
N  */
N#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
N#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
N#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
N#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/
N
N/* Prescaler and Counter configuration functions ******************************/
Nvoid IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
Nvoid IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
Nvoid IWDG_SetReload(uint16_t Reload);
Nvoid IWDG_ReloadCounter(void);
N
N/* IWDG activation function ***************************************************/
Nvoid IWDG_Enable(void);
N
N/* Flag management function ***************************************************/
NFlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __STM32F4xx_IWDG_H */
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 43 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_pwr.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_pwr.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_pwr.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the PWR firmware 
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */ 
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_PWR_H
N#define __STM32F4xx_PWR_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup PWR
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup PWR_Exported_Constants
N  * @{
N  */ 
N
N/** @defgroup PWR_PVD_detection_level 
N  * @{
N  */ 
N#define PWR_PVDLevel_0                  PWR_CR_PLS_LEV0
N#define PWR_PVDLevel_1                  PWR_CR_PLS_LEV1
N#define PWR_PVDLevel_2                  PWR_CR_PLS_LEV2
N#define PWR_PVDLevel_3                  PWR_CR_PLS_LEV3
N#define PWR_PVDLevel_4                  PWR_CR_PLS_LEV4
N#define PWR_PVDLevel_5                  PWR_CR_PLS_LEV5
N#define PWR_PVDLevel_6                  PWR_CR_PLS_LEV6
N#define PWR_PVDLevel_7                  PWR_CR_PLS_LEV7
N
N#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
N                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
N                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
N                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
X#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)||                                  ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)||                                  ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)||                                  ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
N/**
N  * @}
N  */
N
N  
N/** @defgroup PWR_Regulator_state_in_STOP_mode 
N  * @{
N  */
N#define PWR_MainRegulator_ON                        ((uint32_t)0x00000000)
N#define PWR_LowPowerRegulator_ON                    PWR_CR_LPDS
N
N/* --- PWR_Legacy ---*/
N#define PWR_Regulator_ON                            PWR_MainRegulator_ON
N#define PWR_Regulator_LowPower                      PWR_LowPowerRegulator_ON
N
N#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \
N                                     ((REGULATOR) == PWR_LowPowerRegulator_ON))
X#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) ||                                      ((REGULATOR) == PWR_LowPowerRegulator_ON))
N
N/**
N  * @}
N  */
N
N/** @defgroup PWR_Regulator_state_in_UnderDrive_mode 
N  * @{
N  */
N#define PWR_MainRegulator_UnderDrive_ON               PWR_CR_MRUDS
N#define PWR_LowPowerRegulator_UnderDrive_ON           ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
N
N#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \
N                                                ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
X#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) ||                                                 ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
N
N/**
N  * @}
N  */
N#if defined(STM32F446xx)
X#if 0L
S/** @defgroup PWR_Wake_Up_Pin
S  * @{
S  */
S#define PWR_WakeUp_Pin1           ((uint32_t)0x00)
S#define PWR_WakeUp_Pin2           ((uint32_t)0x01)
S
S#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || \
S                                ((PIN) == PWR_WakeUp_Pin2))
X#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) ||                                 ((PIN) == PWR_WakeUp_Pin2))
S
S/**
S  * @}
S  */    
N#endif /* STM32F446xx */
N
N/** @defgroup PWR_STOP_mode_entry 
N  * @{
N  */
N#define PWR_STOPEntry_WFI               ((uint8_t)0x01)
N#define PWR_STOPEntry_WFE               ((uint8_t)0x02)
N#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
N/**
N  * @}
N  */
N
N/** @defgroup PWR_Regulator_Voltage_Scale 
N  * @{
N  */
N#define PWR_Regulator_Voltage_Scale1    ((uint32_t)0x0000C000)
N#define PWR_Regulator_Voltage_Scale2    ((uint32_t)0x00008000)
N#define PWR_Regulator_Voltage_Scale3    ((uint32_t)0x00004000)
N#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \
N                                           ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \
N                                           ((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
X#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) ||                                            ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) ||                                            ((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
N/**
N  * @}
N  */
N
N/** @defgroup PWR_Flag 
N  * @{
N  */
N#define PWR_FLAG_WU                     PWR_CSR_WUF
N#define PWR_FLAG_SB                     PWR_CSR_SBF
N#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
N#define PWR_FLAG_BRR                    PWR_CSR_BRR
N#define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY
N#define PWR_FLAG_ODRDY                  PWR_CSR_ODRDY
N#define PWR_FLAG_ODSWRDY                PWR_CSR_ODSWRDY
N#define PWR_FLAG_UDRDY                  PWR_CSR_UDSWRDY
N
N/* --- FLAG Legacy ---*/
N#define PWR_FLAG_REGRDY                  PWR_FLAG_VOSRDY               
N
N#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
N                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
N                               ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \
N                               ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
X#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) ||                                ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) ||                                ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) ||                                ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
N
N
N#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
N                                 ((FLAG) == PWR_FLAG_UDRDY))
X#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) ||                                  ((FLAG) == PWR_FLAG_UDRDY))
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N
N/* Function used to set the PWR configuration to the default reset state ******/ 
Nvoid PWR_DeInit(void);
N
N/* Backup Domain Access function **********************************************/ 
Nvoid PWR_BackupAccessCmd(FunctionalState NewState);
N
N/* PVD configuration functions ************************************************/ 
Nvoid PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
Nvoid PWR_PVDCmd(FunctionalState NewState);
N
N/* WakeUp pins configuration functions ****************************************/
N#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
X#if 1L || 0L || 0L || 0L || 0L
Nvoid PWR_WakeUpPinCmd(FunctionalState NewState);
N#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
N#if defined(STM32F446xx)
X#if 0L
Svoid PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState);
N#endif /* STM32F446xx */
N/* Main and Backup Regulators configuration functions *************************/ 
Nvoid PWR_BackupRegulatorCmd(FunctionalState NewState);
Nvoid PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
Nvoid PWR_OverDriveCmd(FunctionalState NewState);
Nvoid PWR_OverDriveSWCmd(FunctionalState NewState);
Nvoid PWR_UnderDriveCmd(FunctionalState NewState);
N
N#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
X#if 0L || 0L || 0L
Svoid PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState);
Svoid PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState);
N#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
N
N#if defined(STM32F401xx) || defined(STM32F411xE)
X#if 0L || 0L
Svoid PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState);
Svoid PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState);
N#endif /* STM32F401xx || STM32F411xE */
N
N/* FLASH Power Down configuration functions ***********************************/ 
Nvoid PWR_FlashPowerDownCmd(FunctionalState NewState);
N
N/* Low Power modes configuration functions ************************************/ 
Nvoid PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
Nvoid PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
Nvoid PWR_EnterSTANDBYMode(void);
N
N/* Flags management functions *************************************************/ 
NFlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
Nvoid PWR_ClearFlag(uint32_t PWR_FLAG);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __STM32F4xx_PWR_H */
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 44 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_rcc.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_rcc.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_rcc.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the RCC firmware library.  
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_RCC_H
N#define __STM32F4xx_RCC_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup RCC
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
Ntypedef struct
N{
N  uint32_t SYSCLK_Frequency; /*!<  SYSCLK clock frequency expressed in Hz */
N  uint32_t HCLK_Frequency;   /*!<  HCLK clock frequency expressed in Hz   */
N  uint32_t PCLK1_Frequency;  /*!<  PCLK1 clock frequency expressed in Hz  */
N  uint32_t PCLK2_Frequency;  /*!<  PCLK2 clock frequency expressed in Hz  */
N}RCC_ClocksTypeDef;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup RCC_Exported_Constants
N  * @{
N  */
N  
N/** @defgroup RCC_HSE_configuration 
N  * @{
N  */
N#define RCC_HSE_OFF                      ((uint8_t)0x00)
N#define RCC_HSE_ON                       ((uint8_t)0x01)
N#define RCC_HSE_Bypass                   ((uint8_t)0x05)
N#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
N                         ((HSE) == RCC_HSE_Bypass))
X#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) ||                          ((HSE) == RCC_HSE_Bypass))
N/**
N  * @}
N  */ 
N
N/** @defgroup RCC_LSE_Dual_Mode_Selection
N  * @{
N  */
N#define RCC_LSE_LOWPOWER_MODE           ((uint8_t)0x00)
N#define RCC_LSE_HIGHDRIVE_MODE          ((uint8_t)0x01)
N#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
N                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
X#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||                                          ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
N/**
N  * @}
N  */
N
N/** @defgroup RCC_PLLSAIDivR_Factor
N  * @{
N  */
N#define RCC_PLLSAIDivR_Div2                ((uint32_t)0x00000000)
N#define RCC_PLLSAIDivR_Div4                ((uint32_t)0x00010000)
N#define RCC_PLLSAIDivR_Div8                ((uint32_t)0x00020000)
N#define RCC_PLLSAIDivR_Div16               ((uint32_t)0x00030000)
N#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
N                                        ((VALUE) == RCC_PLLSAIDivR_Div4)  ||\
N                                        ((VALUE) == RCC_PLLSAIDivR_Div8)  ||\
N                                        ((VALUE) == RCC_PLLSAIDivR_Div16))
X#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||                                        ((VALUE) == RCC_PLLSAIDivR_Div4)  ||                                        ((VALUE) == RCC_PLLSAIDivR_Div8)  ||                                        ((VALUE) == RCC_PLLSAIDivR_Div16))
N/**
N  * @}
N  */
N
N/** @defgroup RCC_PLL_Clock_Source 
N  * @{
N  */
N#define RCC_PLLSource_HSI                ((uint32_t)0x00000000)
N#define RCC_PLLSource_HSE                ((uint32_t)0x00400000)
N#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
N                                   ((SOURCE) == RCC_PLLSource_HSE))
X#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) ||                                    ((SOURCE) == RCC_PLLSource_HSE))
N#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
N#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
N#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
N#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
N#if defined(STM32F446xx)
X#if 0L
S#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
N#endif /* STM32F446xx */
N
N#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
N#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
N#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
N#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
N#if defined(STM32F446xx)
X#if 0L
S#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
S#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
N#endif /* STM32F446xx */
N#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
N#if defined(STM32F446xx)
X#if 0L
S#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
N#endif /* STM32F446xx */
N#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
N#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))  
N
N#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
N#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
N/**
N  * @}
N  */ 
N  
N/** @defgroup RCC_System_Clock_Source 
N  * @{
N  */
N
N#if defined(STM32F446xx)
X#if 0L
S#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
S#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
S#define RCC_SYSCLKSource_PLLPCLK         ((uint32_t)0x00000002)
S#define RCC_SYSCLKSource_PLLRCLK         ((uint32_t)0x00000003)
S#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
S                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
S                                      ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
S                                      ((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
X#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) ||                                       ((SOURCE) == RCC_SYSCLKSource_HSE) ||                                       ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) ||                                       ((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
S/* Add legacy definition */
S#define  RCC_SYSCLKSource_PLLCLK    RCC_SYSCLKSource_PLLPCLK  
N#endif /* STM32F446xx */
N
N#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
X#if 1L || 0L || 0L || 0L || 0L
N#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
N#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
N#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
N#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
N                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
N                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
X#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) ||                                       ((SOURCE) == RCC_SYSCLKSource_HSE) ||                                       ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
N#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ 
N/**
N  * @}
N  */ 
N  
N/** @defgroup RCC_AHB_Clock_Source
N  * @{
N  */
N#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
N#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
N#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
N#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
N#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
N#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
N#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
N#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
N#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
N#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
N                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
N                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
N                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
N                           ((HCLK) == RCC_SYSCLK_Div512))
X#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) ||                            ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) ||                            ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) ||                            ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) ||                            ((HCLK) == RCC_SYSCLK_Div512))
N/**
N  * @}
N  */ 
N  
N/** @defgroup RCC_APB1_APB2_Clock_Source
N  * @{
N  */
N#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
N#define RCC_HCLK_Div2                    ((uint32_t)0x00001000)
N#define RCC_HCLK_Div4                    ((uint32_t)0x00001400)
N#define RCC_HCLK_Div8                    ((uint32_t)0x00001800)
N#define RCC_HCLK_Div16                   ((uint32_t)0x00001C00)
N#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
N                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
N                           ((PCLK) == RCC_HCLK_Div16))
X#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) ||                            ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) ||                            ((PCLK) == RCC_HCLK_Div16))
N/**
N  * @}
N  */ 
N  
N/** @defgroup RCC_Interrupt_Source 
N  * @{
N  */
N#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
N#define RCC_IT_LSERDY                    ((uint8_t)0x02)
N#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
N#define RCC_IT_HSERDY                    ((uint8_t)0x08)
N#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
N#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20) 
N#define RCC_IT_PLLSAIRDY                 ((uint8_t)0x40)
N#define RCC_IT_CSS                       ((uint8_t)0x80)
N
N#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
N#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
N                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
N                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
N                           ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
X#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) ||                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) ||                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) ||                            ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
N#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
N
N/**
N  * @}
N  */ 
N  
N/** @defgroup RCC_LSE_Configuration 
N  * @{
N  */
N#define RCC_LSE_OFF                      ((uint8_t)0x00)
N#define RCC_LSE_ON                       ((uint8_t)0x01)
N#define RCC_LSE_Bypass                   ((uint8_t)0x04)
N#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
N                         ((LSE) == RCC_LSE_Bypass))
X#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) ||                          ((LSE) == RCC_LSE_Bypass))
N/**
N  * @}
N  */ 
N  
N/** @defgroup RCC_RTC_Clock_Source
N  * @{
N  */
N#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
N#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
N#define RCC_RTCCLKSource_HSE_Div2        ((uint32_t)0x00020300)
N#define RCC_RTCCLKSource_HSE_Div3        ((uint32_t)0x00030300)
N#define RCC_RTCCLKSource_HSE_Div4        ((uint32_t)0x00040300)
N#define RCC_RTCCLKSource_HSE_Div5        ((uint32_t)0x00050300)
N#define RCC_RTCCLKSource_HSE_Div6        ((uint32_t)0x00060300)
N#define RCC_RTCCLKSource_HSE_Div7        ((uint32_t)0x00070300)
N#define RCC_RTCCLKSource_HSE_Div8        ((uint32_t)0x00080300)
N#define RCC_RTCCLKSource_HSE_Div9        ((uint32_t)0x00090300)
N#define RCC_RTCCLKSource_HSE_Div10       ((uint32_t)0x000A0300)
N#define RCC_RTCCLKSource_HSE_Div11       ((uint32_t)0x000B0300)
N#define RCC_RTCCLKSource_HSE_Div12       ((uint32_t)0x000C0300)
N#define RCC_RTCCLKSource_HSE_Div13       ((uint32_t)0x000D0300)
N#define RCC_RTCCLKSource_HSE_Div14       ((uint32_t)0x000E0300)
N#define RCC_RTCCLKSource_HSE_Div15       ((uint32_t)0x000F0300)
N#define RCC_RTCCLKSource_HSE_Div16       ((uint32_t)0x00100300)
N#define RCC_RTCCLKSource_HSE_Div17       ((uint32_t)0x00110300)
N#define RCC_RTCCLKSource_HSE_Div18       ((uint32_t)0x00120300)
N#define RCC_RTCCLKSource_HSE_Div19       ((uint32_t)0x00130300)
N#define RCC_RTCCLKSource_HSE_Div20       ((uint32_t)0x00140300)
N#define RCC_RTCCLKSource_HSE_Div21       ((uint32_t)0x00150300)
N#define RCC_RTCCLKSource_HSE_Div22       ((uint32_t)0x00160300)
N#define RCC_RTCCLKSource_HSE_Div23       ((uint32_t)0x00170300)
N#define RCC_RTCCLKSource_HSE_Div24       ((uint32_t)0x00180300)
N#define RCC_RTCCLKSource_HSE_Div25       ((uint32_t)0x00190300)
N#define RCC_RTCCLKSource_HSE_Div26       ((uint32_t)0x001A0300)
N#define RCC_RTCCLKSource_HSE_Div27       ((uint32_t)0x001B0300)
N#define RCC_RTCCLKSource_HSE_Div28       ((uint32_t)0x001C0300)
N#define RCC_RTCCLKSource_HSE_Div29       ((uint32_t)0x001D0300)
N#define RCC_RTCCLKSource_HSE_Div30       ((uint32_t)0x001E0300)
N#define RCC_RTCCLKSource_HSE_Div31       ((uint32_t)0x001F0300)
N#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
N                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
X#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) ||                                       ((SOURCE) == RCC_RTCCLKSource_LSI) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) ||                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
N/**
N  * @}
N  */ 
N
N#if defined(STM32F446xx)
X#if 0L
S/** @defgroup RCC_I2S_Clock_Source
S  * @{
S  */
S#define RCC_I2SCLKSource_PLLI2S             ((uint32_t)0x00)
S#define RCC_I2SCLKSource_Ext                ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
S#define RCC_I2SCLKSource_PLL                ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
S#define RCC_I2SCLKSource_HSI_HSE            ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1)
S
S#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \
S                                      ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))                                
X#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) ||                                       ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))                                
S/**
S  * @}
S  */
S
S/** @defgroup RCC_I2S_APBBus
S  * @{
S  */
S#define RCC_I2SBus_APB1             ((uint8_t)0x00)
S#define RCC_I2SBus_APB2             ((uint8_t)0x01)
S#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2))                                
S/**
S  * @}
S  */
S    
S/** @defgroup RCC_SAI_Clock_Source
S  * @{
S  */
S#define RCC_SAICLKSource_PLLSAI             ((uint32_t)0x00)
S#define RCC_SAICLKSource_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
S#define RCC_SAICLKSource_PLL                ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
S#define RCC_SAICLKSource_HSI_HSE            ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1)
S
S#define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \
S                                      ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))                                
X#define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) ||                                       ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))                                
S/**
S  * @}
S  */    
S    
S/** @defgroup RCC_SAI_Instance
S  * @{
S  */
S#define RCC_SAIInstance_SAI1             ((uint8_t)0x00)
S#define RCC_SAIInstance_SAI2             ((uint8_t)0x01)
S#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))                                
S/**
S  * @}
S  */
N#endif /* STM32F446xx */
N
N#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
X#if 1L || 0L || 0L || 0L || 0L
N/** @defgroup RCC_I2S_Clock_Source
N  * @{
N  */
N#define RCC_I2S2CLKSource_PLLI2S             ((uint8_t)0x00)
N#define RCC_I2S2CLKSource_Ext                ((uint8_t)0x01)
N
N#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))                                
N/**
N  * @}
N  */ 
N
N/** @defgroup RCC_SAI_BlockA_Clock_Source
N  * @{
N  */
N#define RCC_SAIACLKSource_PLLSAI             ((uint32_t)0x00000000)
N#define RCC_SAIACLKSource_PLLI2S             ((uint32_t)0x00100000)
N#define RCC_SAIACLKSource_Ext                ((uint32_t)0x00200000)
N
N#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
N                                       ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
N                                       ((SOURCE) == RCC_SAIACLKSource_Ext))
X#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||                                       ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||                                       ((SOURCE) == RCC_SAIACLKSource_Ext))
N/**
N  * @}
N  */ 
N
N/** @defgroup RCC_SAI_BlockB_Clock_Source
N  * @{
N  */
N#define RCC_SAIBCLKSource_PLLSAI             ((uint32_t)0x00000000)
N#define RCC_SAIBCLKSource_PLLI2S             ((uint32_t)0x00400000)
N#define RCC_SAIBCLKSource_Ext                ((uint32_t)0x00800000)
N
N#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
N                                       ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
N                                       ((SOURCE) == RCC_SAIBCLKSource_Ext))
X#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||                                       ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||                                       ((SOURCE) == RCC_SAIBCLKSource_Ext))
N/**
N  * @}
N  */ 
N#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
N
N/** @defgroup RCC_TIM_PRescaler_Selection
N  * @{
N  */
N#define RCC_TIMPrescDesactivated             ((uint8_t)0x00)
N#define RCC_TIMPrescActivated                ((uint8_t)0x01)
N
N#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
N/**
N  * @}
N  */
N
N#if defined(STM32F446xx)
X#if 0L
S/** @defgroup RCC_SDIO_Clock_Source_Selection
S  * @{
S  */
S#define RCC_SDIOCLKSource_48MHZ              ((uint8_t)0x00)
S#define RCC_SDIOCLKSource_SYSCLK             ((uint8_t)0x01)
S#define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE)   (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \
S                                              ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK))
X#define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE)   (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) ||                                               ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK))
S/**
S  * @}
S  */
S
S
S/** @defgroup RCC_48MHZ_Clock_Source_Selection
S  * @{
S  */
S#define RCC_48MHZCLKSource_PLL                ((uint8_t)0x00)
S#define RCC_48MHZCLKSource_PLLSAI             ((uint8_t)0x01)
S#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE)   (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
S                                               ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
X#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE)   (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) ||                                                ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
S/**
S  * @}
S  */
N#endif /* STM32F446xx */
N
N#if defined(STM32F446xx) 
X#if 0L 
S/** @defgroup RCC_SPDIFRX_Clock_Source_Selection
S  * @{
S  */
S#define RCC_SPDIFRXCLKSource_PLLR                 ((uint8_t)0x00)
S#define RCC_SPDIFRXCLKSource_PLLI2SP              ((uint8_t)0x01)
S#define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE)     (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \
S                                                   ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP))
X#define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE)     (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) ||                                                    ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP))
S/**
S  * @}
S  */
S
S/** @defgroup RCC_CEC_Clock_Source_Selection
S  * @{
S  */
S#define RCC_CECCLKSource_HSIDiv488            ((uint8_t)0x00)
S#define RCC_CECCLKSource_LSE                  ((uint8_t)0x01)
S#define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE)     (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \
S                                               ((CLKSOURCE) == RCC_CECCLKSource_LSE))
X#define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE)     (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) ||                                                ((CLKSOURCE) == RCC_CECCLKSource_LSE))
S/**
S  * @}
S  */
S
S/** @defgroup RCC_FMPI2C1_Clock_Source
S  * @{
S  */
S#define RCC_FMPI2C1CLKSource_APB1            ((uint32_t)0x00)
S#define RCC_FMPI2C1CLKSource_SYSCLK          ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
S#define RCC_FMPI2C1CLKSource_HSI             ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
S    
S#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
S                                         ((SOURCE) == RCC_FMPI2C1CLKSource_HSI))                                
X#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) ||                                          ((SOURCE) == RCC_FMPI2C1CLKSource_HSI))                                
S/**
S  * @}
S  */
S
S/** @defgroup RCC_AHB1_ClockGating
S  * @{
S  */ 
S#define RCC_AHB1ClockGating_APB1Bridge         ((uint32_t)0x00000001)
S#define RCC_AHB1ClockGating_APB2Bridge         ((uint32_t)0x00000002)
S#define RCC_AHB1ClockGating_CM4DBG             ((uint32_t)0x00000004)
S#define RCC_AHB1ClockGating_SPARE              ((uint32_t)0x00000008)
S#define RCC_AHB1ClockGating_SRAM               ((uint32_t)0x00000010)
S#define RCC_AHB1ClockGating_FLITF              ((uint32_t)0x00000020)
S#define RCC_AHB1ClockGating_RCC                ((uint32_t)0x00000040)
S
S#define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00))
S
S/**
S  * @}
S  */
N#endif /* STM32F446xx */
N
N/** @defgroup RCC_AHB1_Peripherals 
N  * @{
N  */ 
N#define RCC_AHB1Periph_GPIOA             ((uint32_t)0x00000001)
N#define RCC_AHB1Periph_GPIOB             ((uint32_t)0x00000002)
N#define RCC_AHB1Periph_GPIOC             ((uint32_t)0x00000004)
N#define RCC_AHB1Periph_GPIOD             ((uint32_t)0x00000008)
N#define RCC_AHB1Periph_GPIOE             ((uint32_t)0x00000010)
N#define RCC_AHB1Periph_GPIOF             ((uint32_t)0x00000020)
N#define RCC_AHB1Periph_GPIOG             ((uint32_t)0x00000040)
N#define RCC_AHB1Periph_GPIOH             ((uint32_t)0x00000080)
N#define RCC_AHB1Periph_GPIOI             ((uint32_t)0x00000100) 
N#define RCC_AHB1Periph_GPIOJ             ((uint32_t)0x00000200)
N#define RCC_AHB1Periph_GPIOK             ((uint32_t)0x00000400)
N#define RCC_AHB1Periph_CRC               ((uint32_t)0x00001000)
N#define RCC_AHB1Periph_FLITF             ((uint32_t)0x00008000)
N#define RCC_AHB1Periph_SRAM1             ((uint32_t)0x00010000)
N#define RCC_AHB1Periph_SRAM2             ((uint32_t)0x00020000)
N#define RCC_AHB1Periph_BKPSRAM           ((uint32_t)0x00040000)
N#define RCC_AHB1Periph_SRAM3             ((uint32_t)0x00080000)
N#define RCC_AHB1Periph_CCMDATARAMEN      ((uint32_t)0x00100000)
N#define RCC_AHB1Periph_DMA1              ((uint32_t)0x00200000)
N#define RCC_AHB1Periph_DMA2              ((uint32_t)0x00400000)
N#define RCC_AHB1Periph_DMA2D             ((uint32_t)0x00800000)
N#define RCC_AHB1Periph_ETH_MAC           ((uint32_t)0x02000000)
N#define RCC_AHB1Periph_ETH_MAC_Tx        ((uint32_t)0x04000000)
N#define RCC_AHB1Periph_ETH_MAC_Rx        ((uint32_t)0x08000000)
N#define RCC_AHB1Periph_ETH_MAC_PTP       ((uint32_t)0x10000000)
N#define RCC_AHB1Periph_OTG_HS            ((uint32_t)0x20000000)
N#define RCC_AHB1Periph_OTG_HS_ULPI       ((uint32_t)0x40000000)
N
N#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00))
N#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00))
N#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00))
N
N/**
N  * @}
N  */ 
N  
N/** @defgroup RCC_AHB2_Peripherals 
N  * @{
N  */  
N#define RCC_AHB2Periph_DCMI              ((uint32_t)0x00000001)
N#define RCC_AHB2Periph_CRYP              ((uint32_t)0x00000010)
N#define RCC_AHB2Periph_HASH              ((uint32_t)0x00000020)
N#define RCC_AHB2Periph_RNG               ((uint32_t)0x00000040)
N#define RCC_AHB2Periph_OTG_FS            ((uint32_t)0x00000080)
N#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
N/**
N  * @}
N  */ 
N  
N/** @defgroup RCC_AHB3_Peripherals 
N  * @{
N  */ 
N#if defined(STM32F40_41xxx)
X#if 1L
N#define RCC_AHB3Periph_FSMC                ((uint32_t)0x00000001)
N#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
N#endif /* STM32F40_41xxx */
N
N#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
X#if 0L || 0L
S#define RCC_AHB3Periph_FMC                 ((uint32_t)0x00000001)
S#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
N#endif /* STM32F427_437xx ||  STM32F429_439xx */
N
N#if defined(STM32F446xx)
X#if 0L
S#define RCC_AHB3Periph_FMC                 ((uint32_t)0x00000001)
S#define RCC_AHB3Periph_QSPI                ((uint32_t)0x00000002)
S#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
N#endif /* STM32F446xx */
N
N/**
N  * @}
N  */ 
N  
N/** @defgroup RCC_APB1_Peripherals 
N  * @{
N  */ 
N#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
N#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
N#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
N#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
N#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
N#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
N#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
N#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
N#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
N#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
N#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
N#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
N#if defined(STM32F446xx)
X#if 0L
S#define RCC_APB1Periph_SPDIFRX           ((uint32_t)0x00010000)
N#endif /* STM32F446xx */ 
N#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
N#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
N#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
N#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
N#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
N#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
N#define RCC_APB1Periph_I2C3              ((uint32_t)0x00800000)
N#if defined(STM32F446xx)
X#if 0L
S#define RCC_APB1Periph_FMPI2C1           ((uint32_t)0x01000000)
N#endif /* STM32F446xx */ 
N#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
N#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
N#if defined(STM32F446xx)
X#if 0L
S#define RCC_APB1Periph_CEC               ((uint32_t)0x08000000)
N#endif /* STM32F446xx */ 
N#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
N#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
N#define RCC_APB1Periph_UART7             ((uint32_t)0x40000000)
N#define RCC_APB1Periph_UART8             ((uint32_t)0x80000000)
N#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))
N/**
N  * @}
N  */ 
N  
N/** @defgroup RCC_APB2_Peripherals 
N  * @{
N  */ 
N#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000001)
N#define RCC_APB2Periph_TIM8              ((uint32_t)0x00000002)
N#define RCC_APB2Periph_USART1            ((uint32_t)0x00000010)
N#define RCC_APB2Periph_USART6            ((uint32_t)0x00000020)
N#define RCC_APB2Periph_ADC               ((uint32_t)0x00000100)
N#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000100)
N#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000200)
N#define RCC_APB2Periph_ADC3              ((uint32_t)0x00000400)
N#define RCC_APB2Periph_SDIO              ((uint32_t)0x00000800)
N#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
N#define RCC_APB2Periph_SPI4              ((uint32_t)0x00002000)
N#define RCC_APB2Periph_SYSCFG            ((uint32_t)0x00004000)
N#define RCC_APB2Periph_TIM9              ((uint32_t)0x00010000)
N#define RCC_APB2Periph_TIM10             ((uint32_t)0x00020000)
N#define RCC_APB2Periph_TIM11             ((uint32_t)0x00040000)
N#define RCC_APB2Periph_SPI5              ((uint32_t)0x00100000)
N#define RCC_APB2Periph_SPI6              ((uint32_t)0x00200000)
N#define RCC_APB2Periph_SAI1              ((uint32_t)0x00400000)
N#if defined(STM32F446xx)
X#if 0L
S#define RCC_APB2Periph_SAI2              ((uint32_t)0x00800000)
N#endif /* STM32F446xx */
N#define RCC_APB2Periph_LTDC              ((uint32_t)0x04000000)
N
N#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF30880CC) == 0x00) && ((PERIPH) != 0x00))
N#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF30886CC) == 0x00) && ((PERIPH) != 0x00))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RCC_MCO1_Clock_Source_Prescaler
N  * @{
N  */
N#define RCC_MCO1Source_HSI               ((uint32_t)0x00000000)
N#define RCC_MCO1Source_LSE               ((uint32_t)0x00200000)
N#define RCC_MCO1Source_HSE               ((uint32_t)0x00400000)
N#define RCC_MCO1Source_PLLCLK            ((uint32_t)0x00600000)
N#define RCC_MCO1Div_1                    ((uint32_t)0x00000000)
N#define RCC_MCO1Div_2                    ((uint32_t)0x04000000)
N#define RCC_MCO1Div_3                    ((uint32_t)0x05000000)
N#define RCC_MCO1Div_4                    ((uint32_t)0x06000000)
N#define RCC_MCO1Div_5                    ((uint32_t)0x07000000)
N#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
N                                   ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
X#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) ||                                    ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
N                                   
N#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
N                             ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
N                             ((DIV) == RCC_MCO1Div_5)) 
X#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) ||                              ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) ||                              ((DIV) == RCC_MCO1Div_5)) 
N/**
N  * @}
N  */ 
N  
N/** @defgroup RCC_MCO2_Clock_Source_Prescaler
N  * @{
N  */
N#define RCC_MCO2Source_SYSCLK            ((uint32_t)0x00000000)
N#define RCC_MCO2Source_PLLI2SCLK         ((uint32_t)0x40000000)
N#define RCC_MCO2Source_HSE               ((uint32_t)0x80000000)
N#define RCC_MCO2Source_PLLCLK            ((uint32_t)0xC0000000)
N#define RCC_MCO2Div_1                    ((uint32_t)0x00000000)
N#define RCC_MCO2Div_2                    ((uint32_t)0x20000000)
N#define RCC_MCO2Div_3                    ((uint32_t)0x28000000)
N#define RCC_MCO2Div_4                    ((uint32_t)0x30000000)
N#define RCC_MCO2Div_5                    ((uint32_t)0x38000000)
N#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
N                                   ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
X#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)||                                    ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
N                                   
N#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
N                             ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
N                             ((DIV) == RCC_MCO2Div_5))                             
X#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) ||                              ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) ||                              ((DIV) == RCC_MCO2Div_5))                             
N/**
N  * @}
N  */ 
N  
N/** @defgroup RCC_Flag 
N  * @{
N  */
N#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
N#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
N#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
N#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
N#define RCC_FLAG_PLLSAIRDY               ((uint8_t)0x3D)
N#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
N#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
N#define RCC_FLAG_BORRST                  ((uint8_t)0x79)
N#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
N#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
N#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
N#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
N#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
N#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
N
N#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)   || ((FLAG) == RCC_FLAG_HSERDY) || \
N                           ((FLAG) == RCC_FLAG_PLLRDY)   || ((FLAG) == RCC_FLAG_LSERDY) || \
N                           ((FLAG) == RCC_FLAG_LSIRDY)   || ((FLAG) == RCC_FLAG_BORRST) || \
N                           ((FLAG) == RCC_FLAG_PINRST)   || ((FLAG) == RCC_FLAG_PORRST) || \
N                           ((FLAG) == RCC_FLAG_SFTRST)   || ((FLAG) == RCC_FLAG_IWDGRST)|| \
N                           ((FLAG) == RCC_FLAG_WWDGRST)  || ((FLAG) == RCC_FLAG_LPWRRST)|| \
N                           ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
X#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)   || ((FLAG) == RCC_FLAG_HSERDY) ||                            ((FLAG) == RCC_FLAG_PLLRDY)   || ((FLAG) == RCC_FLAG_LSERDY) ||                            ((FLAG) == RCC_FLAG_LSIRDY)   || ((FLAG) == RCC_FLAG_BORRST) ||                            ((FLAG) == RCC_FLAG_PINRST)   || ((FLAG) == RCC_FLAG_PORRST) ||                            ((FLAG) == RCC_FLAG_SFTRST)   || ((FLAG) == RCC_FLAG_IWDGRST)||                            ((FLAG) == RCC_FLAG_WWDGRST)  || ((FLAG) == RCC_FLAG_LPWRRST)||                            ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
N
N#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N
N/* Function used to set the RCC clock configuration to the default reset state */
Nvoid        RCC_DeInit(void);
N
N/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
Nvoid        RCC_HSEConfig(uint8_t RCC_HSE);
NErrorStatus RCC_WaitForHSEStartUp(void);
Nvoid        RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
Nvoid        RCC_HSICmd(FunctionalState NewState);
Nvoid        RCC_LSEConfig(uint8_t RCC_LSE);
Nvoid        RCC_LSICmd(FunctionalState NewState);
N
Nvoid        RCC_PLLCmd(FunctionalState NewState);
N#if defined(STM32F446xx)
X#if 0L
Svoid        RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
N#endif /* STM32F446xx */
N
N#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
X#if 1L || 0L || 0L || 0L || 0L
Nvoid        RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
N#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
N
Nvoid        RCC_PLLI2SCmd(FunctionalState NewState);
N#if defined(STM32F40_41xxx) || defined(STM32F401xx)
X#if 1L || 0L
Nvoid        RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
N#endif /* STM32F40_41xxx || STM32F401xx */
N#if defined(STM32F411xE)
X#if 0L
Svoid        RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
N#endif /* STM32F411xE */
N#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
X#if 0L || 0L
Svoid        RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
N#endif /* STM32F427_437xx || STM32F429_439xx */
N#if defined(STM32F446xx)
X#if 0L
Svoid        RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
N#endif /* STM32F446xx */
N
Nvoid        RCC_PLLSAICmd(FunctionalState NewState);
N#if defined(STM32F446xx)
X#if 0L
Svoid        RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ);
N#endif /* STM32F446xx */
N#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
X#if 1L || 0L || 0L || 0L || 0L
Nvoid        RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
N#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
N
Nvoid        RCC_ClockSecuritySystemCmd(FunctionalState NewState);
Nvoid        RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
Nvoid        RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
N
N/* System, AHB and APB busses clocks configuration functions ******************/
Nvoid        RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
Nuint8_t     RCC_GetSYSCLKSource(void);
Nvoid        RCC_HCLKConfig(uint32_t RCC_SYSCLK);
Nvoid        RCC_PCLK1Config(uint32_t RCC_HCLK);
Nvoid        RCC_PCLK2Config(uint32_t RCC_HCLK);
Nvoid        RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
N
N/* Peripheral clocks configuration functions **********************************/
Nvoid        RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
Nvoid        RCC_RTCCLKCmd(FunctionalState NewState);
Nvoid        RCC_BackupResetCmd(FunctionalState NewState);
N
N#if defined(STM32F446xx)
X#if 0L
Svoid        RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
Svoid        RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
N#endif /* STM32F446xx */
N
N#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
X#if 1L || 0L || 0L || 0L || 0L
Nvoid        RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
Nvoid        RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
Nvoid        RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
N#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
N
Nvoid        RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
Nvoid        RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
N
Nvoid        RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
Nvoid        RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
N
Nvoid        RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
Nvoid        RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
Nvoid        RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
Nvoid        RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
Nvoid        RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
N
Nvoid        RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
Nvoid        RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
Nvoid        RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
Nvoid        RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
Nvoid        RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
N
Nvoid        RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
Nvoid        RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
Nvoid        RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
Nvoid        RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
Nvoid        RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
N
N/* Features available only for STM32F411xx/STM32F446xx devices */
Nvoid        RCC_LSEModeConfig(uint8_t RCC_Mode);
N
N/* Features available only for STM32F446xx devices */
N#if defined(STM32F446xx)
X#if 0L
Svoid        RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
Svoid        RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
N#endif /* STM32F446xx */
N
N/* Features available only for STM32F446xx devices */
N#if defined(STM32F446xx)
X#if 0L
Svoid        RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState);
Svoid        RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
Svoid        RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
Svoid        RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
N#endif /* STM32F446xx */
N
N/* Interrupts and flags management functions **********************************/
Nvoid        RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
NFlagStatus  RCC_GetFlagStatus(uint8_t RCC_FLAG);
Nvoid        RCC_ClearFlag(void);
NITStatus    RCC_GetITStatus(uint8_t RCC_IT);
Nvoid        RCC_ClearITPendingBit(uint8_t RCC_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __STM32F4xx_RCC_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 45 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_rtc.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_rtc.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_rtc.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the RTC firmware
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ****************************************************************************** 
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_RTC_H
N#define __STM32F4xx_RTC_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup RTC
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N
N/** 
N  * @brief  RTC Init structures definition  
N  */ 
Ntypedef struct
N{
N  uint32_t RTC_HourFormat;   /*!< Specifies the RTC Hour Format.
N                             This parameter can be a value of @ref RTC_Hour_Formats */
N  
N  uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
N                             This parameter must be set to a value lower than 0x7F */
N  
N  uint32_t RTC_SynchPrediv;  /*!< Specifies the RTC Synchronous Predivider value.
N                             This parameter must be set to a value lower than 0x7FFF */
N}RTC_InitTypeDef;
N
N/** 
N  * @brief  RTC Time structure definition  
N  */
Ntypedef struct
N{
N  uint8_t RTC_Hours;    /*!< Specifies the RTC Time Hour.
N                        This parameter must be set to a value in the 0-12 range
N                        if the RTC_HourFormat_12 is selected or 0-23 range if
N                        the RTC_HourFormat_24 is selected. */
N
N  uint8_t RTC_Minutes;  /*!< Specifies the RTC Time Minutes.
N                        This parameter must be set to a value in the 0-59 range. */
N  
N  uint8_t RTC_Seconds;  /*!< Specifies the RTC Time Seconds.
N                        This parameter must be set to a value in the 0-59 range. */
N
N  uint8_t RTC_H12;      /*!< Specifies the RTC AM/PM Time.
N                        This parameter can be a value of @ref RTC_AM_PM_Definitions */
N}RTC_TimeTypeDef; 
N
N/** 
N  * @brief  RTC Date structure definition  
N  */
Ntypedef struct
N{
N  uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
N                        This parameter can be a value of @ref RTC_WeekDay_Definitions */
N  
N  uint8_t RTC_Month;   /*!< Specifies the RTC Date Month (in BCD format).
N                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
N
N  uint8_t RTC_Date;     /*!< Specifies the RTC Date.
N                        This parameter must be set to a value in the 1-31 range. */
N  
N  uint8_t RTC_Year;     /*!< Specifies the RTC Date Year.
N                        This parameter must be set to a value in the 0-99 range. */
N}RTC_DateTypeDef;
N
N/** 
N  * @brief  RTC Alarm structure definition  
N  */
Ntypedef struct
N{
N  RTC_TimeTypeDef RTC_AlarmTime;     /*!< Specifies the RTC Alarm Time members. */
N
N  uint32_t RTC_AlarmMask;            /*!< Specifies the RTC Alarm Masks.
N                                     This parameter can be a value of @ref RTC_AlarmMask_Definitions */
N
N  uint32_t RTC_AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
N                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
N  
N  uint8_t RTC_AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
N                                     If the Alarm Date is selected, this parameter
N                                     must be set to a value in the 1-31 range.
N                                     If the Alarm WeekDay is selected, this 
N                                     parameter can be a value of @ref RTC_WeekDay_Definitions */
N}RTC_AlarmTypeDef;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup RTC_Exported_Constants
N  * @{
N  */ 
N
N
N/** @defgroup RTC_Hour_Formats 
N  * @{
N  */ 
N#define RTC_HourFormat_24              ((uint32_t)0x00000000)
N#define RTC_HourFormat_12              ((uint32_t)0x00000040)
N#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HourFormat_12) || \
N                                        ((FORMAT) == RTC_HourFormat_24))
X#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HourFormat_12) ||                                         ((FORMAT) == RTC_HourFormat_24))
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Asynchronous_Predivider 
N  * @{
N  */ 
N#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
N 
N/**
N  * @}
N  */ 
N
N
N/** @defgroup RTC_Synchronous_Predivider 
N  * @{
N  */ 
N#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFF)
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Time_Definitions 
N  * @{
N  */ 
N#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
N#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23)
N#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
N#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_AM_PM_Definitions 
N  * @{
N  */ 
N#define RTC_H12_AM                     ((uint8_t)0x00)
N#define RTC_H12_PM                     ((uint8_t)0x40)
N#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Year_Date_Definitions 
N  * @{
N  */ 
N#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99)
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Month_Date_Definitions 
N  * @{
N  */ 
N
N/* Coded in BCD format */
N#define RTC_Month_January              ((uint8_t)0x01)
N#define RTC_Month_February             ((uint8_t)0x02)
N#define RTC_Month_March                ((uint8_t)0x03)
N#define RTC_Month_April                ((uint8_t)0x04)
N#define RTC_Month_May                  ((uint8_t)0x05)
N#define RTC_Month_June                 ((uint8_t)0x06)
N#define RTC_Month_July                 ((uint8_t)0x07)
N#define RTC_Month_August               ((uint8_t)0x08)
N#define RTC_Month_September            ((uint8_t)0x09)
N#define RTC_Month_October              ((uint8_t)0x10)
N#define RTC_Month_November             ((uint8_t)0x11)
N#define RTC_Month_December             ((uint8_t)0x12)
N#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
N#define IS_RTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_WeekDay_Definitions 
N  * @{
N  */ 
N  
N#define RTC_Weekday_Monday             ((uint8_t)0x01)
N#define RTC_Weekday_Tuesday            ((uint8_t)0x02)
N#define RTC_Weekday_Wednesday          ((uint8_t)0x03)
N#define RTC_Weekday_Thursday           ((uint8_t)0x04)
N#define RTC_Weekday_Friday             ((uint8_t)0x05)
N#define RTC_Weekday_Saturday           ((uint8_t)0x06)
N#define RTC_Weekday_Sunday             ((uint8_t)0x07)
N#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
N                                 ((WEEKDAY) == RTC_Weekday_Tuesday) || \
N                                 ((WEEKDAY) == RTC_Weekday_Wednesday) || \
N                                 ((WEEKDAY) == RTC_Weekday_Thursday) || \
N                                 ((WEEKDAY) == RTC_Weekday_Friday) || \
N                                 ((WEEKDAY) == RTC_Weekday_Saturday) || \
N                                 ((WEEKDAY) == RTC_Weekday_Sunday))
X#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) ||                                  ((WEEKDAY) == RTC_Weekday_Tuesday) ||                                  ((WEEKDAY) == RTC_Weekday_Wednesday) ||                                  ((WEEKDAY) == RTC_Weekday_Thursday) ||                                  ((WEEKDAY) == RTC_Weekday_Friday) ||                                  ((WEEKDAY) == RTC_Weekday_Saturday) ||                                  ((WEEKDAY) == RTC_Weekday_Sunday))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup RTC_Alarm_Definitions
N  * @{
N  */ 
N#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
N#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
N                                                    ((WEEKDAY) == RTC_Weekday_Tuesday) || \
N                                                    ((WEEKDAY) == RTC_Weekday_Wednesday) || \
N                                                    ((WEEKDAY) == RTC_Weekday_Thursday) || \
N                                                    ((WEEKDAY) == RTC_Weekday_Friday) || \
N                                                    ((WEEKDAY) == RTC_Weekday_Saturday) || \
N                                                    ((WEEKDAY) == RTC_Weekday_Sunday))
X#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) ||                                                     ((WEEKDAY) == RTC_Weekday_Tuesday) ||                                                     ((WEEKDAY) == RTC_Weekday_Wednesday) ||                                                     ((WEEKDAY) == RTC_Weekday_Thursday) ||                                                     ((WEEKDAY) == RTC_Weekday_Friday) ||                                                     ((WEEKDAY) == RTC_Weekday_Saturday) ||                                                     ((WEEKDAY) == RTC_Weekday_Sunday))
N
N/**
N  * @}
N  */ 
N
N
N/** @defgroup RTC_AlarmDateWeekDay_Definitions 
N  * @{
N  */ 
N#define RTC_AlarmDateWeekDaySel_Date      ((uint32_t)0x00000000)
N#define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)
N
N#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
N                                            ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
X#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) ||                                             ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
N
N/**
N  * @}
N  */ 
N
N
N/** @defgroup RTC_AlarmMask_Definitions 
N  * @{
N  */ 
N#define RTC_AlarmMask_None                ((uint32_t)0x00000000)
N#define RTC_AlarmMask_DateWeekDay         ((uint32_t)0x80000000)
N#define RTC_AlarmMask_Hours               ((uint32_t)0x00800000)
N#define RTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
N#define RTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
N#define RTC_AlarmMask_All                 ((uint32_t)0x80808080)
N#define IS_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Alarms_Definitions 
N  * @{
N  */ 
N#define RTC_Alarm_A                       ((uint32_t)0x00000100)
N#define RTC_Alarm_B                       ((uint32_t)0x00000200)
N#define IS_RTC_ALARM(ALARM)     (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
N#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
N
N/**
N  * @}
N  */ 
N
N  /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
N  * @{
N  */ 
N#define RTC_AlarmSubSecondMask_All         ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. 
N                                                                       There is no comparison on sub seconds 
N                                                                       for Alarm */
N#define RTC_AlarmSubSecondMask_SS14_1      ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm 
N                                                                       comparison. Only SS[0] is compared. */
N#define RTC_AlarmSubSecondMask_SS14_2      ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm 
N                                                                       comparison. Only SS[1:0] are compared */
N#define RTC_AlarmSubSecondMask_SS14_3      ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm 
N                                                                       comparison. Only SS[2:0] are compared */
N#define RTC_AlarmSubSecondMask_SS14_4      ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm 
N                                                                       comparison. Only SS[3:0] are compared */
N#define RTC_AlarmSubSecondMask_SS14_5      ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm 
N                                                                       comparison. Only SS[4:0] are compared */
N#define RTC_AlarmSubSecondMask_SS14_6      ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm 
N                                                                       comparison. Only SS[5:0] are compared */
N#define RTC_AlarmSubSecondMask_SS14_7      ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm 
N                                                                       comparison. Only SS[6:0] are compared */
N#define RTC_AlarmSubSecondMask_SS14_8      ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm 
N                                                                       comparison. Only SS[7:0] are compared */
N#define RTC_AlarmSubSecondMask_SS14_9      ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm 
N                                                                       comparison. Only SS[8:0] are compared */
N#define RTC_AlarmSubSecondMask_SS14_10     ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm 
N                                                                       comparison. Only SS[9:0] are compared */
N#define RTC_AlarmSubSecondMask_SS14_11     ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm 
N                                                                       comparison. Only SS[10:0] are compared */
N#define RTC_AlarmSubSecondMask_SS14_12     ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm 
N                                                                       comparison.Only SS[11:0] are compared */
N#define RTC_AlarmSubSecondMask_SS14_13     ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm 
N                                                                       comparison. Only SS[12:0] are compared */
N#define RTC_AlarmSubSecondMask_SS14        ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm 
N                                                                       comparison.Only SS[13:0] are compared */
N#define RTC_AlarmSubSecondMask_None        ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match 
N                                                                       to activate alarm. */
N#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_AlarmSubSecondMask_All) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
N                                              ((MASK) == RTC_AlarmSubSecondMask_None))
X#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_AlarmSubSecondMask_All) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_1) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_2) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_3) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_4) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_5) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_6) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_7) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_8) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_9) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_10) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_11) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_12) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14_13) ||                                               ((MASK) == RTC_AlarmSubSecondMask_SS14) ||                                               ((MASK) == RTC_AlarmSubSecondMask_None))
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Alarm_Sub_Seconds_Value
N  * @{
N  */ 
N
N#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Wakeup_Timer_Definitions 
N  * @{
N  */ 
N#define RTC_WakeUpClock_RTCCLK_Div16        ((uint32_t)0x00000000)
N#define RTC_WakeUpClock_RTCCLK_Div8         ((uint32_t)0x00000001)
N#define RTC_WakeUpClock_RTCCLK_Div4         ((uint32_t)0x00000002)
N#define RTC_WakeUpClock_RTCCLK_Div2         ((uint32_t)0x00000003)
N#define RTC_WakeUpClock_CK_SPRE_16bits      ((uint32_t)0x00000004)
N#define RTC_WakeUpClock_CK_SPRE_17bits      ((uint32_t)0x00000006)
N#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
N                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
N                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
N                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
N                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
N                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
X#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) ||                                     ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) ||                                     ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) ||                                     ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) ||                                     ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) ||                                     ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
N#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Time_Stamp_Edges_definitions 
N  * @{
N  */ 
N#define RTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
N#define RTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
N#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
N                                     ((EDGE) == RTC_TimeStampEdge_Falling))
X#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) ||                                      ((EDGE) == RTC_TimeStampEdge_Falling))
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Output_selection_Definitions 
N  * @{
N  */ 
N#define RTC_Output_Disable             ((uint32_t)0x00000000)
N#define RTC_Output_AlarmA              ((uint32_t)0x00200000)
N#define RTC_Output_AlarmB              ((uint32_t)0x00400000)
N#define RTC_Output_WakeUp              ((uint32_t)0x00600000)
N 
N#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
N                               ((OUTPUT) == RTC_Output_AlarmA) || \
N                               ((OUTPUT) == RTC_Output_AlarmB) || \
N                               ((OUTPUT) == RTC_Output_WakeUp))
X#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) ||                                ((OUTPUT) == RTC_Output_AlarmA) ||                                ((OUTPUT) == RTC_Output_AlarmB) ||                                ((OUTPUT) == RTC_Output_WakeUp))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Output_Polarity_Definitions 
N  * @{
N  */ 
N#define RTC_OutputPolarity_High           ((uint32_t)0x00000000)
N#define RTC_OutputPolarity_Low            ((uint32_t)0x00100000)
N#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
N                                ((POL) == RTC_OutputPolarity_Low))
X#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) ||                                 ((POL) == RTC_OutputPolarity_Low))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup RTC_Digital_Calibration_Definitions 
N  * @{
N  */ 
N#define RTC_CalibSign_Positive            ((uint32_t)0x00000000) 
N#define RTC_CalibSign_Negative            ((uint32_t)0x00000080)
N#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
N                                 ((SIGN) == RTC_CalibSign_Negative))
X#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) ||                                  ((SIGN) == RTC_CalibSign_Negative))
N#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
N
N/**
N  * @}
N  */ 
N
N /** @defgroup RTC_Calib_Output_selection_Definitions 
N  * @{
N  */ 
N#define RTC_CalibOutput_512Hz            ((uint32_t)0x00000000) 
N#define RTC_CalibOutput_1Hz              ((uint32_t)0x00080000)
N#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CalibOutput_512Hz) || \
N                                      ((OUTPUT) == RTC_CalibOutput_1Hz))
X#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CalibOutput_512Hz) ||                                       ((OUTPUT) == RTC_CalibOutput_1Hz))
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Smooth_calib_period_Definitions 
N  * @{
N  */ 
N#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
N                                                             period is 32s,  else 2exp20 RTCCLK seconds */
N#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibration 
N                                                             period is 16s, else 2exp19 RTCCLK seconds */
N#define RTC_SmoothCalibPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
N                                                             period is 8s, else 2exp18 RTCCLK seconds */
N#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
N                                             ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
N                                             ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
X#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) ||                                              ((PERIOD) == RTC_SmoothCalibPeriod_16sec) ||                                              ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
N                                          
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions 
N  * @{
N  */ 
N#define RTC_SmoothCalibPlusPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added  
N                                                                during a X -second window = Y - CALM[8:0]. 
N                                                                 with Y = 512, 256, 128 when X = 32, 16, 8 */
N#define RTC_SmoothCalibPlusPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
N                                                                 during a 32-second window =   CALM[8:0]. */
N#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
N                                         ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
X#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) ||                                          ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions 
N  * @{
N  */ 
N#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
N
N/**
N  * @}
N  */
N
N/** @defgroup RTC_DayLightSaving_Definitions 
N  * @{
N  */ 
N#define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
N#define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
N#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
N                                      ((SAVE) == RTC_DayLightSaving_ADD1H))
X#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) ||                                       ((SAVE) == RTC_DayLightSaving_ADD1H))
N
N#define RTC_StoreOperation_Reset        ((uint32_t)0x00000000)
N#define RTC_StoreOperation_Set          ((uint32_t)0x00040000)
N#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
N                                           ((OPERATION) == RTC_StoreOperation_Set))
X#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) ||                                            ((OPERATION) == RTC_StoreOperation_Set))
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Tamper_Trigger_Definitions 
N  * @{
N  */ 
N#define RTC_TamperTrigger_RisingEdge            ((uint32_t)0x00000000)
N#define RTC_TamperTrigger_FallingEdge           ((uint32_t)0x00000001)
N#define RTC_TamperTrigger_LowLevel              ((uint32_t)0x00000000)
N#define RTC_TamperTrigger_HighLevel             ((uint32_t)0x00000001)
N#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
N                                        ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
N                                        ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
N                                        ((TRIGGER) == RTC_TamperTrigger_HighLevel)) 
X#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) ||                                         ((TRIGGER) == RTC_TamperTrigger_FallingEdge) ||                                         ((TRIGGER) == RTC_TamperTrigger_LowLevel) ||                                         ((TRIGGER) == RTC_TamperTrigger_HighLevel)) 
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Tamper_Filter_Definitions 
N  * @{
N  */ 
N#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
N
N#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2 
N                                                          consecutive samples at the active level */
N#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4 
N                                                          consecutive samples at the active level */
N#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8 
N                                                          consecutive samples at the active level. */
N#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
N                                      ((FILTER) == RTC_TamperFilter_2Sample) || \
N                                      ((FILTER) == RTC_TamperFilter_4Sample) || \
N                                      ((FILTER) == RTC_TamperFilter_8Sample))
X#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) ||                                       ((FILTER) == RTC_TamperFilter_2Sample) ||                                       ((FILTER) == RTC_TamperFilter_4Sample) ||                                       ((FILTER) == RTC_TamperFilter_8Sample))
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions 
N  * @{
N  */ 
N#define RTC_TamperSamplingFreq_RTCCLK_Div32768  ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
N                                                                           with a frequency =  RTCCLK / 32768 */
N#define RTC_TamperSamplingFreq_RTCCLK_Div16384  ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
N                                                                            with a frequency =  RTCCLK / 16384 */
N#define RTC_TamperSamplingFreq_RTCCLK_Div8192   ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
N                                                                           with a frequency =  RTCCLK / 8192  */
N#define RTC_TamperSamplingFreq_RTCCLK_Div4096   ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
N                                                                           with a frequency =  RTCCLK / 4096  */
N#define RTC_TamperSamplingFreq_RTCCLK_Div2048   ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
N                                                                           with a frequency =  RTCCLK / 2048  */
N#define RTC_TamperSamplingFreq_RTCCLK_Div1024   ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
N                                                                           with a frequency =  RTCCLK / 1024  */
N#define RTC_TamperSamplingFreq_RTCCLK_Div512    ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
N                                                                           with a frequency =  RTCCLK / 512   */
N#define RTC_TamperSamplingFreq_RTCCLK_Div256    ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
N                                                                           with a frequency =  RTCCLK / 256   */
N#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
N                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
N                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
N                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
N                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
N                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
N                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
N                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
X#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) ||                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) ||                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) ||                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) ||                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) ||                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) ||                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) ||                                            ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
N
N/**
N  * @}
N  */
N
N  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions 
N  * @{
N  */ 
N#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before 
N                                                                         sampling during 1 RTCCLK cycle */
N#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before 
N                                                                         sampling during 2 RTCCLK cycles */
N#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before 
N                                                                         sampling during 4 RTCCLK cycles */
N#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before 
N                                                                         sampling during 8 RTCCLK cycles */
N
N#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
N                                                    ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
N                                                    ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
N                                                    ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
X#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) ||                                                     ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) ||                                                     ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) ||                                                     ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
N/**
N  * @}
N  */
N
N/** @defgroup RTC_Tamper_Pins_Definitions 
N  * @{
N  */ 
N#define RTC_Tamper_1                    RTC_TAFCR_TAMP1E
N#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))
N
N/**
N  * @}
N  */
N
N/** @defgroup RTC_Tamper_Pin_Selection 
N  * @{
N  */ 
N#define RTC_TamperPin_PC13                 ((uint32_t)0x00000000)
N#define RTC_TamperPin_PI8                  ((uint32_t)0x00010000)
N#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \
N                                ((PIN) == RTC_TamperPin_PI8))
X#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) ||                                 ((PIN) == RTC_TamperPin_PI8))
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_TimeStamp_Pin_Selection 
N  * @{
N  */ 
N#define RTC_TimeStampPin_PC13              ((uint32_t)0x00000000)
N#define RTC_TimeStampPin_PI8               ((uint32_t)0x00020000)
N#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \
N                                   ((PIN) == RTC_TimeStampPin_PI8))
X#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) ||                                    ((PIN) == RTC_TimeStampPin_PI8))
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Output_Type_ALARM_OUT 
N  * @{
N  */ 
N#define RTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
N#define RTC_OutputType_PushPull            ((uint32_t)0x00040000)
N#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
N                                  ((TYPE) == RTC_OutputType_PushPull))
X#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) ||                                   ((TYPE) == RTC_OutputType_PushPull))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Add_1_Second_Parameter_Definitions
N  * @{
N  */ 
N#define RTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
N#define RTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
N#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
N                                 ((SEL) == RTC_ShiftAdd1S_Set))
X#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) ||                                  ((SEL) == RTC_ShiftAdd1S_Set))
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Substract_Fraction_Of_Second_Value
N  * @{
N  */ 
N#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
N
N/**
N  * @}
N  */
N
N/** @defgroup RTC_Backup_Registers_Definitions 
N  * @{
N  */
N
N#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
N#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
N#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
N#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
N#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
N#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
N#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
N#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
N#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
N#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
N#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
N#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
N#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
N#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
N#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
N#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
N#define RTC_BKP_DR16                      ((uint32_t)0x00000010)
N#define RTC_BKP_DR17                      ((uint32_t)0x00000011)
N#define RTC_BKP_DR18                      ((uint32_t)0x00000012)
N#define RTC_BKP_DR19                      ((uint32_t)0x00000013)
N#define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0) || \
N                                           ((BKP) == RTC_BKP_DR1) || \
N                                           ((BKP) == RTC_BKP_DR2) || \
N                                           ((BKP) == RTC_BKP_DR3) || \
N                                           ((BKP) == RTC_BKP_DR4) || \
N                                           ((BKP) == RTC_BKP_DR5) || \
N                                           ((BKP) == RTC_BKP_DR6) || \
N                                           ((BKP) == RTC_BKP_DR7) || \
N                                           ((BKP) == RTC_BKP_DR8) || \
N                                           ((BKP) == RTC_BKP_DR9) || \
N                                           ((BKP) == RTC_BKP_DR10) || \
N                                           ((BKP) == RTC_BKP_DR11) || \
N                                           ((BKP) == RTC_BKP_DR12) || \
N                                           ((BKP) == RTC_BKP_DR13) || \
N                                           ((BKP) == RTC_BKP_DR14) || \
N                                           ((BKP) == RTC_BKP_DR15) || \
N                                           ((BKP) == RTC_BKP_DR16) || \
N                                           ((BKP) == RTC_BKP_DR17) || \
N                                           ((BKP) == RTC_BKP_DR18) || \
N                                           ((BKP) == RTC_BKP_DR19))
X#define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0) ||                                            ((BKP) == RTC_BKP_DR1) ||                                            ((BKP) == RTC_BKP_DR2) ||                                            ((BKP) == RTC_BKP_DR3) ||                                            ((BKP) == RTC_BKP_DR4) ||                                            ((BKP) == RTC_BKP_DR5) ||                                            ((BKP) == RTC_BKP_DR6) ||                                            ((BKP) == RTC_BKP_DR7) ||                                            ((BKP) == RTC_BKP_DR8) ||                                            ((BKP) == RTC_BKP_DR9) ||                                            ((BKP) == RTC_BKP_DR10) ||                                            ((BKP) == RTC_BKP_DR11) ||                                            ((BKP) == RTC_BKP_DR12) ||                                            ((BKP) == RTC_BKP_DR13) ||                                            ((BKP) == RTC_BKP_DR14) ||                                            ((BKP) == RTC_BKP_DR15) ||                                            ((BKP) == RTC_BKP_DR16) ||                                            ((BKP) == RTC_BKP_DR17) ||                                            ((BKP) == RTC_BKP_DR18) ||                                            ((BKP) == RTC_BKP_DR19))
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Input_parameter_format_definitions 
N  * @{
N  */ 
N#define RTC_Format_BIN                    ((uint32_t)0x000000000)
N#define RTC_Format_BCD                    ((uint32_t)0x000000001)
N#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Flags_Definitions 
N  * @{
N  */ 
N#define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000)
N#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
N#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
N#define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
N#define RTC_FLAG_WUTF                     ((uint32_t)0x00000400)
N#define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200)
N#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
N#define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
N#define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
N#define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
N#define RTC_FLAG_SHPF                     ((uint32_t)0x00000008)
N#define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004)
N#define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002)
N#define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001)
N#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
N                               ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
N                               ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
N                               ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
N                               ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
N                               ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \
N                                ((FLAG) == RTC_FLAG_SHPF))
X#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) ||                                ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) ||                                ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) ||                                ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) ||                                ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) ||                                ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) ||                                 ((FLAG) == RTC_FLAG_SHPF))
N#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Interrupts_Definitions 
N  * @{
N  */ 
N#define RTC_IT_TS                         ((uint32_t)0x00008000)
N#define RTC_IT_WUT                        ((uint32_t)0x00004000)
N#define RTC_IT_ALRB                       ((uint32_t)0x00002000)
N#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
N#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
N#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
N
N#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
N#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
N                           ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
N                           ((IT) == RTC_IT_TAMP1))
X#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) ||                            ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) ||                            ((IT) == RTC_IT_TAMP1))
N#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup RTC_Legacy 
N  * @{
N  */ 
N#define RTC_DigitalCalibConfig  RTC_CoarseCalibConfig
N#define RTC_DigitalCalibCmd     RTC_CoarseCalibCmd
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N
N/*  Function used to set the RTC configuration to the default reset state *****/
NErrorStatus RTC_DeInit(void);
N
N/* Initialization and Configuration functions *********************************/
NErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
Nvoid RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
Nvoid RTC_WriteProtectionCmd(FunctionalState NewState);
NErrorStatus RTC_EnterInitMode(void);
Nvoid RTC_ExitInitMode(void);
NErrorStatus RTC_WaitForSynchro(void);
NErrorStatus RTC_RefClockCmd(FunctionalState NewState);
Nvoid RTC_BypassShadowCmd(FunctionalState NewState);
N
N/* Time and Date configuration functions **************************************/
NErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
Nvoid RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
Nvoid RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
Nuint32_t RTC_GetSubSecond(void);
NErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
Nvoid RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
Nvoid RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
N
N/* Alarms (Alarm A and Alarm B) configuration functions  **********************/
Nvoid RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
Nvoid RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
Nvoid RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
NErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
Nvoid RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
Nuint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
N
N/* WakeUp Timer configuration functions ***************************************/
Nvoid RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
Nvoid RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
Nuint32_t RTC_GetWakeUpCounter(void);
NErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
N
N/* Daylight Saving configuration functions ************************************/
Nvoid RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
Nuint32_t RTC_GetStoreOperation(void);
N
N/* Output pin Configuration function ******************************************/
Nvoid RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
N
N/* Digital Calibration configuration functions *********************************/
NErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
NErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
Nvoid RTC_CalibOutputCmd(FunctionalState NewState);
Nvoid RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
NErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, 
N                                  uint32_t RTC_SmoothCalibPlusPulses,
N                                  uint32_t RTC_SmouthCalibMinusPulsesValue);
N
N/* TimeStamp configuration functions ******************************************/
Nvoid RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
Nvoid RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
N                                      RTC_DateTypeDef* RTC_StampDateStruct);
Nuint32_t RTC_GetTimeStampSubSecond(void);
N
N/* Tampers configuration functions ********************************************/
Nvoid RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
Nvoid RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
Nvoid RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
Nvoid RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
Nvoid RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
Nvoid RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
Nvoid RTC_TamperPullUpCmd(FunctionalState NewState);
N
N/* Backup Data Registers configuration functions ******************************/
Nvoid RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
Nuint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
N
N/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
N   functions ******************************************************************/
Nvoid RTC_TamperPinSelection(uint32_t RTC_TamperPin);
Nvoid RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin);
Nvoid RTC_OutputTypeConfig(uint32_t RTC_OutputType);
N
N/* RTC_Shift_control_synchonisation_functions *********************************/
NErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
N
N/* Interrupts and flags management functions **********************************/
Nvoid RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
NFlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
Nvoid RTC_ClearFlag(uint32_t RTC_FLAG);
NITStatus RTC_GetITStatus(uint32_t RTC_IT);
Nvoid RTC_ClearITPendingBit(uint32_t RTC_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_RTC_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 46 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_sdio.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_sdio.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_sdio.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the SDIO firmware
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_SDIO_H
N#define __STM32F4xx_SDIO_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup SDIO
N  * @{
N  */
N
N/* Exported types ------------------------------------------------------------*/
N
Ntypedef struct
N{
N  uint32_t SDIO_ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
N                                           This parameter can be a value of @ref SDIO_Clock_Edge */
N
N  uint32_t SDIO_ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
N                                           enabled or disabled.
N                                           This parameter can be a value of @ref SDIO_Clock_Bypass */
N
N  uint32_t SDIO_ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
N                                           disabled when the bus is idle.
N                                           This parameter can be a value of @ref SDIO_Clock_Power_Save */
N
N  uint32_t SDIO_BusWide;              /*!< Specifies the SDIO bus width.
N                                           This parameter can be a value of @ref SDIO_Bus_Wide */
N
N  uint32_t SDIO_HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
N                                           This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
N
N  uint8_t SDIO_ClockDiv;              /*!< Specifies the clock frequency of the SDIO controller.
N                                           This parameter can be a value between 0x00 and 0xFF. */
N                                           
N} SDIO_InitTypeDef;
N
Ntypedef struct
N{
N  uint32_t SDIO_Argument;  /*!< Specifies the SDIO command argument which is sent
N                                to a card as part of a command message. If a command
N                                contains an argument, it must be loaded into this register
N                                before writing the command to the command register */
N
N  uint32_t SDIO_CmdIndex;  /*!< Specifies the SDIO command index. It must be lower than 0x40. */
N
N  uint32_t SDIO_Response;  /*!< Specifies the SDIO response type.
N                                This parameter can be a value of @ref SDIO_Response_Type */
N
N  uint32_t SDIO_Wait;      /*!< Specifies whether SDIO wait for interrupt request is enabled or disabled.
N                                This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
N
N  uint32_t SDIO_CPSM;      /*!< Specifies whether SDIO Command path state machine (CPSM)
N                                is enabled or disabled.
N                                This parameter can be a value of @ref SDIO_CPSM_State */
N} SDIO_CmdInitTypeDef;
N
Ntypedef struct
N{
N  uint32_t SDIO_DataTimeOut;    /*!< Specifies the data timeout period in card bus clock periods. */
N
N  uint32_t SDIO_DataLength;     /*!< Specifies the number of data bytes to be transferred. */
N 
N  uint32_t SDIO_DataBlockSize;  /*!< Specifies the data block size for block transfer.
N                                     This parameter can be a value of @ref SDIO_Data_Block_Size */
N 
N  uint32_t SDIO_TransferDir;    /*!< Specifies the data transfer direction, whether the transfer
N                                     is a read or write.
N                                     This parameter can be a value of @ref SDIO_Transfer_Direction */
N 
N  uint32_t SDIO_TransferMode;   /*!< Specifies whether data transfer is in stream or block mode.
N                                     This parameter can be a value of @ref SDIO_Transfer_Type */
N 
N  uint32_t SDIO_DPSM;           /*!< Specifies whether SDIO Data path state machine (DPSM)
N                                     is enabled or disabled.
N                                     This parameter can be a value of @ref SDIO_DPSM_State */
N} SDIO_DataInitTypeDef;
N
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup SDIO_Exported_Constants
N  * @{
N  */
N
N/** @defgroup SDIO_Clock_Edge 
N  * @{
N  */
N
N#define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
N#define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
N#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
N                                  ((EDGE) == SDIO_ClockEdge_Falling))
X#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) ||                                   ((EDGE) == SDIO_ClockEdge_Falling))
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_Clock_Bypass 
N  * @{
N  */
N
N#define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
N#define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)    
N#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
N                                     ((BYPASS) == SDIO_ClockBypass_Enable))
X#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) ||                                      ((BYPASS) == SDIO_ClockBypass_Enable))
N/**
N  * @}
N  */ 
N
N/** @defgroup SDIO_Clock_Power_Save 
N  * @{
N  */
N
N#define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
N#define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200) 
N#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
N                                        ((SAVE) == SDIO_ClockPowerSave_Enable))
X#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) ||                                         ((SAVE) == SDIO_ClockPowerSave_Enable))
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_Bus_Wide 
N  * @{
N  */
N
N#define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
N#define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
N#define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
N#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
N                                ((WIDE) == SDIO_BusWide_8b))
X#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) ||                                 ((WIDE) == SDIO_BusWide_8b))
N
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_Hardware_Flow_Control 
N  * @{
N  */
N
N#define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
N#define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
N#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
N                                                ((CONTROL) == SDIO_HardwareFlowControl_Enable))
X#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) ||                                                 ((CONTROL) == SDIO_HardwareFlowControl_Enable))
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_Power_State 
N  * @{
N  */
N
N#define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
N#define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
N#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup SDIO_Interrupt_sources
N  * @{
N  */
N
N#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
N#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
N#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
N#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
N#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
N#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
N#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
N#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
N#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
N#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
N#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
N#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
N#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
N#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
N#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
N#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
N#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
N#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
N#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
N#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
N#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
N#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
N#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
N#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
N#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
N/**
N  * @}
N  */ 
N
N/** @defgroup SDIO_Command_Index
N  * @{
N  */
N
N#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_Response_Type
N  * @{
N  */
N
N#define SDIO_Response_No                    ((uint32_t)0x00000000)
N#define SDIO_Response_Short                 ((uint32_t)0x00000040)
N#define SDIO_Response_Long                  ((uint32_t)0x000000C0)
N#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
N                                    ((RESPONSE) == SDIO_Response_Short) || \
N                                    ((RESPONSE) == SDIO_Response_Long))
X#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) ||                                     ((RESPONSE) == SDIO_Response_Short) ||                                     ((RESPONSE) == SDIO_Response_Long))
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_Wait_Interrupt_State
N  * @{
N  */
N
N#define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
N#define SDIO_Wait_IT                        ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
N#define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
N#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
N                            ((WAIT) == SDIO_Wait_Pend))
X#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) ||                             ((WAIT) == SDIO_Wait_Pend))
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_CPSM_State
N  * @{
N  */
N
N#define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
N#define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
N#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
N/**
N  * @}
N  */ 
N
N/** @defgroup SDIO_Response_Registers
N  * @{
N  */
N
N#define SDIO_RESP1                          ((uint32_t)0x00000000)
N#define SDIO_RESP2                          ((uint32_t)0x00000004)
N#define SDIO_RESP3                          ((uint32_t)0x00000008)
N#define SDIO_RESP4                          ((uint32_t)0x0000000C)
N#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
N                            ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
X#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) ||                             ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_Data_Length 
N  * @{
N  */
N
N#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_Data_Block_Size 
N  * @{
N  */
N
N#define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
N#define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
N#define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
N#define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
N#define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
N#define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
N#define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
N#define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
N#define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
N#define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
N#define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
N#define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
N#define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
N#define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
N#define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
N#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_2b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_4b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_8b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_16b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_32b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_64b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_128b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_256b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_512b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_1024b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_2048b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_4096b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_8192b) || \
N                                  ((SIZE) == SDIO_DataBlockSize_16384b)) 
X#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) ||                                   ((SIZE) == SDIO_DataBlockSize_2b) ||                                   ((SIZE) == SDIO_DataBlockSize_4b) ||                                   ((SIZE) == SDIO_DataBlockSize_8b) ||                                   ((SIZE) == SDIO_DataBlockSize_16b) ||                                   ((SIZE) == SDIO_DataBlockSize_32b) ||                                   ((SIZE) == SDIO_DataBlockSize_64b) ||                                   ((SIZE) == SDIO_DataBlockSize_128b) ||                                   ((SIZE) == SDIO_DataBlockSize_256b) ||                                   ((SIZE) == SDIO_DataBlockSize_512b) ||                                   ((SIZE) == SDIO_DataBlockSize_1024b) ||                                   ((SIZE) == SDIO_DataBlockSize_2048b) ||                                   ((SIZE) == SDIO_DataBlockSize_4096b) ||                                   ((SIZE) == SDIO_DataBlockSize_8192b) ||                                   ((SIZE) == SDIO_DataBlockSize_16384b)) 
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_Transfer_Direction 
N  * @{
N  */
N
N#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
N#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
N#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
N                                   ((DIR) == SDIO_TransferDir_ToSDIO))
X#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) ||                                    ((DIR) == SDIO_TransferDir_ToSDIO))
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_Transfer_Type 
N  * @{
N  */
N
N#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
N#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
N#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
N                                     ((MODE) == SDIO_TransferMode_Block))
X#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) ||                                      ((MODE) == SDIO_TransferMode_Block))
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_DPSM_State 
N  * @{
N  */
N
N#define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
N#define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
N#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_Flags 
N  * @{
N  */
N
N#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
N#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
N#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
N#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
N#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
N#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
N#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
N#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
N#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
N#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
N#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
N#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
N#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
N#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
N#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
N#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
N#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
N#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
N#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
N#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
N#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
N#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
N#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
N#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
N#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
N                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
N                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
N                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
N                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
N                            ((FLAG)  == SDIO_FLAG_RXOVERR) || \
N                            ((FLAG)  == SDIO_FLAG_CMDREND) || \
N                            ((FLAG)  == SDIO_FLAG_CMDSENT) || \
N                            ((FLAG)  == SDIO_FLAG_DATAEND) || \
N                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
N                            ((FLAG)  == SDIO_FLAG_DBCKEND) || \
N                            ((FLAG)  == SDIO_FLAG_CMDACT) || \
N                            ((FLAG)  == SDIO_FLAG_TXACT) || \
N                            ((FLAG)  == SDIO_FLAG_RXACT) || \
N                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
N                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
N                            ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
N                            ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
N                            ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
N                            ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
N                            ((FLAG)  == SDIO_FLAG_TXDAVL) || \
N                            ((FLAG)  == SDIO_FLAG_RXDAVL) || \
N                            ((FLAG)  == SDIO_FLAG_SDIOIT) || \
N                            ((FLAG)  == SDIO_FLAG_CEATAEND))
X#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) ||                             ((FLAG)  == SDIO_FLAG_DCRCFAIL) ||                             ((FLAG)  == SDIO_FLAG_CTIMEOUT) ||                             ((FLAG)  == SDIO_FLAG_DTIMEOUT) ||                             ((FLAG)  == SDIO_FLAG_TXUNDERR) ||                             ((FLAG)  == SDIO_FLAG_RXOVERR) ||                             ((FLAG)  == SDIO_FLAG_CMDREND) ||                             ((FLAG)  == SDIO_FLAG_CMDSENT) ||                             ((FLAG)  == SDIO_FLAG_DATAEND) ||                             ((FLAG)  == SDIO_FLAG_STBITERR) ||                             ((FLAG)  == SDIO_FLAG_DBCKEND) ||                             ((FLAG)  == SDIO_FLAG_CMDACT) ||                             ((FLAG)  == SDIO_FLAG_TXACT) ||                             ((FLAG)  == SDIO_FLAG_RXACT) ||                             ((FLAG)  == SDIO_FLAG_TXFIFOHE) ||                             ((FLAG)  == SDIO_FLAG_RXFIFOHF) ||                             ((FLAG)  == SDIO_FLAG_TXFIFOF) ||                             ((FLAG)  == SDIO_FLAG_RXFIFOF) ||                             ((FLAG)  == SDIO_FLAG_TXFIFOE) ||                             ((FLAG)  == SDIO_FLAG_RXFIFOE) ||                             ((FLAG)  == SDIO_FLAG_TXDAVL) ||                             ((FLAG)  == SDIO_FLAG_RXDAVL) ||                             ((FLAG)  == SDIO_FLAG_SDIOIT) ||                             ((FLAG)  == SDIO_FLAG_CEATAEND))
N
N#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
N
N#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
N                            ((IT)  == SDIO_IT_DCRCFAIL) || \
N                            ((IT)  == SDIO_IT_CTIMEOUT) || \
N                            ((IT)  == SDIO_IT_DTIMEOUT) || \
N                            ((IT)  == SDIO_IT_TXUNDERR) || \
N                            ((IT)  == SDIO_IT_RXOVERR) || \
N                            ((IT)  == SDIO_IT_CMDREND) || \
N                            ((IT)  == SDIO_IT_CMDSENT) || \
N                            ((IT)  == SDIO_IT_DATAEND) || \
N                            ((IT)  == SDIO_IT_STBITERR) || \
N                            ((IT)  == SDIO_IT_DBCKEND) || \
N                            ((IT)  == SDIO_IT_CMDACT) || \
N                            ((IT)  == SDIO_IT_TXACT) || \
N                            ((IT)  == SDIO_IT_RXACT) || \
N                            ((IT)  == SDIO_IT_TXFIFOHE) || \
N                            ((IT)  == SDIO_IT_RXFIFOHF) || \
N                            ((IT)  == SDIO_IT_TXFIFOF) || \
N                            ((IT)  == SDIO_IT_RXFIFOF) || \
N                            ((IT)  == SDIO_IT_TXFIFOE) || \
N                            ((IT)  == SDIO_IT_RXFIFOE) || \
N                            ((IT)  == SDIO_IT_TXDAVL) || \
N                            ((IT)  == SDIO_IT_RXDAVL) || \
N                            ((IT)  == SDIO_IT_SDIOIT) || \
N                            ((IT)  == SDIO_IT_CEATAEND))
X#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) ||                             ((IT)  == SDIO_IT_DCRCFAIL) ||                             ((IT)  == SDIO_IT_CTIMEOUT) ||                             ((IT)  == SDIO_IT_DTIMEOUT) ||                             ((IT)  == SDIO_IT_TXUNDERR) ||                             ((IT)  == SDIO_IT_RXOVERR) ||                             ((IT)  == SDIO_IT_CMDREND) ||                             ((IT)  == SDIO_IT_CMDSENT) ||                             ((IT)  == SDIO_IT_DATAEND) ||                             ((IT)  == SDIO_IT_STBITERR) ||                             ((IT)  == SDIO_IT_DBCKEND) ||                             ((IT)  == SDIO_IT_CMDACT) ||                             ((IT)  == SDIO_IT_TXACT) ||                             ((IT)  == SDIO_IT_RXACT) ||                             ((IT)  == SDIO_IT_TXFIFOHE) ||                             ((IT)  == SDIO_IT_RXFIFOHF) ||                             ((IT)  == SDIO_IT_TXFIFOF) ||                             ((IT)  == SDIO_IT_RXFIFOF) ||                             ((IT)  == SDIO_IT_TXFIFOE) ||                             ((IT)  == SDIO_IT_RXFIFOE) ||                             ((IT)  == SDIO_IT_TXDAVL) ||                             ((IT)  == SDIO_IT_RXDAVL) ||                             ((IT)  == SDIO_IT_SDIOIT) ||                             ((IT)  == SDIO_IT_CEATAEND))
N
N#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
N
N/**
N  * @}
N  */
N
N/** @defgroup SDIO_Read_Wait_Mode 
N  * @{
N  */
N
N#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000000)
N#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000001)
N#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
N                                     ((MODE) == SDIO_ReadWaitMode_DATA2))
X#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) ||                                      ((MODE) == SDIO_ReadWaitMode_DATA2))
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/
N/*  Function used to set the SDIO configuration to the default reset state ****/
Nvoid SDIO_DeInit(void);
N
N/* Initialization and Configuration functions *********************************/
Nvoid SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
Nvoid SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
Nvoid SDIO_ClockCmd(FunctionalState NewState);
Nvoid SDIO_SetPowerState(uint32_t SDIO_PowerState);
Nuint32_t SDIO_GetPowerState(void);
N
N/* Command path state machine (CPSM) management functions *********************/
Nvoid SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
Nvoid SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
Nuint8_t SDIO_GetCommandResponse(void);
Nuint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
N
N/* Data path state machine (DPSM) management functions ************************/
Nvoid SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
Nvoid SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
Nuint32_t SDIO_GetDataCounter(void);
Nuint32_t SDIO_ReadData(void);
Nvoid SDIO_WriteData(uint32_t Data);
Nuint32_t SDIO_GetFIFOCount(void);
N
N/* SDIO IO Cards mode management functions ************************************/
Nvoid SDIO_StartSDIOReadWait(FunctionalState NewState);
Nvoid SDIO_StopSDIOReadWait(FunctionalState NewState);
Nvoid SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
Nvoid SDIO_SetSDIOOperation(FunctionalState NewState);
Nvoid SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
N
N/* CE-ATA mode management functions *******************************************/
Nvoid SDIO_CommandCompletionCmd(FunctionalState NewState);
Nvoid SDIO_CEATAITCmd(FunctionalState NewState);
Nvoid SDIO_SendCEATACmd(FunctionalState NewState);
N
N/* DMA transfers management functions *****************************************/
Nvoid SDIO_DMACmd(FunctionalState NewState);
N
N/* Interrupts and flags management functions **********************************/
Nvoid SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
NFlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
Nvoid SDIO_ClearFlag(uint32_t SDIO_FLAG);
NITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
Nvoid SDIO_ClearITPendingBit(uint32_t SDIO_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __STM32F4xx_SDIO_H */
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 47 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_spi.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_spi.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_spi.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the SPI 
N  *          firmware library. 
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************  
N  */ 
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_SPI_H
N#define __STM32F4xx_SPI_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup SPI
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N
N/** 
N  * @brief  SPI Init structure definition  
N  */
N
Ntypedef struct
N{
N  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
N                                         This parameter can be a value of @ref SPI_data_direction */
N
N  uint16_t SPI_Mode;                /*!< Specifies the SPI operating mode.
N                                         This parameter can be a value of @ref SPI_mode */
N
N  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
N                                         This parameter can be a value of @ref SPI_data_size */
N
N  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
N                                         This parameter can be a value of @ref SPI_Clock_Polarity */
N
N  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
N                                         This parameter can be a value of @ref SPI_Clock_Phase */
N
N  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
N                                         hardware (NSS pin) or by software using the SSI bit.
N                                         This parameter can be a value of @ref SPI_Slave_Select_management */
N 
N  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
N                                         used to configure the transmit and receive SCK clock.
N                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler
N                                         @note The communication clock is derived from the master
N                                               clock. The slave clock does not need to be set. */
N
N  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
N                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
N
N  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
N}SPI_InitTypeDef;
N
N/** 
N  * @brief  I2S Init structure definition  
N  */
N
Ntypedef struct
N{
N
N  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
N                                  This parameter can be a value of @ref I2S_Mode */
N
N  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
N                                  This parameter can be a value of @ref I2S_Standard */
N
N  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
N                                  This parameter can be a value of @ref I2S_Data_Format */
N
N  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
N                                  This parameter can be a value of @ref I2S_MCLK_Output */
N
N  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
N                                  This parameter can be a value of @ref I2S_Audio_Frequency */
N
N  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
N                                  This parameter can be a value of @ref I2S_Clock_Polarity */
N}I2S_InitTypeDef;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup SPI_Exported_Constants
N  * @{
N  */
N
N#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
N                                   ((PERIPH) == SPI2) || \
N                                   ((PERIPH) == SPI3) || \
N                                   ((PERIPH) == SPI4) || \
N                                   ((PERIPH) == SPI5) || \
N                                   ((PERIPH) == SPI6))
X#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) ||                                    ((PERIPH) == SPI2) ||                                    ((PERIPH) == SPI3) ||                                    ((PERIPH) == SPI4) ||                                    ((PERIPH) == SPI5) ||                                    ((PERIPH) == SPI6))
N
N#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1)    || \
N                                       ((PERIPH) == SPI2)    || \
N                                       ((PERIPH) == SPI3)    || \
N                                       ((PERIPH) == SPI4)    || \
N                                       ((PERIPH) == SPI5)    || \
N                                       ((PERIPH) == SPI6)    || \
N                                       ((PERIPH) == I2S2ext) || \
N                                       ((PERIPH) == I2S3ext))
X#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1)    ||                                        ((PERIPH) == SPI2)    ||                                        ((PERIPH) == SPI3)    ||                                        ((PERIPH) == SPI4)    ||                                        ((PERIPH) == SPI5)    ||                                        ((PERIPH) == SPI6)    ||                                        ((PERIPH) == I2S2ext) ||                                        ((PERIPH) == I2S3ext))
N
N#define IS_SPI_23_PERIPH(PERIPH)  (((PERIPH) == SPI2) || \
N                                   ((PERIPH) == SPI3))
X#define IS_SPI_23_PERIPH(PERIPH)  (((PERIPH) == SPI2) ||                                    ((PERIPH) == SPI3))
N
N#define IS_SPI_23_PERIPH_EXT(PERIPH)  (((PERIPH) == SPI2)    || \
N                                       ((PERIPH) == SPI3)    || \
N                                       ((PERIPH) == I2S2ext) || \
N                                       ((PERIPH) == I2S3ext))
X#define IS_SPI_23_PERIPH_EXT(PERIPH)  (((PERIPH) == SPI2)    ||                                        ((PERIPH) == SPI3)    ||                                        ((PERIPH) == I2S2ext) ||                                        ((PERIPH) == I2S3ext))
N
N#define IS_I2S_EXT_PERIPH(PERIPH)  (((PERIPH) == I2S2ext) || \
N                                    ((PERIPH) == I2S3ext))
X#define IS_I2S_EXT_PERIPH(PERIPH)  (((PERIPH) == I2S2ext) ||                                     ((PERIPH) == I2S3ext))
N
N
N/** @defgroup SPI_data_direction 
N  * @{
N  */
N  
N#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
N#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
N#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
N#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
N#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
N                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
N                                     ((MODE) == SPI_Direction_1Line_Rx) || \
N                                     ((MODE) == SPI_Direction_1Line_Tx))
X#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) ||                                      ((MODE) == SPI_Direction_2Lines_RxOnly) ||                                      ((MODE) == SPI_Direction_1Line_Rx) ||                                      ((MODE) == SPI_Direction_1Line_Tx))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_mode 
N  * @{
N  */
N
N#define SPI_Mode_Master                 ((uint16_t)0x0104)
N#define SPI_Mode_Slave                  ((uint16_t)0x0000)
N#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
N                           ((MODE) == SPI_Mode_Slave))
X#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) ||                            ((MODE) == SPI_Mode_Slave))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_data_size 
N  * @{
N  */
N
N#define SPI_DataSize_16b                ((uint16_t)0x0800)
N#define SPI_DataSize_8b                 ((uint16_t)0x0000)
N#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
N                                   ((DATASIZE) == SPI_DataSize_8b))
X#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) ||                                    ((DATASIZE) == SPI_DataSize_8b))
N/**
N  * @}
N  */ 
N
N/** @defgroup SPI_Clock_Polarity 
N  * @{
N  */
N
N#define SPI_CPOL_Low                    ((uint16_t)0x0000)
N#define SPI_CPOL_High                   ((uint16_t)0x0002)
N#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
N                           ((CPOL) == SPI_CPOL_High))
X#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) ||                            ((CPOL) == SPI_CPOL_High))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_Clock_Phase 
N  * @{
N  */
N
N#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
N#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
N#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
N                           ((CPHA) == SPI_CPHA_2Edge))
X#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) ||                            ((CPHA) == SPI_CPHA_2Edge))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_Slave_Select_management 
N  * @{
N  */
N
N#define SPI_NSS_Soft                    ((uint16_t)0x0200)
N#define SPI_NSS_Hard                    ((uint16_t)0x0000)
N#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
N                         ((NSS) == SPI_NSS_Hard))
X#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) ||                          ((NSS) == SPI_NSS_Hard))
N/**
N  * @}
N  */ 
N
N/** @defgroup SPI_BaudRate_Prescaler 
N  * @{
N  */
N
N#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
N#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
N#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
N#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
N#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
N#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
N#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
N#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
N#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
N                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
N                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
N                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
N                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
N                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
N                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
N                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
X#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) ||                                               ((PRESCALER) == SPI_BaudRatePrescaler_4) ||                                               ((PRESCALER) == SPI_BaudRatePrescaler_8) ||                                               ((PRESCALER) == SPI_BaudRatePrescaler_16) ||                                               ((PRESCALER) == SPI_BaudRatePrescaler_32) ||                                               ((PRESCALER) == SPI_BaudRatePrescaler_64) ||                                               ((PRESCALER) == SPI_BaudRatePrescaler_128) ||                                               ((PRESCALER) == SPI_BaudRatePrescaler_256))
N/**
N  * @}
N  */ 
N
N/** @defgroup SPI_MSB_LSB_transmission 
N  * @{
N  */
N
N#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
N#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
N#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
N                               ((BIT) == SPI_FirstBit_LSB))
X#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) ||                                ((BIT) == SPI_FirstBit_LSB))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_I2S_Mode 
N  * @{
N  */
N
N#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
N#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
N#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
N#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
N#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
N                           ((MODE) == I2S_Mode_SlaveRx) || \
N                           ((MODE) == I2S_Mode_MasterTx)|| \
N                           ((MODE) == I2S_Mode_MasterRx))
X#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) ||                            ((MODE) == I2S_Mode_SlaveRx) ||                            ((MODE) == I2S_Mode_MasterTx)||                            ((MODE) == I2S_Mode_MasterRx))
N/**
N  * @}
N  */
N  
N
N/** @defgroup SPI_I2S_Standard 
N  * @{
N  */
N
N#define I2S_Standard_Phillips           ((uint16_t)0x0000)
N#define I2S_Standard_MSB                ((uint16_t)0x0010)
N#define I2S_Standard_LSB                ((uint16_t)0x0020)
N#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
N#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
N#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
N                                   ((STANDARD) == I2S_Standard_MSB) || \
N                                   ((STANDARD) == I2S_Standard_LSB) || \
N                                   ((STANDARD) == I2S_Standard_PCMShort) || \
N                                   ((STANDARD) == I2S_Standard_PCMLong))
X#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) ||                                    ((STANDARD) == I2S_Standard_MSB) ||                                    ((STANDARD) == I2S_Standard_LSB) ||                                    ((STANDARD) == I2S_Standard_PCMShort) ||                                    ((STANDARD) == I2S_Standard_PCMLong))
N/**
N  * @}
N  */
N  
N/** @defgroup SPI_I2S_Data_Format 
N  * @{
N  */
N
N#define I2S_DataFormat_16b              ((uint16_t)0x0000)
N#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
N#define I2S_DataFormat_24b              ((uint16_t)0x0003)
N#define I2S_DataFormat_32b              ((uint16_t)0x0005)
N#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
N                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
N                                    ((FORMAT) == I2S_DataFormat_24b) || \
N                                    ((FORMAT) == I2S_DataFormat_32b))
X#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) ||                                     ((FORMAT) == I2S_DataFormat_16bextended) ||                                     ((FORMAT) == I2S_DataFormat_24b) ||                                     ((FORMAT) == I2S_DataFormat_32b))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_I2S_MCLK_Output 
N  * @{
N  */
N
N#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
N#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
N#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
N                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
X#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) ||                                     ((OUTPUT) == I2S_MCLKOutput_Disable))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_I2S_Audio_Frequency 
N  * @{
N  */
N
N#define I2S_AudioFreq_192k               ((uint32_t)192000)
N#define I2S_AudioFreq_96k                ((uint32_t)96000)
N#define I2S_AudioFreq_48k                ((uint32_t)48000)
N#define I2S_AudioFreq_44k                ((uint32_t)44100)
N#define I2S_AudioFreq_32k                ((uint32_t)32000)
N#define I2S_AudioFreq_22k                ((uint32_t)22050)
N#define I2S_AudioFreq_16k                ((uint32_t)16000)
N#define I2S_AudioFreq_11k                ((uint32_t)11025)
N#define I2S_AudioFreq_8k                 ((uint32_t)8000)
N#define I2S_AudioFreq_Default            ((uint32_t)2)
N
N#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
N                                 ((FREQ) <= I2S_AudioFreq_192k)) || \
N                                 ((FREQ) == I2S_AudioFreq_Default))
X#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) &&                                  ((FREQ) <= I2S_AudioFreq_192k)) ||                                  ((FREQ) == I2S_AudioFreq_Default))
N/**
N  * @}
N  */
N            
N/** @defgroup SPI_I2S_Clock_Polarity 
N  * @{
N  */
N
N#define I2S_CPOL_Low                    ((uint16_t)0x0000)
N#define I2S_CPOL_High                   ((uint16_t)0x0008)
N#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
N                           ((CPOL) == I2S_CPOL_High))
X#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) ||                            ((CPOL) == I2S_CPOL_High))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_I2S_DMA_transfer_requests 
N  * @{
N  */
N
N#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
N#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
N#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_NSS_internal_software_management 
N  * @{
N  */
N
N#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
N#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
N#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
N                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
X#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) ||                                        ((INTERNAL) == SPI_NSSInternalSoft_Reset))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_CRC_Transmit_Receive 
N  * @{
N  */
N
N#define SPI_CRC_Tx                      ((uint8_t)0x00)
N#define SPI_CRC_Rx                      ((uint8_t)0x01)
N#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_direction_transmit_receive 
N  * @{
N  */
N
N#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
N#define SPI_Direction_Tx                ((uint16_t)0x4000)
N#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
N                                     ((DIRECTION) == SPI_Direction_Tx))
X#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) ||                                      ((DIRECTION) == SPI_Direction_Tx))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_I2S_interrupts_definition 
N  * @{
N  */
N
N#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
N#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
N#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
N#define I2S_IT_UDR                      ((uint8_t)0x53)
N#define SPI_I2S_IT_TIFRFE               ((uint8_t)0x58)
N
N#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
N                                  ((IT) == SPI_I2S_IT_RXNE) || \
N                                  ((IT) == SPI_I2S_IT_ERR))
X#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) ||                                   ((IT) == SPI_I2S_IT_RXNE) ||                                   ((IT) == SPI_I2S_IT_ERR))
N
N#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
N#define SPI_IT_MODF                     ((uint8_t)0x55)
N#define SPI_IT_CRCERR                   ((uint8_t)0x54)
N
N#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
N
N#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \
N                               ((IT) == SPI_IT_CRCERR)  || ((IT) == SPI_IT_MODF) || \
N                               ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
N                               ((IT) == SPI_I2S_IT_TIFRFE))
X#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) ||                                ((IT) == SPI_IT_CRCERR)  || ((IT) == SPI_IT_MODF) ||                                ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||                               ((IT) == SPI_I2S_IT_TIFRFE))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_I2S_flags_definition 
N  * @{
N  */
N
N#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
N#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
N#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
N#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
N#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
N#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
N#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
N#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
N#define SPI_I2S_FLAG_TIFRFE             ((uint16_t)0x0100)
N
N#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
N#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
N                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
N                                   ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
N                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
N                                   ((FLAG) == SPI_I2S_FLAG_TIFRFE))
X#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) ||                                    ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) ||                                    ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) ||                                    ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)||                                    ((FLAG) == SPI_I2S_FLAG_TIFRFE))
N/**
N  * @}
N  */
N
N/** @defgroup SPI_CRC_polynomial 
N  * @{
N  */
N
N#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
N/**
N  * @}
N  */
N
N/** @defgroup SPI_I2S_Legacy 
N  * @{
N  */
N
N#define SPI_DMAReq_Tx                SPI_I2S_DMAReq_Tx
N#define SPI_DMAReq_Rx                SPI_I2S_DMAReq_Rx
N#define SPI_IT_TXE                   SPI_I2S_IT_TXE
N#define SPI_IT_RXNE                  SPI_I2S_IT_RXNE
N#define SPI_IT_ERR                   SPI_I2S_IT_ERR
N#define SPI_IT_OVR                   SPI_I2S_IT_OVR
N#define SPI_FLAG_RXNE                SPI_I2S_FLAG_RXNE
N#define SPI_FLAG_TXE                 SPI_I2S_FLAG_TXE
N#define SPI_FLAG_OVR                 SPI_I2S_FLAG_OVR
N#define SPI_FLAG_BSY                 SPI_I2S_FLAG_BSY
N#define SPI_DeInit                   SPI_I2S_DeInit
N#define SPI_ITConfig                 SPI_I2S_ITConfig
N#define SPI_DMACmd                   SPI_I2S_DMACmd
N#define SPI_SendData                 SPI_I2S_SendData
N#define SPI_ReceiveData              SPI_I2S_ReceiveData
N#define SPI_GetFlagStatus            SPI_I2S_GetFlagStatus
N#define SPI_ClearFlag                SPI_I2S_ClearFlag
N#define SPI_GetITStatus              SPI_I2S_GetITStatus
N#define SPI_ClearITPendingBit        SPI_I2S_ClearITPendingBit
N/**
N  * @}
N  */
N  
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N
N/*  Function used to set the SPI configuration to the default reset state *****/ 
Nvoid SPI_I2S_DeInit(SPI_TypeDef* SPIx);
N
N/* Initialization and Configuration functions *********************************/
Nvoid SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
Nvoid I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
Nvoid SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
Nvoid I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
Nvoid SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
Nvoid I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
Nvoid SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
Nvoid SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
Nvoid SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
Nvoid SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
Nvoid SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
N
Nvoid I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
N
N/* Data transfers functions ***************************************************/ 
Nvoid SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
Nuint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
N
N/* Hardware CRC Calculation functions *****************************************/
Nvoid SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
Nvoid SPI_TransmitCRC(SPI_TypeDef* SPIx);
Nuint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
Nuint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
N
N/* DMA transfers management functions *****************************************/
Nvoid SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
N
N/* Interrupts and flags management functions **********************************/
Nvoid SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
NFlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
Nvoid SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
NITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
Nvoid SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_SPI_H */
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 48 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_syscfg.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_syscfg.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_syscfg.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the SYSCFG firmware
N  *          library. 
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_SYSCFG_H
N#define __STM32F4xx_SYSCFG_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup SYSCFG
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N/* Exported constants --------------------------------------------------------*/
N  
N/** @defgroup SYSCFG_Exported_Constants 
N  * @{
N  */ 
N
N/** @defgroup SYSCFG_EXTI_Port_Sources 
N  * @{
N  */ 
N#define EXTI_PortSourceGPIOA       ((uint8_t)0x00)
N#define EXTI_PortSourceGPIOB       ((uint8_t)0x01)
N#define EXTI_PortSourceGPIOC       ((uint8_t)0x02)
N#define EXTI_PortSourceGPIOD       ((uint8_t)0x03)
N#define EXTI_PortSourceGPIOE       ((uint8_t)0x04)
N#define EXTI_PortSourceGPIOF       ((uint8_t)0x05)
N#define EXTI_PortSourceGPIOG       ((uint8_t)0x06)
N#define EXTI_PortSourceGPIOH       ((uint8_t)0x07)
N#define EXTI_PortSourceGPIOI       ((uint8_t)0x08)
N#define EXTI_PortSourceGPIOJ       ((uint8_t)0x09)
N#define EXTI_PortSourceGPIOK       ((uint8_t)0x0A)
N
N#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
N                                         ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
N                                         ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
N                                         ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
N                                         ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
N                                         ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
N                                         ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
N                                         ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
N                                         ((PORTSOURCE) == EXTI_PortSourceGPIOI) || \
N                                         ((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \
N                                         ((PORTSOURCE) == EXTI_PortSourceGPIOK))
X#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) ||                                          ((PORTSOURCE) == EXTI_PortSourceGPIOB) ||                                          ((PORTSOURCE) == EXTI_PortSourceGPIOC) ||                                          ((PORTSOURCE) == EXTI_PortSourceGPIOD) ||                                          ((PORTSOURCE) == EXTI_PortSourceGPIOE) ||                                          ((PORTSOURCE) == EXTI_PortSourceGPIOF) ||                                          ((PORTSOURCE) == EXTI_PortSourceGPIOG) ||                                          ((PORTSOURCE) == EXTI_PortSourceGPIOH) ||                                          ((PORTSOURCE) == EXTI_PortSourceGPIOI) ||                                          ((PORTSOURCE) == EXTI_PortSourceGPIOJ) ||                                          ((PORTSOURCE) == EXTI_PortSourceGPIOK))
N                                         
N/**
N  * @}
N  */ 
N
N
N/** @defgroup SYSCFG_EXTI_Pin_Sources 
N  * @{
N  */ 
N#define EXTI_PinSource0            ((uint8_t)0x00)
N#define EXTI_PinSource1            ((uint8_t)0x01)
N#define EXTI_PinSource2            ((uint8_t)0x02)
N#define EXTI_PinSource3            ((uint8_t)0x03)
N#define EXTI_PinSource4            ((uint8_t)0x04)
N#define EXTI_PinSource5            ((uint8_t)0x05)
N#define EXTI_PinSource6            ((uint8_t)0x06)
N#define EXTI_PinSource7            ((uint8_t)0x07)
N#define EXTI_PinSource8            ((uint8_t)0x08)
N#define EXTI_PinSource9            ((uint8_t)0x09)
N#define EXTI_PinSource10           ((uint8_t)0x0A)
N#define EXTI_PinSource11           ((uint8_t)0x0B)
N#define EXTI_PinSource12           ((uint8_t)0x0C)
N#define EXTI_PinSource13           ((uint8_t)0x0D)
N#define EXTI_PinSource14           ((uint8_t)0x0E)
N#define EXTI_PinSource15           ((uint8_t)0x0F)
N#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0)  || \
N                                       ((PINSOURCE) == EXTI_PinSource1)  || \
N                                       ((PINSOURCE) == EXTI_PinSource2)  || \
N                                       ((PINSOURCE) == EXTI_PinSource3)  || \
N                                       ((PINSOURCE) == EXTI_PinSource4)  || \
N                                       ((PINSOURCE) == EXTI_PinSource5)  || \
N                                       ((PINSOURCE) == EXTI_PinSource6)  || \
N                                       ((PINSOURCE) == EXTI_PinSource7)  || \
N                                       ((PINSOURCE) == EXTI_PinSource8)  || \
N                                       ((PINSOURCE) == EXTI_PinSource9)  || \
N                                       ((PINSOURCE) == EXTI_PinSource10) || \
N                                       ((PINSOURCE) == EXTI_PinSource11) || \
N                                       ((PINSOURCE) == EXTI_PinSource12) || \
N                                       ((PINSOURCE) == EXTI_PinSource13) || \
N                                       ((PINSOURCE) == EXTI_PinSource14) || \
N                                       ((PINSOURCE) == EXTI_PinSource15))
X#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0)  ||                                        ((PINSOURCE) == EXTI_PinSource1)  ||                                        ((PINSOURCE) == EXTI_PinSource2)  ||                                        ((PINSOURCE) == EXTI_PinSource3)  ||                                        ((PINSOURCE) == EXTI_PinSource4)  ||                                        ((PINSOURCE) == EXTI_PinSource5)  ||                                        ((PINSOURCE) == EXTI_PinSource6)  ||                                        ((PINSOURCE) == EXTI_PinSource7)  ||                                        ((PINSOURCE) == EXTI_PinSource8)  ||                                        ((PINSOURCE) == EXTI_PinSource9)  ||                                        ((PINSOURCE) == EXTI_PinSource10) ||                                        ((PINSOURCE) == EXTI_PinSource11) ||                                        ((PINSOURCE) == EXTI_PinSource12) ||                                        ((PINSOURCE) == EXTI_PinSource13) ||                                        ((PINSOURCE) == EXTI_PinSource14) ||                                        ((PINSOURCE) == EXTI_PinSource15))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup SYSCFG_Memory_Remap_Config 
N  * @{
N  */ 
N#define SYSCFG_MemoryRemap_Flash       ((uint8_t)0x00)
N#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
N#define SYSCFG_MemoryRemap_SRAM        ((uint8_t)0x03)
N#define SYSCFG_MemoryRemap_SDRAM       ((uint8_t)0x04)
N
N#if defined (STM32F40_41xxx)
X#if 1L
N#define SYSCFG_MemoryRemap_FSMC        ((uint8_t)0x02) 
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
X#if 0L || 0L
S#define SYSCFG_MemoryRemap_FMC         ((uint8_t)0x02) 
N#endif /* STM32F427_437xx ||  STM32F429_439xx */  
N
N#if defined (STM32F446xx)
X#if 0L
S#define SYSCFG_MemoryRemap_ExtMEM      ((uint8_t)0x02) 
N#endif /*  STM32F446xx */ 
N
N#if defined (STM32F40_41xxx) 
X#if 1L 
N#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash)       || \
N                                               ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
N                                               ((REMAP) == SYSCFG_MemoryRemap_SRAM)        || \
N                                               ((REMAP) == SYSCFG_MemoryRemap_FSMC))
X#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash)       ||                                                ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) ||                                                ((REMAP) == SYSCFG_MemoryRemap_SRAM)        ||                                                ((REMAP) == SYSCFG_MemoryRemap_FSMC))
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F401xx) || defined (STM32F411xE)
X#if 0L || 0L
S#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash)       || \
S                                               ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
S                                               ((REMAP) == SYSCFG_MemoryRemap_SRAM))
X#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash)       ||                                                ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) ||                                                ((REMAP) == SYSCFG_MemoryRemap_SRAM))
N#endif /* STM32F401xx || STM32F411xE */
N
N#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
X#if 0L || 0L
S#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash)       || \
S                                               ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
S                                               ((REMAP) == SYSCFG_MemoryRemap_SRAM)        || \
S                                               ((REMAP) == SYSCFG_MemoryRemap_SDRAM)       || \
S                                               ((REMAP) == SYSCFG_MemoryRemap_FMC))
X#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash)       ||                                                ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) ||                                                ((REMAP) == SYSCFG_MemoryRemap_SRAM)        ||                                                ((REMAP) == SYSCFG_MemoryRemap_SDRAM)       ||                                                ((REMAP) == SYSCFG_MemoryRemap_FMC))
N#endif /* STM32F427_437xx ||  STM32F429_439xx */
N
N#if defined (STM32F446xx)
X#if 0L
S#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash)       || \
S                                               ((REMAP) == SYSCFG_MemoryRemap_ExtMEM)      || \
S                                               ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
S                                               ((REMAP) == SYSCFG_MemoryRemap_SRAM)        || \
S                                               ((REMAP) == SYSCFG_MemoryRemap_SDRAM))
X#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash)       ||                                                ((REMAP) == SYSCFG_MemoryRemap_ExtMEM)      ||                                                ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) ||                                                ((REMAP) == SYSCFG_MemoryRemap_SRAM)        ||                                                ((REMAP) == SYSCFG_MemoryRemap_SDRAM))
N#endif /* STM32F446xx */
N
N/**
N  * @}
N  */ 
N
N
N/** @defgroup SYSCFG_ETHERNET_Media_Interface 
N  * @{
N  */ 
N#define SYSCFG_ETH_MediaInterface_MII    ((uint32_t)0x00000000)
N#define SYSCFG_ETH_MediaInterface_RMII   ((uint32_t)0x00000001)
N
N#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \
N                                                 ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
X#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) ||                                                  ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N 
Nvoid       SYSCFG_DeInit(void);
Nvoid       SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
Nvoid       SYSCFG_MemorySwappingBank(FunctionalState NewState);
Nvoid       SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
Nvoid       SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); 
Nvoid       SYSCFG_CompensationCellCmd(FunctionalState NewState); 
NFlagStatus SYSCFG_GetCompensationCellStatus(void);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_SYSCFG_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 49 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_tim.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_tim.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_tim.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the TIM firmware 
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_TIM_H
N#define __STM32F4xx_TIM_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup TIM
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N
N/** 
N  * @brief  TIM Time Base Init structure definition  
N  * @note   This structure is used with all TIMx except for TIM6 and TIM7.  
N  */
N
Ntypedef struct
N{
N  uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
N                                       This parameter can be a number between 0x0000 and 0xFFFF */
N
N  uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
N                                       This parameter can be a value of @ref TIM_Counter_Mode */
N
N  uint32_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
N                                       Auto-Reload Register at the next update event.
N                                       This parameter must be a number between 0x0000 and 0xFFFF.  */ 
N
N  uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
N                                      This parameter can be a value of @ref TIM_Clock_Division_CKD */
N
N  uint8_t TIM_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
N                                       reaches zero, an update event is generated and counting restarts
N                                       from the RCR value (N).
N                                       This means in PWM mode that (N+1) corresponds to:
N                                          - the number of PWM periods in edge-aligned mode
N                                          - the number of half PWM period in center-aligned mode
N                                       This parameter must be a number between 0x00 and 0xFF. 
N                                       @note This parameter is valid only for TIM1 and TIM8. */
N} TIM_TimeBaseInitTypeDef; 
N
N/** 
N  * @brief  TIM Output Compare Init structure definition  
N  */
N
Ntypedef struct
N{
N  uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.
N                                   This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
N
N  uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
N                                   This parameter can be a value of @ref TIM_Output_Compare_State */
N
N  uint16_t TIM_OutputNState;  /*!< Specifies the TIM complementary Output Compare state.
N                                   This parameter can be a value of @ref TIM_Output_Compare_N_State
N                                   @note This parameter is valid only for TIM1 and TIM8. */
N
N  uint32_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
N                                   This parameter can be a number between 0x0000 and 0xFFFF */
N
N  uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
N                                   This parameter can be a value of @ref TIM_Output_Compare_Polarity */
N
N  uint16_t TIM_OCNPolarity;   /*!< Specifies the complementary output polarity.
N                                   This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
N                                   @note This parameter is valid only for TIM1 and TIM8. */
N
N  uint16_t TIM_OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
N                                   This parameter can be a value of @ref TIM_Output_Compare_Idle_State
N                                   @note This parameter is valid only for TIM1 and TIM8. */
N
N  uint16_t TIM_OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
N                                   This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
N                                   @note This parameter is valid only for TIM1 and TIM8. */
N} TIM_OCInitTypeDef;
N
N/** 
N  * @brief  TIM Input Capture Init structure definition  
N  */
N
Ntypedef struct
N{
N
N  uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
N                                  This parameter can be a value of @ref TIM_Channel */
N
N  uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
N                                  This parameter can be a value of @ref TIM_Input_Capture_Polarity */
N
N  uint16_t TIM_ICSelection;  /*!< Specifies the input.
N                                  This parameter can be a value of @ref TIM_Input_Capture_Selection */
N
N  uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
N                                  This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
N
N  uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
N                                  This parameter can be a number between 0x0 and 0xF */
N} TIM_ICInitTypeDef;
N
N/** 
N  * @brief  BDTR structure definition 
N  * @note   This structure is used only with TIM1 and TIM8.    
N  */
N
Ntypedef struct
N{
N
N  uint16_t TIM_OSSRState;        /*!< Specifies the Off-State selection used in Run mode.
N                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
N
N  uint16_t TIM_OSSIState;        /*!< Specifies the Off-State used in Idle state.
N                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
N
N  uint16_t TIM_LOCKLevel;        /*!< Specifies the LOCK level parameters.
N                                      This parameter can be a value of @ref TIM_Lock_level */ 
N
N  uint16_t TIM_DeadTime;         /*!< Specifies the delay time between the switching-off and the
N                                      switching-on of the outputs.
N                                      This parameter can be a number between 0x00 and 0xFF  */
N
N  uint16_t TIM_Break;            /*!< Specifies whether the TIM Break input is enabled or not. 
N                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
N
N  uint16_t TIM_BreakPolarity;    /*!< Specifies the TIM Break Input pin polarity.
N                                      This parameter can be a value of @ref TIM_Break_Polarity */
N
N  uint16_t TIM_AutomaticOutput;  /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 
N                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
N} TIM_BDTRInitTypeDef;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup TIM_Exported_constants 
N  * @{
N  */
N
N#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
N                                   ((PERIPH) == TIM2) || \
N                                   ((PERIPH) == TIM3) || \
N                                   ((PERIPH) == TIM4) || \
N                                   ((PERIPH) == TIM5) || \
N                                   ((PERIPH) == TIM6) || \
N                                   ((PERIPH) == TIM7) || \
N                                   ((PERIPH) == TIM8) || \
N                                   ((PERIPH) == TIM9) || \
N                                   ((PERIPH) == TIM10) || \
N                                   ((PERIPH) == TIM11) || \
N                                   ((PERIPH) == TIM12) || \
N                                   (((PERIPH) == TIM13) || \
N                                   ((PERIPH) == TIM14)))
X#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) ||                                    ((PERIPH) == TIM2) ||                                    ((PERIPH) == TIM3) ||                                    ((PERIPH) == TIM4) ||                                    ((PERIPH) == TIM5) ||                                    ((PERIPH) == TIM6) ||                                    ((PERIPH) == TIM7) ||                                    ((PERIPH) == TIM8) ||                                    ((PERIPH) == TIM9) ||                                    ((PERIPH) == TIM10) ||                                    ((PERIPH) == TIM11) ||                                    ((PERIPH) == TIM12) ||                                    (((PERIPH) == TIM13) ||                                    ((PERIPH) == TIM14)))
N/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */                                         
N#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
N                                     ((PERIPH) == TIM2) || \
N                                     ((PERIPH) == TIM3) || \
N                                     ((PERIPH) == TIM4) || \
N                                     ((PERIPH) == TIM5) || \
N                                     ((PERIPH) == TIM8) || \
N                                     ((PERIPH) == TIM9) || \
N                                     ((PERIPH) == TIM10) || \
N                                     ((PERIPH) == TIM11) || \
N                                     ((PERIPH) == TIM12) || \
N                                     ((PERIPH) == TIM13) || \
N                                     ((PERIPH) == TIM14))
X#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) ||                                      ((PERIPH) == TIM2) ||                                      ((PERIPH) == TIM3) ||                                      ((PERIPH) == TIM4) ||                                      ((PERIPH) == TIM5) ||                                      ((PERIPH) == TIM8) ||                                      ((PERIPH) == TIM9) ||                                      ((PERIPH) == TIM10) ||                                      ((PERIPH) == TIM11) ||                                      ((PERIPH) == TIM12) ||                                      ((PERIPH) == TIM13) ||                                      ((PERIPH) == TIM14))
N                                     
N/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */
N#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
N                                     ((PERIPH) == TIM2) || \
N                                     ((PERIPH) == TIM3) || \
N                                     ((PERIPH) == TIM4) || \
N                                     ((PERIPH) == TIM5) || \
N                                     ((PERIPH) == TIM8) || \
N                                     ((PERIPH) == TIM9) || \
N                                     ((PERIPH) == TIM12))
X#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) ||                                      ((PERIPH) == TIM2) ||                                      ((PERIPH) == TIM3) ||                                      ((PERIPH) == TIM4) ||                                      ((PERIPH) == TIM5) ||                                      ((PERIPH) == TIM8) ||                                      ((PERIPH) == TIM9) ||                                      ((PERIPH) == TIM12))
N/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */
N#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
N                                     ((PERIPH) == TIM2) || \
N                                     ((PERIPH) == TIM3) || \
N                                     ((PERIPH) == TIM4) || \
N                                     ((PERIPH) == TIM5) || \
N                                     ((PERIPH) == TIM8))
X#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) ||                                      ((PERIPH) == TIM2) ||                                      ((PERIPH) == TIM3) ||                                      ((PERIPH) == TIM4) ||                                      ((PERIPH) == TIM5) ||                                      ((PERIPH) == TIM8))
N/* LIST4: TIM1 and TIM8 */
N#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
N                                     ((PERIPH) == TIM8))
X#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) ||                                      ((PERIPH) == TIM8))
N/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
N#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
N                                     ((PERIPH) == TIM2) || \
N                                     ((PERIPH) == TIM3) || \
N                                     ((PERIPH) == TIM4) || \
N                                     ((PERIPH) == TIM5) || \
N                                     ((PERIPH) == TIM6) || \
N                                     ((PERIPH) == TIM7) || \
N                                     ((PERIPH) == TIM8))
X#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) ||                                      ((PERIPH) == TIM2) ||                                      ((PERIPH) == TIM3) ||                                      ((PERIPH) == TIM4) ||                                      ((PERIPH) == TIM5) ||                                      ((PERIPH) == TIM6) ||                                      ((PERIPH) == TIM7) ||                                      ((PERIPH) == TIM8))
N/* LIST6: TIM2, TIM5 and TIM11 */                               
N#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \
N                                 ((TIMx) == TIM5) || \
N                                 ((TIMx) == TIM11))
X#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) ||                                  ((TIMx) == TIM5) ||                                  ((TIMx) == TIM11))
N
N/** @defgroup TIM_Output_Compare_and_PWM_modes 
N  * @{
N  */
N
N#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
N#define TIM_OCMode_Active                  ((uint16_t)0x0010)
N#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
N#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
N#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
N#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
N#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
N                              ((MODE) == TIM_OCMode_Active) || \
N                              ((MODE) == TIM_OCMode_Inactive) || \
N                              ((MODE) == TIM_OCMode_Toggle)|| \
N                              ((MODE) == TIM_OCMode_PWM1) || \
N                              ((MODE) == TIM_OCMode_PWM2))
X#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) ||                               ((MODE) == TIM_OCMode_Active) ||                               ((MODE) == TIM_OCMode_Inactive) ||                               ((MODE) == TIM_OCMode_Toggle)||                               ((MODE) == TIM_OCMode_PWM1) ||                               ((MODE) == TIM_OCMode_PWM2))
N#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
N                          ((MODE) == TIM_OCMode_Active) || \
N                          ((MODE) == TIM_OCMode_Inactive) || \
N                          ((MODE) == TIM_OCMode_Toggle)|| \
N                          ((MODE) == TIM_OCMode_PWM1) || \
N                          ((MODE) == TIM_OCMode_PWM2) ||	\
N                          ((MODE) == TIM_ForcedAction_Active) || \
N                          ((MODE) == TIM_ForcedAction_InActive))
X#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) ||                           ((MODE) == TIM_OCMode_Active) ||                           ((MODE) == TIM_OCMode_Inactive) ||                           ((MODE) == TIM_OCMode_Toggle)||                           ((MODE) == TIM_OCMode_PWM1) ||                           ((MODE) == TIM_OCMode_PWM2) ||	                          ((MODE) == TIM_ForcedAction_Active) ||                           ((MODE) == TIM_ForcedAction_InActive))
N/**
N  * @}
N  */
N
N/** @defgroup TIM_One_Pulse_Mode 
N  * @{
N  */
N
N#define TIM_OPMode_Single                  ((uint16_t)0x0008)
N#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
N#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
N                               ((MODE) == TIM_OPMode_Repetitive))
X#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) ||                                ((MODE) == TIM_OPMode_Repetitive))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Channel 
N  * @{
N  */
N
N#define TIM_Channel_1                      ((uint16_t)0x0000)
N#define TIM_Channel_2                      ((uint16_t)0x0004)
N#define TIM_Channel_3                      ((uint16_t)0x0008)
N#define TIM_Channel_4                      ((uint16_t)0x000C)
N                                 
N#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
N                                 ((CHANNEL) == TIM_Channel_2) || \
N                                 ((CHANNEL) == TIM_Channel_3) || \
N                                 ((CHANNEL) == TIM_Channel_4))
X#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) ||                                  ((CHANNEL) == TIM_Channel_2) ||                                  ((CHANNEL) == TIM_Channel_3) ||                                  ((CHANNEL) == TIM_Channel_4))
N                                 
N#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
N                                      ((CHANNEL) == TIM_Channel_2))
X#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) ||                                       ((CHANNEL) == TIM_Channel_2))
N#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
N                                               ((CHANNEL) == TIM_Channel_2) || \
N                                               ((CHANNEL) == TIM_Channel_3))
X#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) ||                                                ((CHANNEL) == TIM_Channel_2) ||                                                ((CHANNEL) == TIM_Channel_3))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Clock_Division_CKD 
N  * @{
N  */
N
N#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
N#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
N#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
N#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
N                             ((DIV) == TIM_CKD_DIV2) || \
N                             ((DIV) == TIM_CKD_DIV4))
X#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) ||                              ((DIV) == TIM_CKD_DIV2) ||                              ((DIV) == TIM_CKD_DIV4))
N/**
N  * @}
N  */
N
N/** @defgroup TIM_Counter_Mode 
N  * @{
N  */
N
N#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
N#define TIM_CounterMode_Down               ((uint16_t)0x0010)
N#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
N#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
N#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
N#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
N                                   ((MODE) == TIM_CounterMode_Down) || \
N                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
N                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
N                                   ((MODE) == TIM_CounterMode_CenterAligned3))
X#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||                                     ((MODE) == TIM_CounterMode_Down) ||                                    ((MODE) == TIM_CounterMode_CenterAligned1) ||                                    ((MODE) == TIM_CounterMode_CenterAligned2) ||                                    ((MODE) == TIM_CounterMode_CenterAligned3))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Output_Compare_Polarity 
N  * @{
N  */
N
N#define TIM_OCPolarity_High                ((uint16_t)0x0000)
N#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
N#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
N                                      ((POLARITY) == TIM_OCPolarity_Low))
X#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) ||                                       ((POLARITY) == TIM_OCPolarity_Low))
N/**
N  * @}
N  */
N
N/** @defgroup TIM_Output_Compare_N_Polarity 
N  * @{
N  */
N  
N#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
N#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
N#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
N                                       ((POLARITY) == TIM_OCNPolarity_Low))
X#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) ||                                        ((POLARITY) == TIM_OCNPolarity_Low))
N/**
N  * @}
N  */
N
N/** @defgroup TIM_Output_Compare_State 
N  * @{
N  */
N
N#define TIM_OutputState_Disable            ((uint16_t)0x0000)
N#define TIM_OutputState_Enable             ((uint16_t)0x0001)
N#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
N                                    ((STATE) == TIM_OutputState_Enable))
X#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) ||                                     ((STATE) == TIM_OutputState_Enable))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Output_Compare_N_State
N  * @{
N  */
N
N#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
N#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
N#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
N                                     ((STATE) == TIM_OutputNState_Enable))
X#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) ||                                      ((STATE) == TIM_OutputNState_Enable))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Capture_Compare_State
N  * @{
N  */
N
N#define TIM_CCx_Enable                      ((uint16_t)0x0001)
N#define TIM_CCx_Disable                     ((uint16_t)0x0000)
N#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
N                         ((CCX) == TIM_CCx_Disable))
X#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) ||                          ((CCX) == TIM_CCx_Disable))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Capture_Compare_N_State
N  * @{
N  */
N
N#define TIM_CCxN_Enable                     ((uint16_t)0x0004)
N#define TIM_CCxN_Disable                    ((uint16_t)0x0000)
N#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
N                           ((CCXN) == TIM_CCxN_Disable))
X#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) ||                            ((CCXN) == TIM_CCxN_Disable))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Break_Input_enable_disable 
N  * @{
N  */
N
N#define TIM_Break_Enable                   ((uint16_t)0x1000)
N#define TIM_Break_Disable                  ((uint16_t)0x0000)
N#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
N                                   ((STATE) == TIM_Break_Disable))
X#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) ||                                    ((STATE) == TIM_Break_Disable))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Break_Polarity 
N  * @{
N  */
N
N#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
N#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
N#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
N                                         ((POLARITY) == TIM_BreakPolarity_High))
X#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) ||                                          ((POLARITY) == TIM_BreakPolarity_High))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_AOE_Bit_Set_Reset 
N  * @{
N  */
N
N#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
N#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
N#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
N                                              ((STATE) == TIM_AutomaticOutput_Disable))
X#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) ||                                               ((STATE) == TIM_AutomaticOutput_Disable))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Lock_level
N  * @{
N  */
N
N#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
N#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
N#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
N#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
N#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
N                                  ((LEVEL) == TIM_LOCKLevel_1) || \
N                                  ((LEVEL) == TIM_LOCKLevel_2) || \
N                                  ((LEVEL) == TIM_LOCKLevel_3))
X#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) ||                                   ((LEVEL) == TIM_LOCKLevel_1) ||                                   ((LEVEL) == TIM_LOCKLevel_2) ||                                   ((LEVEL) == TIM_LOCKLevel_3))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state 
N  * @{
N  */
N
N#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
N#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
N#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
N                                  ((STATE) == TIM_OSSIState_Disable))
X#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) ||                                   ((STATE) == TIM_OSSIState_Disable))
N/**
N  * @}
N  */
N
N/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
N  * @{
N  */
N
N#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
N#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
N#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
N                                  ((STATE) == TIM_OSSRState_Disable))
X#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) ||                                   ((STATE) == TIM_OSSRState_Disable))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Output_Compare_Idle_State 
N  * @{
N  */
N
N#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
N#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
N#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
N                                    ((STATE) == TIM_OCIdleState_Reset))
X#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) ||                                     ((STATE) == TIM_OCIdleState_Reset))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Output_Compare_N_Idle_State 
N  * @{
N  */
N
N#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
N#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
N#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
N                                     ((STATE) == TIM_OCNIdleState_Reset))
X#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) ||                                      ((STATE) == TIM_OCNIdleState_Reset))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Input_Capture_Polarity 
N  * @{
N  */
N
N#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
N#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
N#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
N#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
N                                      ((POLARITY) == TIM_ICPolarity_Falling)|| \
N                                      ((POLARITY) == TIM_ICPolarity_BothEdge))
X#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) ||                                       ((POLARITY) == TIM_ICPolarity_Falling)||                                       ((POLARITY) == TIM_ICPolarity_BothEdge))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Input_Capture_Selection 
N  * @{
N  */
N
N#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 
N                                                                   connected to IC1, IC2, IC3 or IC4, respectively */
N#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
N                                                                   connected to IC2, IC1, IC4 or IC3, respectively. */
N#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
N#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
N                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
N                                        ((SELECTION) == TIM_ICSelection_TRC))
X#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) ||                                         ((SELECTION) == TIM_ICSelection_IndirectTI) ||                                         ((SELECTION) == TIM_ICSelection_TRC))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Input_Capture_Prescaler 
N  * @{
N  */
N
N#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
N#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
N#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
N#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
N#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
N                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
N                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
N                                        ((PRESCALER) == TIM_ICPSC_DIV8))
X#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) ||                                         ((PRESCALER) == TIM_ICPSC_DIV2) ||                                         ((PRESCALER) == TIM_ICPSC_DIV4) ||                                         ((PRESCALER) == TIM_ICPSC_DIV8))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_interrupt_sources 
N  * @{
N  */
N
N#define TIM_IT_Update                      ((uint16_t)0x0001)
N#define TIM_IT_CC1                         ((uint16_t)0x0002)
N#define TIM_IT_CC2                         ((uint16_t)0x0004)
N#define TIM_IT_CC3                         ((uint16_t)0x0008)
N#define TIM_IT_CC4                         ((uint16_t)0x0010)
N#define TIM_IT_COM                         ((uint16_t)0x0020)
N#define TIM_IT_Trigger                     ((uint16_t)0x0040)
N#define TIM_IT_Break                       ((uint16_t)0x0080)
N#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
N
N#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
N                           ((IT) == TIM_IT_CC1) || \
N                           ((IT) == TIM_IT_CC2) || \
N                           ((IT) == TIM_IT_CC3) || \
N                           ((IT) == TIM_IT_CC4) || \
N                           ((IT) == TIM_IT_COM) || \
N                           ((IT) == TIM_IT_Trigger) || \
N                           ((IT) == TIM_IT_Break))
X#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) ||                            ((IT) == TIM_IT_CC1) ||                            ((IT) == TIM_IT_CC2) ||                            ((IT) == TIM_IT_CC3) ||                            ((IT) == TIM_IT_CC4) ||                            ((IT) == TIM_IT_COM) ||                            ((IT) == TIM_IT_Trigger) ||                            ((IT) == TIM_IT_Break))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_DMA_Base_address 
N  * @{
N  */
N
N#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
N#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
N#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
N#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
N#define TIM_DMABase_SR                     ((uint16_t)0x0004)
N#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
N#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
N#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
N#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
N#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
N#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
N#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
N#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
N#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
N#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
N#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
N#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
N#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
N#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
N#define TIM_DMABase_OR                     ((uint16_t)0x0013)
N#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
N                               ((BASE) == TIM_DMABase_CR2) || \
N                               ((BASE) == TIM_DMABase_SMCR) || \
N                               ((BASE) == TIM_DMABase_DIER) || \
N                               ((BASE) == TIM_DMABase_SR) || \
N                               ((BASE) == TIM_DMABase_EGR) || \
N                               ((BASE) == TIM_DMABase_CCMR1) || \
N                               ((BASE) == TIM_DMABase_CCMR2) || \
N                               ((BASE) == TIM_DMABase_CCER) || \
N                               ((BASE) == TIM_DMABase_CNT) || \
N                               ((BASE) == TIM_DMABase_PSC) || \
N                               ((BASE) == TIM_DMABase_ARR) || \
N                               ((BASE) == TIM_DMABase_RCR) || \
N                               ((BASE) == TIM_DMABase_CCR1) || \
N                               ((BASE) == TIM_DMABase_CCR2) || \
N                               ((BASE) == TIM_DMABase_CCR3) || \
N                               ((BASE) == TIM_DMABase_CCR4) || \
N                               ((BASE) == TIM_DMABase_BDTR) || \
N                               ((BASE) == TIM_DMABase_DCR) || \
N                               ((BASE) == TIM_DMABase_OR))                     
X#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) ||                                ((BASE) == TIM_DMABase_CR2) ||                                ((BASE) == TIM_DMABase_SMCR) ||                                ((BASE) == TIM_DMABase_DIER) ||                                ((BASE) == TIM_DMABase_SR) ||                                ((BASE) == TIM_DMABase_EGR) ||                                ((BASE) == TIM_DMABase_CCMR1) ||                                ((BASE) == TIM_DMABase_CCMR2) ||                                ((BASE) == TIM_DMABase_CCER) ||                                ((BASE) == TIM_DMABase_CNT) ||                                ((BASE) == TIM_DMABase_PSC) ||                                ((BASE) == TIM_DMABase_ARR) ||                                ((BASE) == TIM_DMABase_RCR) ||                                ((BASE) == TIM_DMABase_CCR1) ||                                ((BASE) == TIM_DMABase_CCR2) ||                                ((BASE) == TIM_DMABase_CCR3) ||                                ((BASE) == TIM_DMABase_CCR4) ||                                ((BASE) == TIM_DMABase_BDTR) ||                                ((BASE) == TIM_DMABase_DCR) ||                                ((BASE) == TIM_DMABase_OR))                     
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_DMA_Burst_Length 
N  * @{
N  */
N
N#define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
N#define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
N#define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
N#define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
N#define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
N#define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
N#define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
N#define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
N#define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
N#define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
N#define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
N#define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
N#define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
N#define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
N#define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
N#define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
N#define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
N#define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
N#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
N                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
N                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))
X#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) ||                                    ((LENGTH) == TIM_DMABurstLength_2Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_3Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_4Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_5Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_6Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_7Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_8Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_9Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_10Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_11Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_12Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_13Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_14Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_15Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_16Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_17Transfers) ||                                    ((LENGTH) == TIM_DMABurstLength_18Transfers))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_DMA_sources 
N  * @{
N  */
N
N#define TIM_DMA_Update                     ((uint16_t)0x0100)
N#define TIM_DMA_CC1                        ((uint16_t)0x0200)
N#define TIM_DMA_CC2                        ((uint16_t)0x0400)
N#define TIM_DMA_CC3                        ((uint16_t)0x0800)
N#define TIM_DMA_CC4                        ((uint16_t)0x1000)
N#define TIM_DMA_COM                        ((uint16_t)0x2000)
N#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
N#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_External_Trigger_Prescaler 
N  * @{
N  */
N
N#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
N#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
N#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
N#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
N#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
N                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
N                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
N                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
X#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) ||                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV2) ||                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV4) ||                                          ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Internal_Trigger_Selection 
N  * @{
N  */
N
N#define TIM_TS_ITR0                        ((uint16_t)0x0000)
N#define TIM_TS_ITR1                        ((uint16_t)0x0010)
N#define TIM_TS_ITR2                        ((uint16_t)0x0020)
N#define TIM_TS_ITR3                        ((uint16_t)0x0030)
N#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
N#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
N#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
N#define TIM_TS_ETRF                        ((uint16_t)0x0070)
N#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
N                                             ((SELECTION) == TIM_TS_ITR1) || \
N                                             ((SELECTION) == TIM_TS_ITR2) || \
N                                             ((SELECTION) == TIM_TS_ITR3) || \
N                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
N                                             ((SELECTION) == TIM_TS_TI1FP1) || \
N                                             ((SELECTION) == TIM_TS_TI2FP2) || \
N                                             ((SELECTION) == TIM_TS_ETRF))
X#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) ||                                              ((SELECTION) == TIM_TS_ITR1) ||                                              ((SELECTION) == TIM_TS_ITR2) ||                                              ((SELECTION) == TIM_TS_ITR3) ||                                              ((SELECTION) == TIM_TS_TI1F_ED) ||                                              ((SELECTION) == TIM_TS_TI1FP1) ||                                              ((SELECTION) == TIM_TS_TI2FP2) ||                                              ((SELECTION) == TIM_TS_ETRF))
N#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
N                                                      ((SELECTION) == TIM_TS_ITR1) || \
N                                                      ((SELECTION) == TIM_TS_ITR2) || \
N                                                      ((SELECTION) == TIM_TS_ITR3))
X#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) ||                                                       ((SELECTION) == TIM_TS_ITR1) ||                                                       ((SELECTION) == TIM_TS_ITR2) ||                                                       ((SELECTION) == TIM_TS_ITR3))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_TIx_External_Clock_Source 
N  * @{
N  */
N
N#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
N#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
N#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
N
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_External_Trigger_Polarity 
N  * @{
N  */ 
N#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
N#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
N#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
N                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
X#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) ||                                        ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
N/**
N  * @}
N  */
N
N/** @defgroup TIM_Prescaler_Reload_Mode 
N  * @{
N  */
N
N#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
N#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
N#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
N                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))
X#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) ||                                          ((RELOAD) == TIM_PSCReloadMode_Immediate))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Forced_Action 
N  * @{
N  */
N
N#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
N#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
N#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
N                                      ((ACTION) == TIM_ForcedAction_InActive))
X#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) ||                                       ((ACTION) == TIM_ForcedAction_InActive))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Encoder_Mode 
N  * @{
N  */
N
N#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
N#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
N#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
N#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
N                                   ((MODE) == TIM_EncoderMode_TI2) || \
N                                   ((MODE) == TIM_EncoderMode_TI12))
X#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) ||                                    ((MODE) == TIM_EncoderMode_TI2) ||                                    ((MODE) == TIM_EncoderMode_TI12))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup TIM_Event_Source 
N  * @{
N  */
N
N#define TIM_EventSource_Update             ((uint16_t)0x0001)
N#define TIM_EventSource_CC1                ((uint16_t)0x0002)
N#define TIM_EventSource_CC2                ((uint16_t)0x0004)
N#define TIM_EventSource_CC3                ((uint16_t)0x0008)
N#define TIM_EventSource_CC4                ((uint16_t)0x0010)
N#define TIM_EventSource_COM                ((uint16_t)0x0020)
N#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
N#define TIM_EventSource_Break              ((uint16_t)0x0080)
N#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))                                          
N  
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Update_Source 
N  * @{
N  */
N
N#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
N                                                                   or the setting of UG bit, or an update generation
N                                                                   through the slave mode controller. */
N#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
N#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
N                                      ((SOURCE) == TIM_UpdateSource_Regular))
X#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) ||                                       ((SOURCE) == TIM_UpdateSource_Regular))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Output_Compare_Preload_State 
N  * @{
N  */
N
N#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
N#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
N#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
N                                       ((STATE) == TIM_OCPreload_Disable))
X#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) ||                                        ((STATE) == TIM_OCPreload_Disable))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Output_Compare_Fast_State 
N  * @{
N  */
N
N#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
N#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
N#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
N                                    ((STATE) == TIM_OCFast_Disable))
X#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) ||                                     ((STATE) == TIM_OCFast_Disable))
N                                     
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Output_Compare_Clear_State 
N  * @{
N  */
N
N#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
N#define TIM_OCClear_Disable                ((uint16_t)0x0000)
N#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
N                                     ((STATE) == TIM_OCClear_Disable))
X#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) ||                                      ((STATE) == TIM_OCClear_Disable))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Trigger_Output_Source 
N  * @{
N  */
N
N#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
N#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
N#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
N#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
N#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
N#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
N#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
N#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
N#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
N                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
N                                    ((SOURCE) == TIM_TRGOSource_Update) || \
N                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
N                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
N                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
N                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
N                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))
X#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) ||                                     ((SOURCE) == TIM_TRGOSource_Enable) ||                                     ((SOURCE) == TIM_TRGOSource_Update) ||                                     ((SOURCE) == TIM_TRGOSource_OC1) ||                                     ((SOURCE) == TIM_TRGOSource_OC1Ref) ||                                     ((SOURCE) == TIM_TRGOSource_OC2Ref) ||                                     ((SOURCE) == TIM_TRGOSource_OC3Ref) ||                                     ((SOURCE) == TIM_TRGOSource_OC4Ref))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Slave_Mode 
N  * @{
N  */
N
N#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
N#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
N#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
N#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
N#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
N                                 ((MODE) == TIM_SlaveMode_Gated) || \
N                                 ((MODE) == TIM_SlaveMode_Trigger) || \
N                                 ((MODE) == TIM_SlaveMode_External1))
X#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) ||                                  ((MODE) == TIM_SlaveMode_Gated) ||                                  ((MODE) == TIM_SlaveMode_Trigger) ||                                  ((MODE) == TIM_SlaveMode_External1))
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Master_Slave_Mode 
N  * @{
N  */
N
N#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
N#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
N#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
N                                 ((STATE) == TIM_MasterSlaveMode_Disable))
X#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) ||                                  ((STATE) == TIM_MasterSlaveMode_Disable))
N/**
N  * @}
N  */ 
N/** @defgroup TIM_Remap 
N  * @{
N  */
N
N#define TIM2_TIM8_TRGO                     ((uint16_t)0x0000)
N#define TIM2_ETH_PTP                       ((uint16_t)0x0400)
N#define TIM2_USBFS_SOF                     ((uint16_t)0x0800)
N#define TIM2_USBHS_SOF                     ((uint16_t)0x0C00)
N
N#define TIM5_GPIO                          ((uint16_t)0x0000)
N#define TIM5_LSI                           ((uint16_t)0x0040)
N#define TIM5_LSE                           ((uint16_t)0x0080)
N#define TIM5_RTC                           ((uint16_t)0x00C0)
N
N#define TIM11_GPIO                         ((uint16_t)0x0000)
N#define TIM11_HSE                          ((uint16_t)0x0002)
N
N#define IS_TIM_REMAP(TIM_REMAP)	 (((TIM_REMAP) == TIM2_TIM8_TRGO)||\
N                                  ((TIM_REMAP) == TIM2_ETH_PTP)||\
N                                  ((TIM_REMAP) == TIM2_USBFS_SOF)||\
N                                  ((TIM_REMAP) == TIM2_USBHS_SOF)||\
N                                  ((TIM_REMAP) == TIM5_GPIO)||\
N                                  ((TIM_REMAP) == TIM5_LSI)||\
N                                  ((TIM_REMAP) == TIM5_LSE)||\
N                                  ((TIM_REMAP) == TIM5_RTC)||\
N                                  ((TIM_REMAP) == TIM11_GPIO)||\
N                                  ((TIM_REMAP) == TIM11_HSE))
X#define IS_TIM_REMAP(TIM_REMAP)	 (((TIM_REMAP) == TIM2_TIM8_TRGO)||                                  ((TIM_REMAP) == TIM2_ETH_PTP)||                                  ((TIM_REMAP) == TIM2_USBFS_SOF)||                                  ((TIM_REMAP) == TIM2_USBHS_SOF)||                                  ((TIM_REMAP) == TIM5_GPIO)||                                  ((TIM_REMAP) == TIM5_LSI)||                                  ((TIM_REMAP) == TIM5_LSE)||                                  ((TIM_REMAP) == TIM5_RTC)||                                  ((TIM_REMAP) == TIM11_GPIO)||                                  ((TIM_REMAP) == TIM11_HSE))
N
N/**
N  * @}
N  */ 
N/** @defgroup TIM_Flags 
N  * @{
N  */
N
N#define TIM_FLAG_Update                    ((uint16_t)0x0001)
N#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
N#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
N#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
N#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
N#define TIM_FLAG_COM                       ((uint16_t)0x0020)
N#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
N#define TIM_FLAG_Break                     ((uint16_t)0x0080)
N#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
N#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
N#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
N#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
N#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
N                               ((FLAG) == TIM_FLAG_CC1) || \
N                               ((FLAG) == TIM_FLAG_CC2) || \
N                               ((FLAG) == TIM_FLAG_CC3) || \
N                               ((FLAG) == TIM_FLAG_CC4) || \
N                               ((FLAG) == TIM_FLAG_COM) || \
N                               ((FLAG) == TIM_FLAG_Trigger) || \
N                               ((FLAG) == TIM_FLAG_Break) || \
N                               ((FLAG) == TIM_FLAG_CC1OF) || \
N                               ((FLAG) == TIM_FLAG_CC2OF) || \
N                               ((FLAG) == TIM_FLAG_CC3OF) || \
N                               ((FLAG) == TIM_FLAG_CC4OF))
X#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) ||                                ((FLAG) == TIM_FLAG_CC1) ||                                ((FLAG) == TIM_FLAG_CC2) ||                                ((FLAG) == TIM_FLAG_CC3) ||                                ((FLAG) == TIM_FLAG_CC4) ||                                ((FLAG) == TIM_FLAG_COM) ||                                ((FLAG) == TIM_FLAG_Trigger) ||                                ((FLAG) == TIM_FLAG_Break) ||                                ((FLAG) == TIM_FLAG_CC1OF) ||                                ((FLAG) == TIM_FLAG_CC2OF) ||                                ((FLAG) == TIM_FLAG_CC3OF) ||                                ((FLAG) == TIM_FLAG_CC4OF))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Input_Capture_Filer_Value 
N  * @{
N  */
N
N#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_External_Trigger_Filter 
N  * @{
N  */
N
N#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
N/**
N  * @}
N  */ 
N
N/** @defgroup TIM_Legacy 
N  * @{
N  */
N
N#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
N#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
N#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
N#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
N#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
N#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
N#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
N#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
N#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
N#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
N#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
N#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
N#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
N#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
N#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
N#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
N#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
N#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N
N/* TimeBase management ********************************************************/
Nvoid TIM_DeInit(TIM_TypeDef* TIMx);
Nvoid TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
Nvoid TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
Nvoid TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
Nvoid TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
Nvoid TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
Nvoid TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
Nuint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
Nuint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
Nvoid TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
Nvoid TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
Nvoid TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
Nvoid TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
Nvoid TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
Nvoid TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
N
N/* Output Compare management **************************************************/
Nvoid TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
Nvoid TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
Nvoid TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
Nvoid TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
Nvoid TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
Nvoid TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
Nvoid TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
Nvoid TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
Nvoid TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
Nvoid TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
Nvoid TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
Nvoid TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
Nvoid TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
Nvoid TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
Nvoid TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
Nvoid TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
Nvoid TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
Nvoid TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
Nvoid TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
Nvoid TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
Nvoid TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
Nvoid TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
Nvoid TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
Nvoid TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
Nvoid TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
Nvoid TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
Nvoid TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
Nvoid TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
Nvoid TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
Nvoid TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
Nvoid TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
Nvoid TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
Nvoid TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
Nvoid TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
Nvoid TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
N
N/* Input Capture management ***************************************************/
Nvoid TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
Nvoid TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
Nvoid TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
Nuint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
Nuint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
Nuint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
Nuint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
Nvoid TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
Nvoid TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
Nvoid TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
Nvoid TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
N
N/* Advanced-control timers (TIM1 and TIM8) specific features ******************/
Nvoid TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
Nvoid TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
Nvoid TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
Nvoid TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
Nvoid TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
N
N/* Interrupts, DMA and flags management ***************************************/
Nvoid TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
Nvoid TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
NFlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
Nvoid TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
NITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
Nvoid TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
Nvoid TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
Nvoid TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
Nvoid TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
N
N/* Clocks management **********************************************************/
Nvoid TIM_InternalClockConfig(TIM_TypeDef* TIMx);
Nvoid TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
Nvoid TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
N                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
Nvoid TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
N                             uint16_t ExtTRGFilter);
Nvoid TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
N                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
N
N/* Synchronization management *************************************************/
Nvoid TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
Nvoid TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
Nvoid TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
Nvoid TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
Nvoid TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
N                   uint16_t ExtTRGFilter);
N
N/* Specific interface management **********************************************/   
Nvoid TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
N                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
Nvoid TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
N
N/* Specific remapping management **********************************************/
Nvoid TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_TIM_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 50 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_usart.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_usart.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_usart.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the USART 
N  *          firmware library.    
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************  
N  */ 
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_USART_H
N#define __STM32F4xx_USART_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup USART
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/ 
N
N/** 
N  * @brief  USART Init Structure definition  
N  */ 
N  
Ntypedef struct
N{
N  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
N                                           The baud rate is computed using the following formula:
N                                            - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
N                                            - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 
N                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
N
N  uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
N                                           This parameter can be a value of @ref USART_Word_Length */
N
N  uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
N                                           This parameter can be a value of @ref USART_Stop_Bits */
N
N  uint16_t USART_Parity;              /*!< Specifies the parity mode.
N                                           This parameter can be a value of @ref USART_Parity
N                                           @note When parity is enabled, the computed parity is inserted
N                                                 at the MSB position of the transmitted data (9th bit when
N                                                 the word length is set to 9 data bits; 8th bit when the
N                                                 word length is set to 8 data bits). */
N 
N  uint16_t USART_Mode;                /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
N                                           This parameter can be a value of @ref USART_Mode */
N
N  uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
N                                           or disabled.
N                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */
N} USART_InitTypeDef;
N
N/** 
N  * @brief  USART Clock Init Structure definition  
N  */ 
N  
Ntypedef struct
N{
N
N  uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.
N                               This parameter can be a value of @ref USART_Clock */
N
N  uint16_t USART_CPOL;    /*!< Specifies the steady state of the serial clock.
N                               This parameter can be a value of @ref USART_Clock_Polarity */
N
N  uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.
N                               This parameter can be a value of @ref USART_Clock_Phase */
N
N  uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
N                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.
N                               This parameter can be a value of @ref USART_Last_Bit */
N} USART_ClockInitTypeDef;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup USART_Exported_Constants
N  * @{
N  */ 
N  
N#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
N                                     ((PERIPH) == USART2) || \
N                                     ((PERIPH) == USART3) || \
N                                     ((PERIPH) == UART4)  || \
N                                     ((PERIPH) == UART5)  || \
N                                     ((PERIPH) == USART6) || \
N                                     ((PERIPH) == UART7)  || \
N                                     ((PERIPH) == UART8))
X#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) ||                                      ((PERIPH) == USART2) ||                                      ((PERIPH) == USART3) ||                                      ((PERIPH) == UART4)  ||                                      ((PERIPH) == UART5)  ||                                      ((PERIPH) == USART6) ||                                      ((PERIPH) == UART7)  ||                                      ((PERIPH) == UART8))
N
N#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
N                                      ((PERIPH) == USART2) || \
N                                      ((PERIPH) == USART3) || \
N                                      ((PERIPH) == USART6))
X#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) ||                                       ((PERIPH) == USART2) ||                                       ((PERIPH) == USART3) ||                                       ((PERIPH) == USART6))
N
N/** @defgroup USART_Word_Length 
N  * @{
N  */ 
N  
N#define USART_WordLength_8b                  ((uint16_t)0x0000)
N#define USART_WordLength_9b                  ((uint16_t)0x1000)
N                                    
N#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
N                                      ((LENGTH) == USART_WordLength_9b))
X#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) ||                                       ((LENGTH) == USART_WordLength_9b))
N/**
N  * @}
N  */ 
N
N/** @defgroup USART_Stop_Bits 
N  * @{
N  */ 
N  
N#define USART_StopBits_1                     ((uint16_t)0x0000)
N#define USART_StopBits_0_5                   ((uint16_t)0x1000)
N#define USART_StopBits_2                     ((uint16_t)0x2000)
N#define USART_StopBits_1_5                   ((uint16_t)0x3000)
N#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
N                                     ((STOPBITS) == USART_StopBits_0_5) || \
N                                     ((STOPBITS) == USART_StopBits_2) || \
N                                     ((STOPBITS) == USART_StopBits_1_5))
X#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) ||                                      ((STOPBITS) == USART_StopBits_0_5) ||                                      ((STOPBITS) == USART_StopBits_2) ||                                      ((STOPBITS) == USART_StopBits_1_5))
N/**
N  * @}
N  */ 
N
N/** @defgroup USART_Parity 
N  * @{
N  */ 
N  
N#define USART_Parity_No                      ((uint16_t)0x0000)
N#define USART_Parity_Even                    ((uint16_t)0x0400)
N#define USART_Parity_Odd                     ((uint16_t)0x0600) 
N#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
N                                 ((PARITY) == USART_Parity_Even) || \
N                                 ((PARITY) == USART_Parity_Odd))
X#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) ||                                  ((PARITY) == USART_Parity_Even) ||                                  ((PARITY) == USART_Parity_Odd))
N/**
N  * @}
N  */ 
N
N/** @defgroup USART_Mode 
N  * @{
N  */ 
N  
N#define USART_Mode_Rx                        ((uint16_t)0x0004)
N#define USART_Mode_Tx                        ((uint16_t)0x0008)
N#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
N/**
N  * @}
N  */ 
N
N/** @defgroup USART_Hardware_Flow_Control 
N  * @{
N  */ 
N#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
N#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
N#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
N#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
N#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
N                              (((CONTROL) == USART_HardwareFlowControl_None) || \
N                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
N                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
N                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
X#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)                              (((CONTROL) == USART_HardwareFlowControl_None) ||                                ((CONTROL) == USART_HardwareFlowControl_RTS) ||                                ((CONTROL) == USART_HardwareFlowControl_CTS) ||                                ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
N/**
N  * @}
N  */ 
N
N/** @defgroup USART_Clock 
N  * @{
N  */ 
N#define USART_Clock_Disable                  ((uint16_t)0x0000)
N#define USART_Clock_Enable                   ((uint16_t)0x0800)
N#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
N                               ((CLOCK) == USART_Clock_Enable))
X#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) ||                                ((CLOCK) == USART_Clock_Enable))
N/**
N  * @}
N  */ 
N
N/** @defgroup USART_Clock_Polarity 
N  * @{
N  */
N  
N#define USART_CPOL_Low                       ((uint16_t)0x0000)
N#define USART_CPOL_High                      ((uint16_t)0x0400)
N#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup USART_Clock_Phase
N  * @{
N  */
N
N#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
N#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
N#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
N
N/**
N  * @}
N  */
N
N/** @defgroup USART_Last_Bit
N  * @{
N  */
N
N#define USART_LastBit_Disable                ((uint16_t)0x0000)
N#define USART_LastBit_Enable                 ((uint16_t)0x0100)
N#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
N                                   ((LASTBIT) == USART_LastBit_Enable))
X#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) ||                                    ((LASTBIT) == USART_LastBit_Enable))
N/**
N  * @}
N  */ 
N
N/** @defgroup USART_Interrupt_definition 
N  * @{
N  */
N  
N#define USART_IT_PE                          ((uint16_t)0x0028)
N#define USART_IT_TXE                         ((uint16_t)0x0727)
N#define USART_IT_TC                          ((uint16_t)0x0626)
N#define USART_IT_RXNE                        ((uint16_t)0x0525)
N#define USART_IT_ORE_RX                      ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
N#define USART_IT_IDLE                        ((uint16_t)0x0424)
N#define USART_IT_LBD                         ((uint16_t)0x0846)
N#define USART_IT_CTS                         ((uint16_t)0x096A)
N#define USART_IT_ERR                         ((uint16_t)0x0060)
N#define USART_IT_ORE_ER                      ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
N#define USART_IT_NE                          ((uint16_t)0x0260)
N#define USART_IT_FE                          ((uint16_t)0x0160)
N
N/** @defgroup USART_Legacy 
N  * @{
N  */
N#define USART_IT_ORE                          USART_IT_ORE_ER               
N/**
N  * @}
N  */
N
N#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
N                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
N                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
N                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
X#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) ||                                 ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) ||                                 ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) ||                                 ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
N#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
N                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
N                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
N                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
N                             ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
N                             ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
X#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) ||                              ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) ||                              ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) ||                              ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) ||                              ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) ||                              ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
N#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
N                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
X#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) ||                                ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
N/**
N  * @}
N  */
N
N/** @defgroup USART_DMA_Requests 
N  * @{
N  */
N
N#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
N#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
N#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup USART_WakeUp_methods
N  * @{
N  */
N
N#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
N#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
N#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
N                                 ((WAKEUP) == USART_WakeUp_AddressMark))
X#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) ||                                  ((WAKEUP) == USART_WakeUp_AddressMark))
N/**
N  * @}
N  */
N
N/** @defgroup USART_LIN_Break_Detection_Length 
N  * @{
N  */
N  
N#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
N#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
N#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
N                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
N                                ((LENGTH) == USART_LINBreakDetectLength_11b))
X#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH)                                (((LENGTH) == USART_LINBreakDetectLength_10b) ||                                 ((LENGTH) == USART_LINBreakDetectLength_11b))
N/**
N  * @}
N  */
N
N/** @defgroup USART_IrDA_Low_Power 
N  * @{
N  */
N
N#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
N#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
N#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
N                                  ((MODE) == USART_IrDAMode_Normal))
X#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) ||                                   ((MODE) == USART_IrDAMode_Normal))
N/**
N  * @}
N  */ 
N
N/** @defgroup USART_Flags 
N  * @{
N  */
N
N#define USART_FLAG_CTS                       ((uint16_t)0x0200)
N#define USART_FLAG_LBD                       ((uint16_t)0x0100)
N#define USART_FLAG_TXE                       ((uint16_t)0x0080)
N#define USART_FLAG_TC                        ((uint16_t)0x0040)
N#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
N#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
N#define USART_FLAG_ORE                       ((uint16_t)0x0008)
N#define USART_FLAG_NE                        ((uint16_t)0x0004)
N#define USART_FLAG_FE                        ((uint16_t)0x0002)
N#define USART_FLAG_PE                        ((uint16_t)0x0001)
N#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
N                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
N                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
N                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
N                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
X#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) ||                              ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) ||                              ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) ||                              ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) ||                              ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
N                              
N#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
N
N#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))
N#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
N#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/  
N
N/*  Function used to set the USART configuration to the default reset state ***/ 
Nvoid USART_DeInit(USART_TypeDef* USARTx);
N
N/* Initialization and Configuration functions *********************************/
Nvoid USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
Nvoid USART_StructInit(USART_InitTypeDef* USART_InitStruct);
Nvoid USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
Nvoid USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
Nvoid USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
Nvoid USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
Nvoid USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
Nvoid USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
N
N/* Data transfers functions ***************************************************/ 
Nvoid USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
Nuint16_t USART_ReceiveData(USART_TypeDef* USARTx);
N
N/* Multi-Processor Communication functions ************************************/
Nvoid USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
Nvoid USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
Nvoid USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
N
N/* LIN mode functions *********************************************************/
Nvoid USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
Nvoid USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
Nvoid USART_SendBreak(USART_TypeDef* USARTx);
N
N/* Half-duplex mode function **************************************************/
Nvoid USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
N
N/* Smartcard mode functions ***************************************************/
Nvoid USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
Nvoid USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
Nvoid USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
N
N/* IrDA mode functions ********************************************************/
Nvoid USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
Nvoid USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
N
N/* DMA transfers management functions *****************************************/
Nvoid USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
N
N/* Interrupts and flags management functions **********************************/
Nvoid USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
NFlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
Nvoid USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
NITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
Nvoid USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __STM32F4xx_USART_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 51 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_wwdg.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_wwdg.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_wwdg.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the WWDG firmware
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_WWDG_H
N#define __STM32F4xx_WWDG_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup WWDG
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup WWDG_Exported_Constants
N  * @{
N  */ 
N  
N/** @defgroup WWDG_Prescaler 
N  * @{
N  */
N  
N#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
N#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
N#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
N#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
N#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
N                                      ((PRESCALER) == WWDG_Prescaler_2) || \
N                                      ((PRESCALER) == WWDG_Prescaler_4) || \
N                                      ((PRESCALER) == WWDG_Prescaler_8))
X#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) ||                                       ((PRESCALER) == WWDG_Prescaler_2) ||                                       ((PRESCALER) == WWDG_Prescaler_4) ||                                       ((PRESCALER) == WWDG_Prescaler_8))
N#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
N#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/
N  
N/*  Function used to set the WWDG configuration to the default reset state ****/  
Nvoid WWDG_DeInit(void);
N
N/* Prescaler, Refresh window and Counter configuration functions **************/
Nvoid WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
Nvoid WWDG_SetWindowValue(uint8_t WindowValue);
Nvoid WWDG_EnableIT(void);
Nvoid WWDG_SetCounter(uint8_t Counter);
N
N/* WWDG activation function ***************************************************/
Nvoid WWDG_Enable(uint8_t Counter);
N
N/* Interrupts and flags management functions **********************************/
NFlagStatus WWDG_GetFlagStatus(void);
Nvoid WWDG_ClearFlag(void);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __STM32F4xx_WWDG_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 52 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\misc.h" 1
N/**
N  ******************************************************************************
N  * @file    misc.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the miscellaneous
N  *          firmware library functions (add-on to CMSIS functions).
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __MISC_H
N#define __MISC_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup MISC
N  * @{
N  */
N
N/* Exported types ------------------------------------------------------------*/
N
N/** 
N  * @brief  NVIC Init Structure definition  
N  */
N
Ntypedef struct
N{
N  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
N                                                   This parameter can be an enumerator of @ref IRQn_Type 
N                                                   enumeration (For the complete STM32 Devices IRQ Channels
N                                                   list, please refer to stm32f4xx.h file) */
N
N  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
N                                                   specified in NVIC_IRQChannel. This parameter can be a value
N                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
N                                                   A lower priority value indicates a higher priority */
N
N  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
N                                                   in NVIC_IRQChannel. This parameter can be a value
N                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
N                                                   A lower priority value indicates a higher priority */
N
N  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
N                                                   will be enabled or disabled. 
N                                                   This parameter can be set either to ENABLE or DISABLE */   
N} NVIC_InitTypeDef;
N 
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup MISC_Exported_Constants
N  * @{
N  */
N
N/** @defgroup MISC_Vector_Table_Base 
N  * @{
N  */
N
N#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
N#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
N#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
N                                  ((VECTTAB) == NVIC_VectTab_FLASH))
X#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) ||                                   ((VECTTAB) == NVIC_VectTab_FLASH))
N/**
N  * @}
N  */
N
N/** @defgroup MISC_System_Low_Power 
N  * @{
N  */
N
N#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
N#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
N#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
N#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
N                        ((LP) == NVIC_LP_SLEEPDEEP) || \
N                        ((LP) == NVIC_LP_SLEEPONEXIT))
X#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) ||                         ((LP) == NVIC_LP_SLEEPDEEP) ||                         ((LP) == NVIC_LP_SLEEPONEXIT))
N/**
N  * @}
N  */
N
N/** @defgroup MISC_Preemption_Priority_Group 
N  * @{
N  */
N
N#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
N                                                            4 bits for subpriority */
N#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
N                                                            3 bits for subpriority */
N#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
N                                                            2 bits for subpriority */
N#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
N                                                            1 bits for subpriority */
N#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
N                                                            0 bits for subpriority */
N
N#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
N                                       ((GROUP) == NVIC_PriorityGroup_1) || \
N                                       ((GROUP) == NVIC_PriorityGroup_2) || \
N                                       ((GROUP) == NVIC_PriorityGroup_3) || \
N                                       ((GROUP) == NVIC_PriorityGroup_4))
X#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) ||                                        ((GROUP) == NVIC_PriorityGroup_1) ||                                        ((GROUP) == NVIC_PriorityGroup_2) ||                                        ((GROUP) == NVIC_PriorityGroup_3) ||                                        ((GROUP) == NVIC_PriorityGroup_4))
N
N#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
N
N#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
N
N#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
N
N/**
N  * @}
N  */
N
N/** @defgroup MISC_SysTick_clock_source 
N  * @{
N  */
N
N#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
N#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
N#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
N                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
X#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) ||                                        ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/
N
Nvoid NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
Nvoid NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
Nvoid NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
Nvoid NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
Nvoid SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __MISC_H */
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 53 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N
N#if defined (STM32F429_439xx)
X#if 0L
S#include "stm32f4xx_cryp.h"
S#include "stm32f4xx_hash.h"
S#include "stm32f4xx_rng.h"
S#include "stm32f4xx_can.h"
S#include "stm32f4xx_dac.h"
S#include "stm32f4xx_dcmi.h"
S#include "stm32f4xx_dma2d.h"
S#include "stm32f4xx_fmc.h"
S#include "stm32f4xx_ltdc.h"
S#include "stm32f4xx_sai.h"
N#endif /* STM32F429_439xx */
N
N#if defined (STM32F427_437xx)
X#if 0L
S#include "stm32f4xx_cryp.h"
S#include "stm32f4xx_hash.h"
S#include "stm32f4xx_rng.h"
S#include "stm32f4xx_can.h"
S#include "stm32f4xx_dac.h"
S#include "stm32f4xx_dcmi.h"
S#include "stm32f4xx_dma2d.h"
S#include "stm32f4xx_fmc.h"
S#include "stm32f4xx_sai.h"
N#endif /* STM32F427_437xx */
N
N#if defined (STM32F40_41xxx)
X#if 1L
N#include "stm32f4xx_cryp.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_cryp.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_cryp.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the Cryptographic
N  *          processor(CRYP) firmware library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_CRYP_H
N#define __STM32F4xx_CRYP_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup CRYP
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N
N/** 
N  * @brief   CRYP Init structure definition  
N  */ 
Ntypedef struct
N{
N  uint32_t CRYP_AlgoDir;   /*!< Encrypt or Decrypt. This parameter can be a 
N                                value of @ref CRYP_Algorithm_Direction */
N  uint32_t CRYP_AlgoMode;  /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, 
N                                AES-CBC, AES-CTR, AES-Key, AES-GCM and AES-CCM.
N                                This parameter can be a value of @ref CRYP_Algorithm_Mode */
N  uint32_t CRYP_DataType;  /*!< 32-bit data, 16-bit data, bit data or bit string.
N                                This parameter can be a value of @ref CRYP_Data_Type */ 
N  uint32_t CRYP_KeySize;   /*!< Used only in AES mode only : 128, 192 or 256 bit 
N                                key length. This parameter can be a value of 
N                                @ref CRYP_Key_Size_for_AES_only */
N}CRYP_InitTypeDef;
N
N/** 
N  * @brief   CRYP Key(s) structure definition  
N  */ 
Ntypedef struct
N{
N  uint32_t CRYP_Key0Left;  /*!< Key 0 Left  */
N  uint32_t CRYP_Key0Right; /*!< Key 0 Right */
N  uint32_t CRYP_Key1Left;  /*!< Key 1 left  */
N  uint32_t CRYP_Key1Right; /*!< Key 1 Right */
N  uint32_t CRYP_Key2Left;  /*!< Key 2 left  */
N  uint32_t CRYP_Key2Right; /*!< Key 2 Right */
N  uint32_t CRYP_Key3Left;  /*!< Key 3 left  */
N  uint32_t CRYP_Key3Right; /*!< Key 3 Right */
N}CRYP_KeyInitTypeDef;
N/** 
N  * @brief   CRYP Initialization Vectors (IV) structure definition  
N  */ 
Ntypedef struct
N{
N  uint32_t CRYP_IV0Left;  /*!< Init Vector 0 Left  */
N  uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */
N  uint32_t CRYP_IV1Left;  /*!< Init Vector 1 left  */
N  uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */
N}CRYP_IVInitTypeDef;
N
N/** 
N  * @brief  CRYP context swapping structure definition  
N  */ 
Ntypedef struct
N{
N  /*!< Current Configuration */
N  uint32_t CR_CurrentConfig;
N  /*!< IV */
N  uint32_t CRYP_IV0LR;
N  uint32_t CRYP_IV0RR;
N  uint32_t CRYP_IV1LR;
N  uint32_t CRYP_IV1RR;
N  /*!< KEY */
N  uint32_t CRYP_K0LR;
N  uint32_t CRYP_K0RR;
N  uint32_t CRYP_K1LR;
N  uint32_t CRYP_K1RR;
N  uint32_t CRYP_K2LR;
N  uint32_t CRYP_K2RR;
N  uint32_t CRYP_K3LR;
N  uint32_t CRYP_K3RR;
N  uint32_t CRYP_CSGCMCCMR[8];
N  uint32_t CRYP_CSGCMR[8];
N}CRYP_Context;
N
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup CRYP_Exported_Constants
N  * @{
N  */
N
N/** @defgroup CRYP_Algorithm_Direction 
N  * @{
N  */
N#define CRYP_AlgoDir_Encrypt      ((uint16_t)0x0000)
N#define CRYP_AlgoDir_Decrypt      ((uint16_t)0x0004)
N#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \
N                                  ((ALGODIR) == CRYP_AlgoDir_Decrypt))
X#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) ||                                   ((ALGODIR) == CRYP_AlgoDir_Decrypt))
N
N/**
N  * @}
N  */ 
N 
N/** @defgroup CRYP_Algorithm_Mode 
N  * @{
N  */
N
N/*!< TDES Modes */
N#define CRYP_AlgoMode_TDES_ECB    ((uint32_t)0x00000000)
N#define CRYP_AlgoMode_TDES_CBC    ((uint32_t)0x00000008)
N
N/*!< DES Modes */
N#define CRYP_AlgoMode_DES_ECB     ((uint32_t)0x00000010)
N#define CRYP_AlgoMode_DES_CBC     ((uint32_t)0x00000018)
N
N/*!< AES Modes */
N#define CRYP_AlgoMode_AES_ECB     ((uint32_t)0x00000020)
N#define CRYP_AlgoMode_AES_CBC     ((uint32_t)0x00000028)
N#define CRYP_AlgoMode_AES_CTR     ((uint32_t)0x00000030)
N#define CRYP_AlgoMode_AES_Key     ((uint32_t)0x00000038)
N#define CRYP_AlgoMode_AES_GCM     ((uint32_t)0x00080000)
N#define CRYP_AlgoMode_AES_CCM     ((uint32_t)0x00080008)
N
N#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \
N                                   ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \
N                                   ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \
N                                   ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \
N                                   ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \
N                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \
N                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \
N                                   ((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \
N                                   ((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \
N                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CCM))
X#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) ||                                    ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)||                                    ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) ||                                    ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) ||                                    ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) ||                                    ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) ||                                    ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) ||                                    ((ALGOMODE) == CRYP_AlgoMode_AES_Key) ||                                    ((ALGOMODE) == CRYP_AlgoMode_AES_GCM) ||                                    ((ALGOMODE) == CRYP_AlgoMode_AES_CCM))
N/**
N  * @}
N  */ 
N
N/** @defgroup CRYP_Phase 
N  * @{
N  */
N
N/*!< The phases are valid only for AES-GCM and AES-CCM modes */
N#define CRYP_Phase_Init           ((uint32_t)0x00000000)
N#define CRYP_Phase_Header         CRYP_CR_GCM_CCMPH_0
N#define CRYP_Phase_Payload        CRYP_CR_GCM_CCMPH_1
N#define CRYP_Phase_Final          CRYP_CR_GCM_CCMPH
N
N#define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init)    || \
N                              ((PHASE) == CRYP_Phase_Header)  || \
N                              ((PHASE) == CRYP_Phase_Payload) || \
N                              ((PHASE) == CRYP_Phase_Final))
X#define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init)    ||                               ((PHASE) == CRYP_Phase_Header)  ||                               ((PHASE) == CRYP_Phase_Payload) ||                               ((PHASE) == CRYP_Phase_Final))
N
N/**
N  * @}
N  */ 
N
N/** @defgroup CRYP_Data_Type 
N  * @{
N  */
N#define CRYP_DataType_32b         ((uint16_t)0x0000)
N#define CRYP_DataType_16b         ((uint16_t)0x0040)
N#define CRYP_DataType_8b          ((uint16_t)0x0080)
N#define CRYP_DataType_1b          ((uint16_t)0x00C0)
N#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \
N                                    ((DATATYPE) == CRYP_DataType_16b)|| \
N                                    ((DATATYPE) == CRYP_DataType_8b)|| \
N                                    ((DATATYPE) == CRYP_DataType_1b))  
X#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) ||                                     ((DATATYPE) == CRYP_DataType_16b)||                                     ((DATATYPE) == CRYP_DataType_8b)||                                     ((DATATYPE) == CRYP_DataType_1b))  
N/**
N  * @}
N  */
N                                     
N/** @defgroup CRYP_Key_Size_for_AES_only 
N  * @{
N  */
N#define CRYP_KeySize_128b         ((uint16_t)0x0000)
N#define CRYP_KeySize_192b         ((uint16_t)0x0100)
N#define CRYP_KeySize_256b         ((uint16_t)0x0200)
N#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \
N                                  ((KEYSIZE) == CRYP_KeySize_192b)|| \
N                                  ((KEYSIZE) == CRYP_KeySize_256b))
X#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)||                                   ((KEYSIZE) == CRYP_KeySize_192b)||                                   ((KEYSIZE) == CRYP_KeySize_256b))
N/**
N  * @}
N  */
N
N/** @defgroup CRYP_flags_definition 
N  * @{
N  */
N#define CRYP_FLAG_BUSY            ((uint8_t)0x10)  /*!< The CRYP core is currently 
N                                                        processing a block of data 
N                                                        or a key preparation (for 
N                                                        AES decryption). */
N#define CRYP_FLAG_IFEM            ((uint8_t)0x01)  /*!< Input Fifo Empty */
N#define CRYP_FLAG_IFNF            ((uint8_t)0x02)  /*!< Input Fifo is Not Full */
N#define CRYP_FLAG_INRIS           ((uint8_t)0x22)  /*!< Raw interrupt pending */
N#define CRYP_FLAG_OFNE            ((uint8_t)0x04)  /*!< Input Fifo service raw 
N                                                        interrupt status */
N#define CRYP_FLAG_OFFU            ((uint8_t)0x08)  /*!< Output Fifo is Full */
N#define CRYP_FLAG_OUTRIS          ((uint8_t)0x21)  /*!< Output Fifo service raw 
N                                                        interrupt status */
N
N#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM)  || \
N                                ((FLAG) == CRYP_FLAG_IFNF)  || \
N                                ((FLAG) == CRYP_FLAG_OFNE)  || \
N                                ((FLAG) == CRYP_FLAG_OFFU)  || \
N                                ((FLAG) == CRYP_FLAG_BUSY)  || \
N                                ((FLAG) == CRYP_FLAG_OUTRIS)|| \
N                                ((FLAG) == CRYP_FLAG_INRIS))
X#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM)  ||                                 ((FLAG) == CRYP_FLAG_IFNF)  ||                                 ((FLAG) == CRYP_FLAG_OFNE)  ||                                 ((FLAG) == CRYP_FLAG_OFFU)  ||                                 ((FLAG) == CRYP_FLAG_BUSY)  ||                                 ((FLAG) == CRYP_FLAG_OUTRIS)||                                 ((FLAG) == CRYP_FLAG_INRIS))
N/**
N  * @}
N  */
N
N/** @defgroup CRYP_interrupts_definition 
N  * @{
N  */
N#define CRYP_IT_INI               ((uint8_t)0x01) /*!< IN Fifo Interrupt */
N#define CRYP_IT_OUTI              ((uint8_t)0x02) /*!< OUT Fifo Interrupt */
N#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
N#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))
N
N/**
N  * @}
N  */
N
N/** @defgroup CRYP_Encryption_Decryption_modes_definition 
N  * @{
N  */
N#define MODE_ENCRYPT             ((uint8_t)0x01)
N#define MODE_DECRYPT             ((uint8_t)0x00)
N
N/**
N  * @}
N  */
N
N/** @defgroup CRYP_DMA_transfer_requests 
N  * @{
N  */
N#define CRYP_DMAReq_DataIN             ((uint8_t)0x01)
N#define CRYP_DMAReq_DataOUT            ((uint8_t)0x02)
N#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/
N
N/*  Function used to set the CRYP configuration to the default reset state ****/
Nvoid CRYP_DeInit(void);
N
N/* CRYP Initialization and Configuration functions ****************************/
Nvoid CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct);
Nvoid CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct);
Nvoid CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
Nvoid CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
Nvoid CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
Nvoid CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
Nvoid CRYP_Cmd(FunctionalState NewState);
Nvoid CRYP_PhaseConfig(uint32_t CRYP_Phase);
Nvoid CRYP_FIFOFlush(void);
N/* CRYP Data processing functions *********************************************/
Nvoid CRYP_DataIn(uint32_t Data);
Nuint32_t CRYP_DataOut(void);
N
N/* CRYP Context swapping functions ********************************************/
NErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
N                             CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
Nvoid CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);
N
N/* CRYP DMA interface function ************************************************/
Nvoid CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);
N
N/* Interrupts and flags management functions **********************************/
Nvoid CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);
NITStatus CRYP_GetITStatus(uint8_t CRYP_IT);
NFunctionalState CRYP_GetCmdStatus(void);
NFlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);
N
N/* High Level AES functions **************************************************/
NErrorStatus CRYP_AES_ECB(uint8_t Mode,
N                         uint8_t *Key, uint16_t Keysize,
N                         uint8_t *Input, uint32_t Ilength,
N                         uint8_t *Output);
N
NErrorStatus CRYP_AES_CBC(uint8_t Mode,
N                         uint8_t InitVectors[16],
N                         uint8_t *Key, uint16_t Keysize,
N                         uint8_t *Input, uint32_t Ilength,
N                         uint8_t *Output);
N
NErrorStatus CRYP_AES_CTR(uint8_t Mode,
N                         uint8_t InitVectors[16],
N                         uint8_t *Key, uint16_t Keysize,
N                         uint8_t *Input, uint32_t Ilength,
N                         uint8_t *Output);
N
NErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
N                         uint8_t *Key, uint16_t Keysize,
N                         uint8_t *Input, uint32_t ILength,
N                         uint8_t *Header, uint32_t HLength,
N                         uint8_t *Output, uint8_t *AuthTAG);
N
NErrorStatus CRYP_AES_CCM(uint8_t Mode, 
N                         uint8_t* Nonce, uint32_t NonceSize,
N                         uint8_t* Key, uint16_t Keysize,
N                         uint8_t* Input, uint32_t ILength,
N                         uint8_t* Header, uint32_t HLength, uint8_t *HBuffer,
N                         uint8_t* Output,
N                         uint8_t* AuthTAG, uint32_t TAGSize);
N
N/* High Level TDES functions **************************************************/
NErrorStatus CRYP_TDES_ECB(uint8_t Mode,
N                           uint8_t Key[24], 
N                           uint8_t *Input, uint32_t Ilength,
N                           uint8_t *Output);
N
NErrorStatus CRYP_TDES_CBC(uint8_t Mode,
N                          uint8_t Key[24],
N                          uint8_t InitVectors[8],
N                          uint8_t *Input, uint32_t Ilength,
N                          uint8_t *Output);
N
N/* High Level DES functions **************************************************/
NErrorStatus CRYP_DES_ECB(uint8_t Mode,
N                         uint8_t Key[8],
N                         uint8_t *Input, uint32_t Ilength,
N                         uint8_t *Output);
N
NErrorStatus CRYP_DES_CBC(uint8_t Mode,
N                         uint8_t Key[8],
N                         uint8_t InitVectors[8],
N                         uint8_t *Input,uint32_t Ilength,
N                         uint8_t *Output);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_CRYP_H */
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 81 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_hash.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_hash.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_hash.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the HASH 
N  *          firmware library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_HASH_H
N#define __STM32F4xx_HASH_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup HASH
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N
N/** 
N  * @brief   HASH Init structure definition
N  */ 
Ntypedef struct
N{
N  uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter
N                                    can be a value of @ref HASH_Algo_Selection */
N  uint32_t HASH_AlgoMode;      /*!< HASH or HMAC. This parameter can be a value 
N                                    of @ref HASH_processor_Algorithm_Mode */
N  uint32_t HASH_DataType;      /*!< 32-bit data, 16-bit data, 8-bit data or 
N                                    bit string. This parameter can be a value of
N                                    @ref HASH_Data_Type */
N  uint32_t HASH_HMACKeyType;   /*!< HMAC Short key or HMAC Long Key. This parameter
N                                    can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */
N}HASH_InitTypeDef;
N
N/** 
N  * @brief  HASH message digest result structure definition  
N  */ 
Ntypedef struct
N{
N  uint32_t Data[8];      /*!< Message digest result : 8x 32bit wors for SHA-256,
N                                                      7x 32bit wors for SHA-224,
N                                                      5x 32bit words for SHA-1 or
N                                                      4x 32bit words for MD5  */
N} HASH_MsgDigest; 
N
N/** 
N  * @brief  HASH context swapping structure definition  
N  */ 
Ntypedef struct
N{
N  uint32_t HASH_IMR; 
N  uint32_t HASH_STR;      
N  uint32_t HASH_CR;     
N  uint32_t HASH_CSR[54];       
N}HASH_Context;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup HASH_Exported_Constants
N  * @{
N  */ 
N
N/** @defgroup HASH_Algo_Selection 
N  * @{
N  */ 
N#define HASH_AlgoSelection_SHA1      ((uint32_t)0x0000) /*!< HASH function is SHA1   */
N#define HASH_AlgoSelection_SHA224    HASH_CR_ALGO_1     /*!< HASH function is SHA224 */
N#define HASH_AlgoSelection_SHA256    HASH_CR_ALGO       /*!< HASH function is SHA256 */
N#define HASH_AlgoSelection_MD5       HASH_CR_ALGO_0     /*!< HASH function is MD5    */
N
N#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
N                                              ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
N                                              ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
N                                              ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
X#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) ||                                               ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) ||                                               ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) ||                                               ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
N/**
N  * @}
N  */
N
N/** @defgroup HASH_processor_Algorithm_Mode 
N  * @{
N  */ 
N#define HASH_AlgoMode_HASH         ((uint32_t)0x00000000) /*!< Algorithm is HASH */ 
N#define HASH_AlgoMode_HMAC         HASH_CR_MODE           /*!< Algorithm is HMAC */
N
N#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
N                                    ((ALGOMODE) == HASH_AlgoMode_HMAC))
X#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) ||                                     ((ALGOMODE) == HASH_AlgoMode_HMAC))
N/**
N  * @}
N  */
N
N/** @defgroup HASH_Data_Type  
N  * @{
N  */  
N#define HASH_DataType_32b          ((uint32_t)0x0000) /*!< 32-bit data. No swapping                     */
N#define HASH_DataType_16b          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
N#define HASH_DataType_8b           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
N#define HASH_DataType_1b           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
N
N#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \
N                                    ((DATATYPE) == HASH_DataType_16b)|| \
N                                    ((DATATYPE) == HASH_DataType_8b) || \
N                                    ((DATATYPE) == HASH_DataType_1b))
X#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)||                                     ((DATATYPE) == HASH_DataType_16b)||                                     ((DATATYPE) == HASH_DataType_8b) ||                                     ((DATATYPE) == HASH_DataType_1b))
N/**
N  * @}
N  */
N
N/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode  
N  * @{
N  */ 
N#define HASH_HMACKeyType_ShortKey      ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
N#define HASH_HMACKeyType_LongKey       HASH_CR_LKEY           /*!< HMAC Key is > 64 bytes  */
N
N#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
N                                       ((KEYTYPE) == HASH_HMACKeyType_LongKey))
X#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) ||                                        ((KEYTYPE) == HASH_HMACKeyType_LongKey))
N/**
N  * @}
N  */
N
N/** @defgroup Number_of_valid_bits_in_last_word_of_the_message   
N  * @{
N  */  
N#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)
N
N/**
N  * @}
N  */
N
N/** @defgroup HASH_interrupts_definition   
N  * @{
N  */  
N#define HASH_IT_DINI               HASH_IMR_DINIM  /*!< A new block can be entered into the input buffer (DIN) */
N#define HASH_IT_DCI                HASH_IMR_DCIM   /*!< Digest calculation complete                            */
N
N#define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000))
N#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
N				   
N/**
N  * @}
N  */
N
N/** @defgroup HASH_flags_definition   
N  * @{
N  */  
N#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
N#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                                         */
N#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing                          */
N#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy : processing a block of data                                  */
N#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : The input buffer contains at least one word of data                 */
N
N#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \
N                                ((FLAG) == HASH_FLAG_DCIS)  || \
N                                ((FLAG) == HASH_FLAG_DMAS)  || \
N                                ((FLAG) == HASH_FLAG_BUSY)  || \
N                                ((FLAG) == HASH_FLAG_DINNE)) 
X#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) ||                                 ((FLAG) == HASH_FLAG_DCIS)  ||                                 ((FLAG) == HASH_FLAG_DMAS)  ||                                 ((FLAG) == HASH_FLAG_BUSY)  ||                                 ((FLAG) == HASH_FLAG_DINNE)) 
N
N#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \
N                                 ((FLAG) == HASH_FLAG_DCIS))                                 
X#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) ||                                  ((FLAG) == HASH_FLAG_DCIS))                                 
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N  
N/*  Function used to set the HASH configuration to the default reset state ****/
Nvoid HASH_DeInit(void);
N
N/* HASH Configuration function ************************************************/
Nvoid HASH_Init(HASH_InitTypeDef* HASH_InitStruct);
Nvoid HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct);
Nvoid HASH_Reset(void);
N
N/* HASH Message Digest generation functions ***********************************/
Nvoid HASH_DataIn(uint32_t Data);
Nuint8_t HASH_GetInFIFOWordsNbr(void);
Nvoid HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);
Nvoid HASH_StartDigest(void);
Nvoid HASH_AutoStartDigest(FunctionalState NewState);
Nvoid HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);
N
N/* HASH Context swapping functions ********************************************/
Nvoid HASH_SaveContext(HASH_Context* HASH_ContextSave);
Nvoid HASH_RestoreContext(HASH_Context* HASH_ContextRestore);
N
N/* HASH DMA interface function ************************************************/
Nvoid HASH_DMACmd(FunctionalState NewState);
N
N/* HASH Interrupts and flags management functions *****************************/
Nvoid HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState);
NFlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG);
Nvoid HASH_ClearFlag(uint32_t HASH_FLAG);
NITStatus HASH_GetITStatus(uint32_t HASH_IT);
Nvoid HASH_ClearITPendingBit(uint32_t HASH_IT);
N
N/* High Level SHA1 functions **************************************************/
NErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);
NErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen,
N                      uint8_t *Input, uint32_t Ilen,
N                      uint8_t Output[20]);
N
N/* High Level MD5 functions ***************************************************/
NErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]);
NErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,
N                     uint8_t *Input, uint32_t Ilen,
N                     uint8_t Output[16]);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_HASH_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 82 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_rng.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_rng.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_rng.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the Random 
N  *          Number Generator(RNG) firmware library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_RNG_H
N#define __STM32F4xx_RNG_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup RNG
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N/* Exported constants --------------------------------------------------------*/ 
N
N/** @defgroup RNG_Exported_Constants
N  * @{
N  */
N  
N/** @defgroup RNG_flags_definition  
N  * @{
N  */ 
N#define RNG_FLAG_DRDY               ((uint8_t)0x0001) /*!< Data ready */
N#define RNG_FLAG_CECS               ((uint8_t)0x0002) /*!< Clock error current status */
N#define RNG_FLAG_SECS               ((uint8_t)0x0004) /*!< Seed error current status */
N
N#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \
N                                   ((RNG_FLAG) == RNG_FLAG_CECS) || \
N                                   ((RNG_FLAG) == RNG_FLAG_SECS))
X#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) ||                                    ((RNG_FLAG) == RNG_FLAG_CECS) ||                                    ((RNG_FLAG) == RNG_FLAG_SECS))
N#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \
N                                    ((RNG_FLAG) == RNG_FLAG_SECS))
X#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) ||                                     ((RNG_FLAG) == RNG_FLAG_SECS))
N/**
N  * @}
N  */ 
N
N/** @defgroup RNG_interrupts_definition   
N  * @{
N  */  
N#define RNG_IT_CEI                  ((uint8_t)0x20) /*!< Clock error interrupt */
N#define RNG_IT_SEI                  ((uint8_t)0x40) /*!< Seed error interrupt */
N
N#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))
N#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N
N/*  Function used to set the RNG configuration to the default reset state *****/ 
Nvoid RNG_DeInit(void);
N
N/* Configuration function *****************************************************/
Nvoid RNG_Cmd(FunctionalState NewState);
N
N/* Get 32 bit Random number function ******************************************/
Nuint32_t RNG_GetRandomNumber(void);
N
N/* Interrupts and flags management functions **********************************/
Nvoid RNG_ITConfig(FunctionalState NewState);
NFlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
Nvoid RNG_ClearFlag(uint8_t RNG_FLAG);
NITStatus RNG_GetITStatus(uint8_t RNG_IT);
Nvoid RNG_ClearITPendingBit(uint8_t RNG_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_RNG_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 83 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_can.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_can.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_can.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the CAN firmware 
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_CAN_H
N#define __STM32F4xx_CAN_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup CAN
N  * @{
N  */
N
N/* Exported types ------------------------------------------------------------*/
N
N#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
N                                   ((PERIPH) == CAN2))
X#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) ||                                    ((PERIPH) == CAN2))
N
N/** 
N  * @brief  CAN init structure definition
N  */
Ntypedef struct
N{
N  uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum. 
N                                 It ranges from 1 to 1024. */
N  
N  uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
N                                 This parameter can be a value of @ref CAN_operating_mode */
N
N  uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
N                                 the CAN hardware is allowed to lengthen or 
N                                 shorten a bit to perform resynchronization.
N                                 This parameter can be a value of @ref CAN_synchronisation_jump_width */
N
N  uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit 
N                                 Segment 1. This parameter can be a value of 
N                                 @ref CAN_time_quantum_in_bit_segment_1 */
N
N  uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit Segment 2.
N                                 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
N  
N  FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
N                                This parameter can be set either to ENABLE or DISABLE. */
N  
N  FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off management.
N                                  This parameter can be set either to ENABLE or DISABLE. */
N
N  FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode. 
N                                  This parameter can be set either to ENABLE or DISABLE. */
N
N  FunctionalState CAN_NART;  /*!< Enable or disable the non-automatic retransmission mode.
N                                  This parameter can be set either to ENABLE or DISABLE. */
N
N  FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
N                                  This parameter can be set either to ENABLE or DISABLE. */
N
N  FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
N                                  This parameter can be set either to ENABLE or DISABLE. */
N} CAN_InitTypeDef;
N
N/** 
N  * @brief  CAN filter init structure definition
N  */
Ntypedef struct
N{
N  uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
N                                              configuration, first one for a 16-bit configuration).
N                                              This parameter can be a value between 0x0000 and 0xFFFF */
N
N  uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
N                                              configuration, second one for a 16-bit configuration).
N                                              This parameter can be a value between 0x0000 and 0xFFFF */
N
N  uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
N                                              according to the mode (MSBs for a 32-bit configuration,
N                                              first one for a 16-bit configuration).
N                                              This parameter can be a value between 0x0000 and 0xFFFF */
N
N  uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
N                                              according to the mode (LSBs for a 32-bit configuration,
N                                              second one for a 16-bit configuration).
N                                              This parameter can be a value between 0x0000 and 0xFFFF */
N
N  uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
N                                              This parameter can be a value of @ref CAN_filter_FIFO */
N  
N  uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
N
N  uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
N                                              This parameter can be a value of @ref CAN_filter_mode */
N
N  uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
N                                              This parameter can be a value of @ref CAN_filter_scale */
N
N  FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
N                                              This parameter can be set either to ENABLE or DISABLE. */
N} CAN_FilterInitTypeDef;
N
N/** 
N  * @brief  CAN Tx message structure definition  
N  */
Ntypedef struct
N{
N  uint32_t StdId;  /*!< Specifies the standard identifier.
N                        This parameter can be a value between 0 to 0x7FF. */
N
N  uint32_t ExtId;  /*!< Specifies the extended identifier.
N                        This parameter can be a value between 0 to 0x1FFFFFFF. */
N
N  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
N                        will be transmitted. This parameter can be a value 
N                        of @ref CAN_identifier_type */
N
N  uint8_t RTR;     /*!< Specifies the type of frame for the message that will 
N                        be transmitted. This parameter can be a value of 
N                        @ref CAN_remote_transmission_request */
N
N  uint8_t DLC;     /*!< Specifies the length of the frame that will be 
N                        transmitted. This parameter can be a value between 
N                        0 to 8 */
N
N  uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 
N                        to 0xFF. */
N} CanTxMsg;
N
N/** 
N  * @brief  CAN Rx message structure definition  
N  */
Ntypedef struct
N{
N  uint32_t StdId;  /*!< Specifies the standard identifier.
N                        This parameter can be a value between 0 to 0x7FF. */
N
N  uint32_t ExtId;  /*!< Specifies the extended identifier.
N                        This parameter can be a value between 0 to 0x1FFFFFFF. */
N
N  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
N                        will be received. This parameter can be a value of 
N                        @ref CAN_identifier_type */
N
N  uint8_t RTR;     /*!< Specifies the type of frame for the received message.
N                        This parameter can be a value of 
N                        @ref CAN_remote_transmission_request */
N
N  uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
N                        This parameter can be a value between 0 to 8 */
N
N  uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 
N                        0xFF. */
N
N  uint8_t FMI;     /*!< Specifies the index of the filter the message stored in 
N                        the mailbox passes through. This parameter can be a 
N                        value between 0 to 0xFF */
N} CanRxMsg;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup CAN_Exported_Constants
N  * @{
N  */
N
N/** @defgroup CAN_InitStatus 
N  * @{
N  */
N
N#define CAN_InitStatus_Failed              ((uint8_t)0x00) /*!< CAN initialization failed */
N#define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
N
N
N/* Legacy defines */
N#define CANINITFAILED    CAN_InitStatus_Failed
N#define CANINITOK        CAN_InitStatus_Success
N/**
N  * @}
N  */
N
N/** @defgroup CAN_operating_mode 
N  * @{
N  */
N
N#define CAN_Mode_Normal             ((uint8_t)0x00)  /*!< normal mode */
N#define CAN_Mode_LoopBack           ((uint8_t)0x01)  /*!< loopback mode */
N#define CAN_Mode_Silent             ((uint8_t)0x02)  /*!< silent mode */
N#define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
N
N#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
N                           ((MODE) == CAN_Mode_LoopBack)|| \
N                           ((MODE) == CAN_Mode_Silent) || \
N                           ((MODE) == CAN_Mode_Silent_LoopBack))
X#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) ||                            ((MODE) == CAN_Mode_LoopBack)||                            ((MODE) == CAN_Mode_Silent) ||                            ((MODE) == CAN_Mode_Silent_LoopBack))
N/**
N  * @}
N  */
N
N
N /**
N  * @defgroup CAN_operating_mode 
N  * @{
N  */  
N#define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
N#define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
N#define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
N
N
N#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
N                                    ((MODE) == CAN_OperatingMode_Normal)|| \
N																		((MODE) == CAN_OperatingMode_Sleep))
X#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||                                    ((MODE) == CAN_OperatingMode_Normal)|| 																		((MODE) == CAN_OperatingMode_Sleep))
N/**
N  * @}
N  */
N  
N/**
N  * @defgroup CAN_operating_mode_status
N  * @{
N  */  
N
N#define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
N#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
N/**
N  * @}
N  */
N
N/** @defgroup CAN_synchronisation_jump_width 
N  * @{
N  */
N#define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
N#define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
N#define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
N#define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
N
N#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
N                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
X#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)||                          ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
N/**
N  * @}
N  */
N
N/** @defgroup CAN_time_quantum_in_bit_segment_1 
N  * @{
N  */
N#define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
N#define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
N#define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
N#define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
N#define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
N#define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
N#define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
N#define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
N#define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
N#define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
N#define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
N#define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
N#define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
N#define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
N#define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
N#define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
N
N#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
N/**
N  * @}
N  */
N
N/** @defgroup CAN_time_quantum_in_bit_segment_2 
N  * @{
N  */
N#define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
N#define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
N#define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
N#define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
N#define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
N#define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
N#define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
N#define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
N
N#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
N/**
N  * @}
N  */
N
N/** @defgroup CAN_clock_prescaler 
N  * @{
N  */
N#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
N/**
N  * @}
N  */
N
N/** @defgroup CAN_filter_number 
N  * @{
N  */
N#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
N/**
N  * @}
N  */
N
N/** @defgroup CAN_filter_mode 
N  * @{
N  */
N#define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
N#define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
N
N#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
N                                  ((MODE) == CAN_FilterMode_IdList))
X#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) ||                                   ((MODE) == CAN_FilterMode_IdList))
N/**
N  * @}
N  */
N
N/** @defgroup CAN_filter_scale 
N  * @{
N  */
N#define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
N#define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
N
N#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
N                                    ((SCALE) == CAN_FilterScale_32bit))
X#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) ||                                     ((SCALE) == CAN_FilterScale_32bit))
N/**
N  * @}
N  */
N
N/** @defgroup CAN_filter_FIFO
N  * @{
N  */
N#define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
N#define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
N#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
N                                  ((FIFO) == CAN_FilterFIFO1))
X#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) ||                                   ((FIFO) == CAN_FilterFIFO1))
N
N/* Legacy defines */
N#define CAN_FilterFIFO0  CAN_Filter_FIFO0
N#define CAN_FilterFIFO1  CAN_Filter_FIFO1
N/**
N  * @}
N  */
N
N/** @defgroup CAN_Start_bank_filter_for_slave_CAN 
N  * @{
N  */
N#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
N/**
N  * @}
N  */
N
N/** @defgroup CAN_Tx 
N  * @{
N  */
N#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
N#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
N#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
N#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
N/**
N  * @}
N  */
N
N/** @defgroup CAN_identifier_type 
N  * @{
N  */
N#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
N#define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
N#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
N                               ((IDTYPE) == CAN_Id_Extended))
X#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) ||                                ((IDTYPE) == CAN_Id_Extended))
N
N/* Legacy defines */
N#define CAN_ID_STD      CAN_Id_Standard           
N#define CAN_ID_EXT      CAN_Id_Extended
N/**
N  * @}
N  */
N
N/** @defgroup CAN_remote_transmission_request 
N  * @{
N  */
N#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
N#define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
N#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
N
N/* Legacy defines */
N#define CAN_RTR_DATA     CAN_RTR_Data         
N#define CAN_RTR_REMOTE   CAN_RTR_Remote
N/**
N  * @}
N  */
N
N/** @defgroup CAN_transmit_constants 
N  * @{
N  */
N#define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
N#define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
N#define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
N#define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide 
N                                                         an empty mailbox */
N/* Legacy defines */	
N#define CANTXFAILED                  CAN_TxStatus_Failed
N#define CANTXOK                      CAN_TxStatus_Ok
N#define CANTXPENDING                 CAN_TxStatus_Pending
N#define CAN_NO_MB                    CAN_TxStatus_NoMailBox
N/**
N  * @}
N  */
N
N/** @defgroup CAN_receive_FIFO_number_constants 
N  * @{
N  */
N#define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
N#define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
N
N#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
N/**
N  * @}
N  */
N
N/** @defgroup CAN_sleep_constants 
N  * @{
N  */
N#define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
N#define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
N
N/* Legacy defines */	
N#define CANSLEEPFAILED   CAN_Sleep_Failed
N#define CANSLEEPOK       CAN_Sleep_Ok
N/**
N  * @}
N  */
N
N/** @defgroup CAN_wake_up_constants 
N  * @{
N  */
N#define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
N#define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
N
N/* Legacy defines */
N#define CANWAKEUPFAILED   CAN_WakeUp_Failed        
N#define CANWAKEUPOK       CAN_WakeUp_Ok        
N/**
N  * @}
N  */
N
N/**
N  * @defgroup CAN_Error_Code_constants
N  * @{
N  */                                                         
N#define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */ 
N#define	CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */ 
N#define	CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */ 
N#define	CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */ 
N#define	CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ 
N#define	CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */ 
N#define	CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */ 
N#define	CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */ 
N/**
N  * @}
N  */
N
N/** @defgroup CAN_flags 
N  * @{
N  */
N/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
N   and CAN_ClearFlag() functions. */
N/* If the flag is 0x1XXXXXXX, it means that it can only be used with 
N   CAN_GetFlagStatus() function.  */
N
N/* Transmit Flags */
N#define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
N#define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
N#define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
N
N/* Receive Flags */
N#define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
N#define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
N#define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
N#define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
N#define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
N#define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
N
N/* Operating Mode Flags */
N#define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
N#define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
N/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
N         In this case the SLAK bit can be polled.*/
N
N/* Error Flags */
N#define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
N#define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
N#define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
N#define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
N
N#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
N                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
N                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
N                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
N                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
N                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
N                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
N                               ((FLAG) == CAN_FLAG_SLAK ))
X#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   ||                                ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   ||                                ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  ||                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  ||                                ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   ||                                ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) ||                                ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) ||                                ((FLAG) == CAN_FLAG_SLAK ))
N
N#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
N                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
N                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
N                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
N                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
X#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) ||                                 ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) ||                                 ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) ||                                 ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
N/**
N  * @}
N  */
N
N  
N/** @defgroup CAN_interrupts 
N  * @{
N  */ 
N#define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
N
N/* Receive Interrupts */
N#define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
N#define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
N#define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
N#define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
N#define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
N#define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
N
N/* Operating Mode Interrupts */
N#define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
N#define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
N
N/* Error Interrupts */
N#define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
N#define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
N#define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
N#define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
N#define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
N
N/* Flags named as Interrupts : kept only for FW compatibility */
N#define CAN_IT_RQCP0   CAN_IT_TME
N#define CAN_IT_RQCP1   CAN_IT_TME
N#define CAN_IT_RQCP2   CAN_IT_TME
N
N
N#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
N                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
N                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
N                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
N                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
N                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
N                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
X#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
N
N#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
N                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
N                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
N                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
N                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
N                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
X#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/  
N
N/*  Function used to set the CAN configuration to the default reset state *****/ 
Nvoid CAN_DeInit(CAN_TypeDef* CANx);
N
N/* Initialization and Configuration functions *********************************/ 
Nuint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
Nvoid CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
Nvoid CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
Nvoid CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
Nvoid CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
Nvoid CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
N
N/* CAN Frames Transmission functions ******************************************/
Nuint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
Nuint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
Nvoid CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
N
N/* CAN Frames Reception functions *********************************************/
Nvoid CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
Nvoid CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
Nuint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
N
N/* Operation modes functions **************************************************/
Nuint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
Nuint8_t CAN_Sleep(CAN_TypeDef* CANx);
Nuint8_t CAN_WakeUp(CAN_TypeDef* CANx);
N
N/* CAN Bus Error management functions *****************************************/
Nuint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
Nuint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
Nuint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
N
N/* Interrupts and flags management functions **********************************/
Nvoid CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
NFlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
Nvoid CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
NITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
Nvoid CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /* __STM32F4xx_CAN_H */
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 84 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_dac.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_dac.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_dac.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the DAC firmware 
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_DAC_H
N#define __STM32F4xx_DAC_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup DAC
N  * @{
N  */
N
N/* Exported types ------------------------------------------------------------*/
N
N/** 
N  * @brief  DAC Init structure definition
N  */
N
Ntypedef struct
N{
N  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
N                                                  This parameter can be a value of @ref DAC_trigger_selection */
N
N  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
N                                                  are generated, or whether no wave is generated.
N                                                  This parameter can be a value of @ref DAC_wave_generation */
N
N  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
N                                                  the maximum amplitude triangle generation for the DAC channel. 
N                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
N
N  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
N                                                  This parameter can be a value of @ref DAC_output_buffer */
N}DAC_InitTypeDef;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup DAC_Exported_Constants
N  * @{
N  */
N
N/** @defgroup DAC_trigger_selection 
N  * @{
N  */
N
N#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
N                                                                       has been loaded, and not by external trigger */
N#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
N#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
N#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
N#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
N#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
N#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
N
N#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
N#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
N
N#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
N                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
N                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
N                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
N                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
N                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
N                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
N                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
N                                 ((TRIGGER) == DAC_Trigger_Software))
X#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) ||                                  ((TRIGGER) == DAC_Trigger_T6_TRGO) ||                                  ((TRIGGER) == DAC_Trigger_T8_TRGO) ||                                  ((TRIGGER) == DAC_Trigger_T7_TRGO) ||                                  ((TRIGGER) == DAC_Trigger_T5_TRGO) ||                                  ((TRIGGER) == DAC_Trigger_T2_TRGO) ||                                  ((TRIGGER) == DAC_Trigger_T4_TRGO) ||                                  ((TRIGGER) == DAC_Trigger_Ext_IT9) ||                                  ((TRIGGER) == DAC_Trigger_Software))
N
N/**
N  * @}
N  */
N
N/** @defgroup DAC_wave_generation 
N  * @{
N  */
N
N#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
N#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
N#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
N#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
N                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
N                                    ((WAVE) == DAC_WaveGeneration_Triangle))
X#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) ||                                     ((WAVE) == DAC_WaveGeneration_Noise) ||                                     ((WAVE) == DAC_WaveGeneration_Triangle))
N/**
N  * @}
N  */
N
N/** @defgroup DAC_lfsrunmask_triangleamplitude
N  * @{
N  */
N
N#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
N#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
N#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
N#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
N#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
N#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
N#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
N#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
N#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
N#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
N#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
N#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
N#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
N#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
N#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
N#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
N#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
N#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
N#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
N#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
N#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
N#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
N#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
N#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
N
N#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
N                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
N                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
N                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
N                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
N                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
N                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
N                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
N                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
N                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
N                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
N                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
N                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
N                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
N                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
N                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
N                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
N                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
N                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
N                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
N                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
N                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
N                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
N                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
X#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) ||                                                       ((VALUE) == DAC_LFSRUnmask_Bits1_0) ||                                                       ((VALUE) == DAC_LFSRUnmask_Bits2_0) ||                                                       ((VALUE) == DAC_LFSRUnmask_Bits3_0) ||                                                       ((VALUE) == DAC_LFSRUnmask_Bits4_0) ||                                                       ((VALUE) == DAC_LFSRUnmask_Bits5_0) ||                                                       ((VALUE) == DAC_LFSRUnmask_Bits6_0) ||                                                       ((VALUE) == DAC_LFSRUnmask_Bits7_0) ||                                                       ((VALUE) == DAC_LFSRUnmask_Bits8_0) ||                                                       ((VALUE) == DAC_LFSRUnmask_Bits9_0) ||                                                       ((VALUE) == DAC_LFSRUnmask_Bits10_0) ||                                                       ((VALUE) == DAC_LFSRUnmask_Bits11_0) ||                                                       ((VALUE) == DAC_TriangleAmplitude_1) ||                                                       ((VALUE) == DAC_TriangleAmplitude_3) ||                                                       ((VALUE) == DAC_TriangleAmplitude_7) ||                                                       ((VALUE) == DAC_TriangleAmplitude_15) ||                                                       ((VALUE) == DAC_TriangleAmplitude_31) ||                                                       ((VALUE) == DAC_TriangleAmplitude_63) ||                                                       ((VALUE) == DAC_TriangleAmplitude_127) ||                                                       ((VALUE) == DAC_TriangleAmplitude_255) ||                                                       ((VALUE) == DAC_TriangleAmplitude_511) ||                                                       ((VALUE) == DAC_TriangleAmplitude_1023) ||                                                       ((VALUE) == DAC_TriangleAmplitude_2047) ||                                                       ((VALUE) == DAC_TriangleAmplitude_4095))
N/**
N  * @}
N  */
N
N/** @defgroup DAC_output_buffer 
N  * @{
N  */
N
N#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
N#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
N#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
N                                           ((STATE) == DAC_OutputBuffer_Disable))
X#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) ||                                            ((STATE) == DAC_OutputBuffer_Disable))
N/**
N  * @}
N  */
N
N/** @defgroup DAC_Channel_selection 
N  * @{
N  */
N
N#define DAC_Channel_1                      ((uint32_t)0x00000000)
N#define DAC_Channel_2                      ((uint32_t)0x00000010)
N#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
N                                 ((CHANNEL) == DAC_Channel_2))
X#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) ||                                  ((CHANNEL) == DAC_Channel_2))
N/**
N  * @}
N  */
N
N/** @defgroup DAC_data_alignement 
N  * @{
N  */
N
N#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
N#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
N#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
N#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
N                             ((ALIGN) == DAC_Align_12b_L) || \
N                             ((ALIGN) == DAC_Align_8b_R))
X#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) ||                              ((ALIGN) == DAC_Align_12b_L) ||                              ((ALIGN) == DAC_Align_8b_R))
N/**
N  * @}
N  */
N
N/** @defgroup DAC_wave_generation 
N  * @{
N  */
N
N#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
N#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
N#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
N                           ((WAVE) == DAC_Wave_Triangle))
X#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) ||                            ((WAVE) == DAC_Wave_Triangle))
N/**
N  * @}
N  */
N
N/** @defgroup DAC_data 
N  * @{
N  */
N
N#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
N/**
N  * @}
N  */
N  
N/** @defgroup DAC_interrupts_definition 
N  * @{
N  */   
N#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
N#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
N
N/**
N  * @}
N  */ 
N
N/** @defgroup DAC_flags_definition 
N  * @{
N  */ 
N  
N#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)  
N#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/  
N
N/*  Function used to set the DAC configuration to the default reset state *****/  
Nvoid DAC_DeInit(void);
N
N/*  DAC channels configuration: trigger, output buffer, data format functions */
Nvoid DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
Nvoid DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
Nvoid DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
Nvoid DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
Nvoid DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
Nvoid DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
Nvoid DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
Nvoid DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
Nvoid DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
Nuint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
N
N/* DMA management functions ***************************************************/
Nvoid DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
N
N/* Interrupts and flags management functions **********************************/
Nvoid DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
NFlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
Nvoid DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
NITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
Nvoid DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_DAC_H */
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 85 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_dcmi.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_dcmi.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_dcmi.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the DCMI firmware library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_DCMI_H
N#define __STM32F4xx_DCMI_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup DCMI
N  * @{
N  */ 
N
N/* Exported types ------------------------------------------------------------*/
N/** 
N  * @brief   DCMI Init structure definition  
N  */ 
Ntypedef struct
N{
N  uint16_t DCMI_CaptureMode;      /*!< Specifies the Capture Mode: Continuous or Snapshot.
N                                       This parameter can be a value of @ref DCMI_Capture_Mode */
N
N  uint16_t DCMI_SynchroMode;      /*!< Specifies the Synchronization Mode: Hardware or Embedded.
N                                       This parameter can be a value of @ref DCMI_Synchronization_Mode */
N
N  uint16_t DCMI_PCKPolarity;      /*!< Specifies the Pixel clock polarity: Falling or Rising.
N                                       This parameter can be a value of @ref DCMI_PIXCK_Polarity */
N
N  uint16_t DCMI_VSPolarity;       /*!< Specifies the Vertical synchronization polarity: High or Low.
N                                       This parameter can be a value of @ref DCMI_VSYNC_Polarity */
N
N  uint16_t DCMI_HSPolarity;       /*!< Specifies the Horizontal synchronization polarity: High or Low.
N                                       This parameter can be a value of @ref DCMI_HSYNC_Polarity */
N
N  uint16_t DCMI_CaptureRate;      /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
N                                       This parameter can be a value of @ref DCMI_Capture_Rate */
N
N  uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
N                                       This parameter can be a value of @ref DCMI_Extended_Data_Mode */
N} DCMI_InitTypeDef;
N
N/** 
N  * @brief   DCMI CROP Init structure definition  
N  */ 
Ntypedef struct
N{
N  uint16_t DCMI_VerticalStartLine;      /*!< Specifies the Vertical start line count from which the image capture
N                                             will start. This parameter can be a value between 0x00 and 0x1FFF */
N
N  uint16_t DCMI_HorizontalOffsetCount;  /*!< Specifies the number of pixel clocks to count before starting a capture.
N                                             This parameter can be a value between 0x00 and 0x3FFF */
N
N  uint16_t DCMI_VerticalLineCount;      /*!< Specifies the number of lines to be captured from the starting point.
N                                             This parameter can be a value between 0x00 and 0x3FFF */
N
N  uint16_t DCMI_CaptureCount;           /*!< Specifies the number of pixel clocks to be captured from the starting
N                                             point on the same line.
N                                             This parameter can be a value between 0x00 and 0x3FFF */
N} DCMI_CROPInitTypeDef;
N
N/** 
N  * @brief   DCMI Embedded Synchronisation CODE Init structure definition  
N  */ 
Ntypedef struct
N{
N  uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
N  uint8_t DCMI_LineStartCode;  /*!< Specifies the code of the line start delimiter. */
N  uint8_t DCMI_LineEndCode;    /*!< Specifies the code of the line end delimiter. */
N  uint8_t DCMI_FrameEndCode;   /*!< Specifies the code of the frame end delimiter. */
N} DCMI_CodesInitTypeDef;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup DCMI_Exported_Constants
N  * @{
N  */
N
N/** @defgroup DCMI_Capture_Mode 
N  * @{
N  */ 
N#define DCMI_CaptureMode_Continuous    ((uint16_t)0x0000) /*!< The received data are transferred continuously 
N                                                               into the destination memory through the DMA */
N#define DCMI_CaptureMode_SnapShot      ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of 
N                                                               frame and then transfers a single frame through the DMA */
N#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \
N                                   ((MODE) == DCMI_CaptureMode_SnapShot))
X#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) ||                                    ((MODE) == DCMI_CaptureMode_SnapShot))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DCMI_Synchronization_Mode
N  * @{
N  */ 
N#define DCMI_SynchroMode_Hardware    ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop)
N                                                             is synchronized with the HSYNC/VSYNC signals */
N#define DCMI_SynchroMode_Embedded    ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with 
N                                                             synchronization codes embedded in the data flow */
N#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \
N                              ((MODE) == DCMI_SynchroMode_Embedded))
X#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) ||                               ((MODE) == DCMI_SynchroMode_Embedded))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DCMI_PIXCK_Polarity 
N  * @{
N  */ 
N#define DCMI_PCKPolarity_Falling    ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */
N#define DCMI_PCKPolarity_Rising     ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */
N#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \
N                                      ((POLARITY) == DCMI_PCKPolarity_Rising))
X#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) ||                                       ((POLARITY) == DCMI_PCKPolarity_Rising))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DCMI_VSYNC_Polarity 
N  * @{
N  */ 
N#define DCMI_VSPolarity_Low     ((uint16_t)0x0000) /*!< Vertical synchronization active Low */
N#define DCMI_VSPolarity_High    ((uint16_t)0x0080) /*!< Vertical synchronization active High */
N#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \
N                                     ((POLARITY) == DCMI_VSPolarity_High))
X#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) ||                                      ((POLARITY) == DCMI_VSPolarity_High))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DCMI_HSYNC_Polarity 
N  * @{
N  */ 
N#define DCMI_HSPolarity_Low     ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */
N#define DCMI_HSPolarity_High    ((uint16_t)0x0040) /*!< Horizontal synchronization active High */
N#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \
N                                     ((POLARITY) == DCMI_HSPolarity_High))
X#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) ||                                      ((POLARITY) == DCMI_HSPolarity_High))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DCMI_Capture_Rate 
N  * @{
N  */ 
N#define DCMI_CaptureRate_All_Frame     ((uint16_t)0x0000) /*!< All frames are captured */
N#define DCMI_CaptureRate_1of2_Frame    ((uint16_t)0x0100) /*!< Every alternate frame captured */
N#define DCMI_CaptureRate_1of4_Frame    ((uint16_t)0x0200) /*!< One frame in 4 frames captured */
N#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \
N                                    ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\
N                                    ((RATE) == DCMI_CaptureRate_1of4_Frame))
X#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) ||                                     ((RATE) == DCMI_CaptureRate_1of2_Frame) ||                                    ((RATE) == DCMI_CaptureRate_1of4_Frame))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DCMI_Extended_Data_Mode 
N  * @{
N  */ 
N#define DCMI_ExtendedDataMode_8b     ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */
N#define DCMI_ExtendedDataMode_10b    ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */
N#define DCMI_ExtendedDataMode_12b    ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */
N#define DCMI_ExtendedDataMode_14b    ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */
N#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \
N                                    ((DATA) == DCMI_ExtendedDataMode_10b) ||\
N                                    ((DATA) == DCMI_ExtendedDataMode_12b) ||\
N                                    ((DATA) == DCMI_ExtendedDataMode_14b))
X#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) ||                                     ((DATA) == DCMI_ExtendedDataMode_10b) ||                                    ((DATA) == DCMI_ExtendedDataMode_12b) ||                                    ((DATA) == DCMI_ExtendedDataMode_14b))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DCMI_interrupt_sources 
N  * @{
N  */ 
N#define DCMI_IT_FRAME    ((uint16_t)0x0001)
N#define DCMI_IT_OVF      ((uint16_t)0x0002)
N#define DCMI_IT_ERR      ((uint16_t)0x0004)
N#define DCMI_IT_VSYNC    ((uint16_t)0x0008)
N#define DCMI_IT_LINE     ((uint16_t)0x0010)
N#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
N#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
N                            ((IT) == DCMI_IT_OVF) || \
N                            ((IT) == DCMI_IT_ERR) || \
N                            ((IT) == DCMI_IT_VSYNC) || \
N                            ((IT) == DCMI_IT_LINE))
X#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) ||                             ((IT) == DCMI_IT_OVF) ||                             ((IT) == DCMI_IT_ERR) ||                             ((IT) == DCMI_IT_VSYNC) ||                             ((IT) == DCMI_IT_LINE))
N/**
N  * @}
N  */ 
N
N
N/** @defgroup DCMI_Flags 
N  * @{
N  */ 
N/** 
N  * @brief   DCMI SR register  
N  */ 
N#define DCMI_FLAG_HSYNC     ((uint16_t)0x2001)
N#define DCMI_FLAG_VSYNC     ((uint16_t)0x2002)
N#define DCMI_FLAG_FNE       ((uint16_t)0x2004)
N/** 
N  * @brief   DCMI RISR register  
N  */ 
N#define DCMI_FLAG_FRAMERI    ((uint16_t)0x0001)
N#define DCMI_FLAG_OVFRI      ((uint16_t)0x0002)
N#define DCMI_FLAG_ERRRI      ((uint16_t)0x0004)
N#define DCMI_FLAG_VSYNCRI    ((uint16_t)0x0008)
N#define DCMI_FLAG_LINERI     ((uint16_t)0x0010)
N/** 
N  * @brief   DCMI MISR register  
N  */ 
N#define DCMI_FLAG_FRAMEMI    ((uint16_t)0x1001)
N#define DCMI_FLAG_OVFMI      ((uint16_t)0x1002)
N#define DCMI_FLAG_ERRMI      ((uint16_t)0x1004)
N#define DCMI_FLAG_VSYNCMI    ((uint16_t)0x1008)
N#define DCMI_FLAG_LINEMI     ((uint16_t)0x1010)
N#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
N                                ((FLAG) == DCMI_FLAG_VSYNC) || \
N                                ((FLAG) == DCMI_FLAG_FNE) || \
N                                ((FLAG) == DCMI_FLAG_FRAMERI) || \
N                                ((FLAG) == DCMI_FLAG_OVFRI) || \
N                                ((FLAG) == DCMI_FLAG_ERRRI) || \
N                                ((FLAG) == DCMI_FLAG_VSYNCRI) || \
N                                ((FLAG) == DCMI_FLAG_LINERI) || \
N                                ((FLAG) == DCMI_FLAG_FRAMEMI) || \
N                                ((FLAG) == DCMI_FLAG_OVFMI) || \
N                                ((FLAG) == DCMI_FLAG_ERRMI) || \
N                                ((FLAG) == DCMI_FLAG_VSYNCMI) || \
N                                ((FLAG) == DCMI_FLAG_LINEMI))
X#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) ||                                 ((FLAG) == DCMI_FLAG_VSYNC) ||                                 ((FLAG) == DCMI_FLAG_FNE) ||                                 ((FLAG) == DCMI_FLAG_FRAMERI) ||                                 ((FLAG) == DCMI_FLAG_OVFRI) ||                                 ((FLAG) == DCMI_FLAG_ERRRI) ||                                 ((FLAG) == DCMI_FLAG_VSYNCRI) ||                                 ((FLAG) == DCMI_FLAG_LINERI) ||                                 ((FLAG) == DCMI_FLAG_FRAMEMI) ||                                 ((FLAG) == DCMI_FLAG_OVFMI) ||                                 ((FLAG) == DCMI_FLAG_ERRMI) ||                                 ((FLAG) == DCMI_FLAG_VSYNCMI) ||                                 ((FLAG) == DCMI_FLAG_LINEMI))
N                                
N#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N
N/*  Function used to set the DCMI configuration to the default reset state ****/ 
Nvoid DCMI_DeInit(void);
N
N/* Initialization and Configuration functions *********************************/
Nvoid DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct);
Nvoid DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct);
Nvoid DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct);
Nvoid DCMI_CROPCmd(FunctionalState NewState);
Nvoid DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct);
Nvoid DCMI_JPEGCmd(FunctionalState NewState);
N
N/* Image capture functions ****************************************************/
Nvoid DCMI_Cmd(FunctionalState NewState);
Nvoid DCMI_CaptureCmd(FunctionalState NewState);
Nuint32_t DCMI_ReadData(void);
N
N/* Interrupts and flags management functions **********************************/
Nvoid DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState);
NFlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG);
Nvoid DCMI_ClearFlag(uint16_t DCMI_FLAG);
NITStatus DCMI_GetITStatus(uint16_t DCMI_IT);
Nvoid DCMI_ClearITPendingBit(uint16_t DCMI_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_DCMI_H */
N
N/**
N  * @}
N  */ 
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 86 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#include "stm32f4xx_fsmc.h"
L 1 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_fsmc.h" 1
N/**
N  ******************************************************************************
N  * @file    stm32f4xx_fsmc.h
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   This file contains all the functions prototypes for the FSMC firmware 
N  *          library.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_FSMC_H
N#define __STM32F4xx_FSMC_H
N
N#ifdef __cplusplus
S extern "C" {
N#endif
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f4xx.h"
N
N/** @addtogroup STM32F4xx_StdPeriph_Driver
N  * @{
N  */
N
N/** @addtogroup FSMC
N  * @{
N  */
N
N/* Exported types ------------------------------------------------------------*/
N
N/** 
N  * @brief  Timing parameters For NOR/SRAM Banks  
N  */
Ntypedef struct
N{
N  uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
N                                             the duration of the address setup time. 
N                                             This parameter can be a value between 0 and 0xF.
N                                             @note This parameter is not used with synchronous NOR Flash memories. */
N
N  uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
N                                             the duration of the address hold time.
N                                             This parameter can be a value between 0 and 0xF. 
N                                             @note This parameter is not used with synchronous NOR Flash memories.*/
N
N  uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
N                                             the duration of the data setup time.
N                                             This parameter can be a value between 0 and 0xFF.
N                                             @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
N
N  uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
N                                             the duration of the bus turnaround.
N                                             This parameter can be a value between 0 and 0xF.
N                                             @note This parameter is only used for multiplexed NOR Flash memories. */
N
N  uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
N                                             This parameter can be a value between 1 and 0xF.
N                                             @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
N
N  uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
N                                             to the memory before getting the first data.
N                                             The parameter value depends on the memory type as shown below:
N                                              - It must be set to 0 in case of a CRAM
N                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
N                                              - It may assume a value between 0 and 0xF in NOR Flash memories
N                                                with synchronous burst mode enable */
N
N  uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
N                                             This parameter can be a value of @ref FSMC_Access_Mode */
N}FSMC_NORSRAMTimingInitTypeDef;
N
N/** 
N  * @brief  FSMC NOR/SRAM Init structure definition
N  */
Ntypedef struct
N{
N  uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
N                                          This parameter can be a value of @ref FSMC_NORSRAM_Bank */
N
N  uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
N                                          multiplexed on the data bus or not. 
N                                          This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
N
N  uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
N                                          the corresponding memory bank.
N                                          This parameter can be a value of @ref FSMC_Memory_Type */
N
N  uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
N                                          This parameter can be a value of @ref FSMC_Data_Width */
N
N  uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
N                                          valid only with synchronous burst Flash memories.
N                                          This parameter can be a value of @ref FSMC_Burst_Access_Mode */
N
N  uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
N                                          valid only with asynchronous Flash memories.
N                                          This parameter can be a value of @ref FSMC_AsynchronousWait */                                          
N
N  uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
N                                          the Flash memory in burst mode.
N                                          This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
N
N  uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
N                                          memory, valid only when accessing Flash memories in burst mode.
N                                          This parameter can be a value of @ref FSMC_Wrap_Mode */
N
N  uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
N                                          clock cycle before the wait state or during the wait state,
N                                          valid only when accessing memories in burst mode. 
N                                          This parameter can be a value of @ref FSMC_Wait_Timing */
N
N  uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC. 
N                                          This parameter can be a value of @ref FSMC_Write_Operation */
N
N  uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait state insertion via wait
N                                          signal, valid for Flash memory access in burst mode. 
N                                          This parameter can be a value of @ref FSMC_Wait_Signal */
N
N  uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
N                                          This parameter can be a value of @ref FSMC_Extended_Mode */
N
N  uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
N                                          This parameter can be a value of @ref FSMC_Write_Burst */ 
N
N  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  Extended Mode is not used*/  
N
N  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  Extended Mode is used*/      
N}FSMC_NORSRAMInitTypeDef;
N
N/** 
N  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
N  */
Ntypedef struct
N{
N  uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
N                                     the command assertion for NAND Flash read or write access
N                                     to common/Attribute or I/O memory space (depending on
N                                     the memory space timing to be configured).
N                                     This parameter can be a value between 0 and 0xFF.*/
N
N  uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
N                                     command for NAND Flash read or write access to
N                                     common/Attribute or I/O memory space (depending on the
N                                     memory space timing to be configured). 
N                                     This parameter can be a number between 0x00 and 0xFF */
N
N  uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
N                                     (and data for write access) after the command de-assertion
N                                     for NAND Flash read or write access to common/Attribute
N                                     or I/O memory space (depending on the memory space timing
N                                     to be configured).
N                                     This parameter can be a number between 0x00 and 0xFF */
N
N  uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
N                                     data bus is kept in HiZ after the start of a NAND Flash
N                                     write access to common/Attribute or I/O memory space (depending
N                                     on the memory space timing to be configured).
N                                     This parameter can be a number between 0x00 and 0xFF */
N}FSMC_NAND_PCCARDTimingInitTypeDef;
N
N/** 
N  * @brief  FSMC NAND Init structure definition
N  */
Ntypedef struct
N{
N  uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
N                                      This parameter can be a value of @ref FSMC_NAND_Bank */
N
N  uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
N                                       This parameter can be any value of @ref FSMC_Wait_feature */
N
N  uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
N                                       This parameter can be any value of @ref FSMC_Data_Width */
N
N  uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
N                                       This parameter can be any value of @ref FSMC_ECC */
N
N  uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
N                                       This parameter can be any value of @ref FSMC_ECC_Page_Size */
N
N  uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
N                                       delay between CLE low and RE low.
N                                       This parameter can be a value between 0 and 0xFF. */
N
N  uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
N                                       delay between ALE low and RE low.
N                                       This parameter can be a number between 0x0 and 0xFF */ 
N
N  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */ 
N
N  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
N}FSMC_NANDInitTypeDef;
N
N/** 
N  * @brief  FSMC PCCARD Init structure definition
N  */
N
Ntypedef struct
N{
N  uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
N                                    This parameter can be any value of @ref FSMC_Wait_feature */
N
N  uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
N                                     delay between CLE low and RE low.
N                                     This parameter can be a value between 0 and 0xFF. */
N
N  uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
N                                     delay between ALE low and RE low.
N                                     This parameter can be a number between 0x0 and 0xFF */ 
N
N  
N  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
N
N  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */ 
N  
N  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */  
N}FSMC_PCCARDInitTypeDef;
N
N/* Exported constants --------------------------------------------------------*/
N
N/** @defgroup FSMC_Exported_Constants
N  * @{
N  */
N
N/** @defgroup FSMC_NORSRAM_Bank 
N  * @{
N  */
N#define FSMC_Bank1_NORSRAM1                      ((uint32_t)0x00000000)
N#define FSMC_Bank1_NORSRAM2                      ((uint32_t)0x00000002)
N#define FSMC_Bank1_NORSRAM3                      ((uint32_t)0x00000004)
N#define FSMC_Bank1_NORSRAM4                      ((uint32_t)0x00000006)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_NAND_Bank 
N  * @{
N  */  
N#define FSMC_Bank2_NAND                          ((uint32_t)0x00000010)
N#define FSMC_Bank3_NAND                          ((uint32_t)0x00000100)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_PCCARD_Bank 
N  * @{
N  */    
N#define FSMC_Bank4_PCCARD                        ((uint32_t)0x00001000)
N/**
N  * @}
N  */
N
N#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
N                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
N                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
N                                    ((BANK) == FSMC_Bank1_NORSRAM4))
X#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) ||                                     ((BANK) == FSMC_Bank1_NORSRAM2) ||                                     ((BANK) == FSMC_Bank1_NORSRAM3) ||                                     ((BANK) == FSMC_Bank1_NORSRAM4))
N
N#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
N                                 ((BANK) == FSMC_Bank3_NAND))
X#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) ||                                  ((BANK) == FSMC_Bank3_NAND))
N
N#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
N                                    ((BANK) == FSMC_Bank3_NAND) || \
N                                    ((BANK) == FSMC_Bank4_PCCARD))
X#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) ||                                     ((BANK) == FSMC_Bank3_NAND) ||                                     ((BANK) == FSMC_Bank4_PCCARD))
N
N#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
N                               ((BANK) == FSMC_Bank3_NAND) || \
N                               ((BANK) == FSMC_Bank4_PCCARD))
X#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) ||                                ((BANK) == FSMC_Bank3_NAND) ||                                ((BANK) == FSMC_Bank4_PCCARD))
N
N/** @defgroup FSMC_NOR_SRAM_Controller 
N  * @{
N  */
N
N/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
N  * @{
N  */
N
N#define FSMC_DataAddressMux_Disable                ((uint32_t)0x00000000)
N#define FSMC_DataAddressMux_Enable                 ((uint32_t)0x00000002)
N#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
N                          ((MUX) == FSMC_DataAddressMux_Enable))
X#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) ||                           ((MUX) == FSMC_DataAddressMux_Enable))
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Memory_Type 
N  * @{
N  */
N
N#define FSMC_MemoryType_SRAM                     ((uint32_t)0x00000000)
N#define FSMC_MemoryType_PSRAM                    ((uint32_t)0x00000004)
N#define FSMC_MemoryType_NOR                      ((uint32_t)0x00000008)
N#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
N                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
N                                ((MEMORY) == FSMC_MemoryType_NOR))
X#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) ||                                 ((MEMORY) == FSMC_MemoryType_PSRAM)||                                 ((MEMORY) == FSMC_MemoryType_NOR))
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Data_Width 
N  * @{
N  */
N
N#define FSMC_MemoryDataWidth_8b                  ((uint32_t)0x00000000)
N#define FSMC_MemoryDataWidth_16b                 ((uint32_t)0x00000010)
N#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
N                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
X#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) ||                                      ((WIDTH) == FSMC_MemoryDataWidth_16b))
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Burst_Access_Mode 
N  * @{
N  */
N
N#define FSMC_BurstAccessMode_Disable             ((uint32_t)0x00000000) 
N#define FSMC_BurstAccessMode_Enable              ((uint32_t)0x00000100)
N#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
N                                  ((STATE) == FSMC_BurstAccessMode_Enable))
X#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) ||                                   ((STATE) == FSMC_BurstAccessMode_Enable))
N/**
N  * @}
N  */
N    
N/** @defgroup FSMC_AsynchronousWait 
N  * @{
N  */
N#define FSMC_AsynchronousWait_Disable            ((uint32_t)0x00000000)
N#define FSMC_AsynchronousWait_Enable             ((uint32_t)0x00008000)
N#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
N                                 ((STATE) == FSMC_AsynchronousWait_Enable))
X#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) ||                                  ((STATE) == FSMC_AsynchronousWait_Enable))
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Wait_Signal_Polarity 
N  * @{
N  */
N#define FSMC_WaitSignalPolarity_Low              ((uint32_t)0x00000000)
N#define FSMC_WaitSignalPolarity_High             ((uint32_t)0x00000200)
N#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
N                                         ((POLARITY) == FSMC_WaitSignalPolarity_High))
X#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) ||                                          ((POLARITY) == FSMC_WaitSignalPolarity_High))
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Wrap_Mode 
N  * @{
N  */
N#define FSMC_WrapMode_Disable                    ((uint32_t)0x00000000)
N#define FSMC_WrapMode_Enable                     ((uint32_t)0x00000400) 
N#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
N                                 ((MODE) == FSMC_WrapMode_Enable))
X#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) ||                                  ((MODE) == FSMC_WrapMode_Enable))
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Wait_Timing 
N  * @{
N  */
N#define FSMC_WaitSignalActive_BeforeWaitState    ((uint32_t)0x00000000)
N#define FSMC_WaitSignalActive_DuringWaitState    ((uint32_t)0x00000800) 
N#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
N                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
X#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) ||                                             ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Write_Operation 
N  * @{
N  */
N#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
N#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
N#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
N                                            ((OPERATION) == FSMC_WriteOperation_Enable))                         
X#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) ||                                             ((OPERATION) == FSMC_WriteOperation_Enable))                         
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Wait_Signal 
N  * @{
N  */
N#define FSMC_WaitSignal_Disable                  ((uint32_t)0x00000000)
N#define FSMC_WaitSignal_Enable                   ((uint32_t)0x00002000) 
N#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
N                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
X#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) ||                                       ((SIGNAL) == FSMC_WaitSignal_Enable))
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Extended_Mode 
N  * @{
N  */
N#define FSMC_ExtendedMode_Disable                ((uint32_t)0x00000000)
N#define FSMC_ExtendedMode_Enable                 ((uint32_t)0x00004000)
N
N#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
N                                     ((MODE) == FSMC_ExtendedMode_Enable)) 
X#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) ||                                      ((MODE) == FSMC_ExtendedMode_Enable)) 
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Write_Burst 
N  * @{
N  */
N
N#define FSMC_WriteBurst_Disable                  ((uint32_t)0x00000000)
N#define FSMC_WriteBurst_Enable                   ((uint32_t)0x00080000) 
N#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
N                                    ((BURST) == FSMC_WriteBurst_Enable))
X#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) ||                                     ((BURST) == FSMC_WriteBurst_Enable))
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Address_Setup_Time 
N  * @{
N  */
N#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Address_Hold_Time 
N  * @{
N  */
N#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Data_Setup_Time 
N  * @{
N  */
N#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Bus_Turn_around_Duration 
N  * @{
N  */
N#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_CLK_Division 
N  * @{
N  */
N#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Data_Latency 
N  * @{
N  */
N#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Access_Mode 
N  * @{
N  */
N#define FSMC_AccessMode_A                        ((uint32_t)0x00000000)
N#define FSMC_AccessMode_B                        ((uint32_t)0x10000000) 
N#define FSMC_AccessMode_C                        ((uint32_t)0x20000000)
N#define FSMC_AccessMode_D                        ((uint32_t)0x30000000)
N#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
N                                   ((MODE) == FSMC_AccessMode_B) || \
N                                   ((MODE) == FSMC_AccessMode_C) || \
N                                   ((MODE) == FSMC_AccessMode_D))
X#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) ||                                    ((MODE) == FSMC_AccessMode_B) ||                                    ((MODE) == FSMC_AccessMode_C) ||                                    ((MODE) == FSMC_AccessMode_D))
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N  
N/** @defgroup FSMC_NAND_PCCARD_Controller 
N  * @{
N  */
N
N/** @defgroup FSMC_Wait_feature 
N  * @{
N  */
N#define FSMC_Waitfeature_Disable                 ((uint32_t)0x00000000)
N#define FSMC_Waitfeature_Enable                  ((uint32_t)0x00000002)
N#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
N                                       ((FEATURE) == FSMC_Waitfeature_Enable))
X#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) ||                                        ((FEATURE) == FSMC_Waitfeature_Enable))
N/**
N  * @}
N  */
N
N
N/** @defgroup FSMC_ECC 
N  * @{
N  */
N#define FSMC_ECC_Disable                         ((uint32_t)0x00000000)
N#define FSMC_ECC_Enable                          ((uint32_t)0x00000040)
N#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
N                                  ((STATE) == FSMC_ECC_Enable))
X#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) ||                                   ((STATE) == FSMC_ECC_Enable))
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_ECC_Page_Size 
N  * @{
N  */
N#define FSMC_ECCPageSize_256Bytes                ((uint32_t)0x00000000)
N#define FSMC_ECCPageSize_512Bytes                ((uint32_t)0x00020000)
N#define FSMC_ECCPageSize_1024Bytes               ((uint32_t)0x00040000)
N#define FSMC_ECCPageSize_2048Bytes               ((uint32_t)0x00060000)
N#define FSMC_ECCPageSize_4096Bytes               ((uint32_t)0x00080000)
N#define FSMC_ECCPageSize_8192Bytes               ((uint32_t)0x000A0000)
N#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
N                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
N                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
N                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
N                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
N                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
X#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) ||                                     ((SIZE) == FSMC_ECCPageSize_512Bytes) ||                                     ((SIZE) == FSMC_ECCPageSize_1024Bytes) ||                                     ((SIZE) == FSMC_ECCPageSize_2048Bytes) ||                                     ((SIZE) == FSMC_ECCPageSize_4096Bytes) ||                                     ((SIZE) == FSMC_ECCPageSize_8192Bytes))
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_TCLR_Setup_Time 
N  * @{
N  */
N#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_TAR_Setup_Time 
N  * @{
N  */
N#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Setup_Time 
N  * @{
N  */
N#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Wait_Setup_Time 
N  * @{
N  */
N#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Hold_Setup_Time 
N  * @{
N  */
N#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_HiZ_Setup_Time 
N  * @{
N  */
N#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Interrupt_sources 
N  * @{
N  */
N#define FSMC_IT_RisingEdge                       ((uint32_t)0x00000008)
N#define FSMC_IT_Level                            ((uint32_t)0x00000010)
N#define FSMC_IT_FallingEdge                      ((uint32_t)0x00000020)
N#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
N#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
N                            ((IT) == FSMC_IT_Level) || \
N                            ((IT) == FSMC_IT_FallingEdge)) 
X#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) ||                             ((IT) == FSMC_IT_Level) ||                             ((IT) == FSMC_IT_FallingEdge)) 
N/**
N  * @}
N  */
N
N/** @defgroup FSMC_Flags 
N  * @{
N  */
N#define FSMC_FLAG_RisingEdge                     ((uint32_t)0x00000001)
N#define FSMC_FLAG_Level                          ((uint32_t)0x00000002)
N#define FSMC_FLAG_FallingEdge                    ((uint32_t)0x00000004)
N#define FSMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
N#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
N                                ((FLAG) == FSMC_FLAG_Level) || \
N                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
N                                ((FLAG) == FSMC_FLAG_FEMPT))
X#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) ||                                 ((FLAG) == FSMC_FLAG_Level) ||                                 ((FLAG) == FSMC_FLAG_FallingEdge) ||                                 ((FLAG) == FSMC_FLAG_FEMPT))
N
N#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */
N
N/* Exported macro ------------------------------------------------------------*/
N/* Exported functions --------------------------------------------------------*/ 
N
N/* NOR/SRAM Controller functions **********************************************/
Nvoid FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
Nvoid FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
Nvoid FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
Nvoid FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
N
N/* NAND Controller functions **************************************************/
Nvoid FSMC_NANDDeInit(uint32_t FSMC_Bank);
Nvoid FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
Nvoid FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
Nvoid FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
Nvoid FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
Nuint32_t FSMC_GetECC(uint32_t FSMC_Bank);
N
N/* PCCARD Controller functions ************************************************/
Nvoid FSMC_PCCARDDeInit(void);
Nvoid FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
Nvoid FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
Nvoid FSMC_PCCARDCmd(FunctionalState NewState);
N
N/* Interrupts and flags management functions **********************************/
Nvoid FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
NFlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
Nvoid FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
NITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
Nvoid FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
N
N#ifdef __cplusplus
S}
N#endif
N
N#endif /*__STM32F4xx_FSMC_H */
N/**
N  * @}
N  */
N
N/**
N  * @}
N  */ 
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 87 "..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_conf.h" 2
N#endif /* STM32F40_41xxx */
N
N#if defined (STM32F411xE)
X#if 0L
S#include "stm32f4xx_flash_ramfunc.h"
N#endif /* STM32F411xE */
N/* Exported types ------------------------------------------------------------*/
N/* Exported constants --------------------------------------------------------*/
N
N/* If an external clock source is used, then the value of the following define 
N   should be set to the value of the external clock source, else, if no external 
N   clock is used, keep this define commented */
N/*#define I2S_EXTERNAL_CLOCK_VAL   12288000 */ /* Value of the external clock in Hz */
N
N
N/* Uncomment the line below to expanse the "assert_param" macro in the 
N   Standard Peripheral Library drivers code */
N/* #define USE_FULL_ASSERT    1 */
N
N/* Exported macro ------------------------------------------------------------*/
N#ifdef  USE_FULL_ASSERT
S
S/**
S  * @brief  The assert_param macro is used for function's parameters check.
S  * @param  expr: If expr is false, it calls assert_failed function
S  *   which reports the name of the source file and the source
S  *   line number of the call that failed. 
S  *   If expr is true, it returns no value.
S  * @retval None
S  */
S  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
S/* Exported functions ------------------------------------------------------- */
S  void assert_failed(uint8_t* file, uint32_t line);
N#else
N  #define assert_param(expr) ((void)0)
N#endif /* USE_FULL_ASSERT */
N
N#endif /* __STM32F4xx_CONF_H */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 9136 "..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h" 2
N#endif /* USE_STDPERIPH_DRIVER */
N
N/** @addtogroup Exported_macro
N  * @{
N  */
N
N#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
N
N#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
N
N#define READ_BIT(REG, BIT)    ((REG) & (BIT))
N
N#define CLEAR_REG(REG)        ((REG) = (0x0))
N
N#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
N
N#define READ_REG(REG)         ((REG))
N
N#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
N
N/**
N  * @}
N  */
N
N#ifdef __cplusplus
S}
N#endif /* __cplusplus */
N
N#endif /* __STM32F4xx_H */
N
N/**
N  * @}
N  */
N
N  /**
N  * @}
N  */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 54 "..\..\User\bsp\bsp.h" 2
N#include <stdio.h>
L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h" 1
N/* stdio.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.9 */
N/* Copyright (C) Codemist Ltd., 1988-1993                       */
N/* Copyright 1991-1998 ARM Limited. All rights reserved.        */
N
N/*
N * RCS $Revision$
N * Checkin $Date$
N * Revising $Author: sdouglas $
N */
N
N/*
N * stdio.h declares two types, several macros, and many functions for
N * performing input and output. For a discussion on Streams and Files
N * refer to sections 4.9.2 and 4.9.3 in the above ANSI draft, or to a
N * modern textbook on C.
N */
N
N#ifndef __stdio_h
N#define __stdio_h
N#define __ARMCLIB_VERSION 5060037
N
N/*
N * Depending on compiler version __int64 or __INT64_TYPE__ should be defined.
N */
N#ifndef __int64
N  #ifdef __INT64_TYPE__
S    #define __int64 __INT64_TYPE__
N  #endif
N  /* On some architectures neither of these may be defined - if so, fall
N     through and error out if used. */
N#endif
N
N
N#define _ARMABI __declspec(__nothrow)
N
N  #ifndef __STDIO_DECLS
N  #define __STDIO_DECLS
N
N    #undef __CLIBNS
N    #ifdef __cplusplus
S      namespace std {
S      #define __CLIBNS ::std::
S        extern "C" {
N    #else /* ndef __cplusplus */
N      #define __CLIBNS
N    #endif /* ndef __cplusplus */
N
N#if defined(__cplusplus) || !defined(__STRICT_ANSI__) || !defined(__size_t)
X#if 0L || !0L || !0L
N /* always defined in C++ and non-strict C for consistency of debug info */
N  #if __sizeof_ptr == 8
X  #if 4 == 8
S    typedef unsigned long size_t;   /* see <stddef.h> */
N  #else
N    typedef unsigned int size_t;   /* see <stddef.h> */
N  #endif
N  #if !defined(__cplusplus) && defined(__STRICT_ANSI__)
X  #if !0L && 0L
S    #define __size_t 1
N  #endif
N#endif
N
N#undef NULL
N#define NULL 0                   /* see <stddef.h> */
N
N/* ANSI forbids va_list to be defined here */
N/* keep in step with <stdarg.h> and <wchar.h> */
N#if !defined(__va_list) && (defined(__cplusplus) || !defined(__STRICT_ANSI__) || !defined(__va_list_defined))
X#if !0L && (0L || !0L || !0L)
N/* always defined in C++ and non-strict C for consistency of debug info */
N  #ifdef __clang__
S    typedef __builtin_va_list __va_list;
N  #else
N    typedef struct __va_list __va_list;
N  #endif
N  #if !defined(__cplusplus) && defined(__STRICT_ANSI__)
X  #if !0L && 0L
S    #define __va_list_defined 1
N  #endif
N#endif
N
N   /*
N    * If the compiler supports signalling nans as per N965 then it
N    * will define __SUPPORT_SNAN__, in which case a user may define
N    * _WANT_SNAN in order to obtain compliant versions of the printf
N    * and scanf families of functions
N    */
N#if defined(__SUPPORT_SNAN__) && defined(_WANT_SNAN)
X#if 0L && 0L
S#pragma import(__use_snan)
N#endif
N
Ntypedef struct __fpos_t_struct {
N    unsigned __int64 __pos;
N    /*
N     * this structure is equivalent to an mbstate_t, but we're not
N     * allowed to actually define the type name `mbstate_t' within
N     * stdio.h
N     */
N    struct {
N        unsigned int __state1, __state2;
N    } __mbstate;
N} fpos_t;
N   /*
N    * fpos_t is an object capable of recording all information needed to
N    * specify uniquely every position within a file.
N    */
N
N#define _SYS_OPEN 16
N   /* _SYS_OPEN defines a limit on the number of open files that is imposed
N    * by this C library
N    */
N
Ntypedef struct __FILE FILE;
N   /*
N    * FILE is an object capable of recording all information needed to control
N    * a stream, such as its file position indicator, a pointer to its
N    * associated buffer, an error indicator that records whether a read/write
N    * error has occurred and an end-of-file indicator that records whether the
N    * end-of-file has been reached.
N    * Its structure is not made known to library clients.
N    */
N
N#if defined(__STRICT_ANSI__) && !__FILE_INCOMPLETE
X#if 0L && !__FILE_INCOMPLETE
Sstruct __FILE {
S    union {
S        long __FILE_alignment;
S#ifdef __TARGET_ARCH_AARCH64
S        char __FILE_size[136];
S#else /* __TARGET_ARCH_AARCH64 */
S        char __FILE_size[84];
S#endif /* __TARGET_ARCH_AARCH64 */
S    } __FILE_opaque;
S};
S    /*
S     * FILE must be an object type (C99 - 7.19.1) and an object type fully
S     * describes an object [including its static size] (C99 - 6.2.5).
S     * This definition is a placeholder which matches the struct __FILE in
S     * size and alignment as used internally by libc.
S     */
N#endif
N
N
Nextern FILE __stdin, __stdout, __stderr;
Nextern FILE *__aeabi_stdin, *__aeabi_stdout, *__aeabi_stderr;
N
N#if _AEABI_PORTABILITY_LEVEL != 0 || (!defined _AEABI_PORTABILITY_LEVEL && __DEFAULT_AEABI_PORTABILITY_LEVEL != 0)
X#if _AEABI_PORTABILITY_LEVEL != 0 || (!0L && __DEFAULT_AEABI_PORTABILITY_LEVEL != 0)
S#define stdin  (__CLIBNS __aeabi_stdin)
S   /* pointer to a FILE object associated with standard input stream */
S#define stdout (__CLIBNS __aeabi_stdout)
S   /* pointer to a FILE object associated with standard output stream */
S#define stderr (__CLIBNS __aeabi_stderr)
S   /* pointer to a FILE object associated with standard error stream */
Sextern const int __aeabi_IOFBF;
S#define _IOFBF (__CLIBNS __aeabi_IOFBF)
Sextern const int __aeabi_IONBF;
S#define _IONBF (__CLIBNS __aeabi_IONBF)
Sextern const int __aeabi_IOLBF;
S#define _IOLBF (__CLIBNS __aeabi_IOLBF)
Sextern const int __aeabi_BUFSIZ;
S#define BUFSIZ (__CLIBNS __aeabi_BUFSIZ)
Sextern const int __aeabi_FOPEN_MAX;
S#define FOPEN_MAX (__CLIBNS __aeabi_FOPEN_MAX)
Sextern const int __aeabi_TMP_MAX;
S#define TMP_MAX (__CLIBNS __aeabi_TMP_MAX)
Sextern const int __aeabi_FILENAME_MAX;
S#define FILENAME_MAX (__CLIBNS __aeabi_FILENAME_MAX)
Sextern const int __aeabi_L_tmpnam;
S#define L_tmpnam (__CLIBNS __aeabi_L_tmpnam)
N#else
N#define stdin  (&__CLIBNS __stdin)
N   /* pointer to a FILE object associated with standard input stream */
N#define stdout (&__CLIBNS __stdout)
N   /* pointer to a FILE object associated with standard output stream */
N#define stderr (&__CLIBNS __stderr)
N   /* pointer to a FILE object associated with standard error stream */
N
N#define _IOFBF           0x100 /* fully buffered IO */
N#define _IOLBF           0x200 /* line buffered IO */
N#define _IONBF           0x400 /* unbuffered IO */
N
N    /* Various default file IO buffer sizes */
N#define BUFSIZ       (512)  /* system buffer size (as used by setbuf) */
N
N#define FOPEN_MAX _SYS_OPEN
N   /*
N    * an integral constant expression that is the minimum number of files that
N    * this implementation guarantees can be open simultaneously.
N    */
N
N#define FILENAME_MAX 256
N   /*
N    * an integral constant expression that is the size of an array of char
N    * large enough to hold the longest filename string
N    */
N#define L_tmpnam FILENAME_MAX
N   /*
N    * an integral constant expression that is the size of an array of char
N    * large enough to hold a temporary file name string generated by the
N    * tmpnam function.
N    */
N#define TMP_MAX 256
N   /*
N    * an integral constant expression that is the minimum number of unique
N    * file names that shall be generated by the tmpnam function.
N    */
N
N#endif
N
N#define EOF      (-1)
N   /*
N    * negative integral constant, indicates end-of-file, that is, no more input
N    * from a stream.
N    */
N
N#define SEEK_SET 0 /* start of stream (see fseek) */
N#define SEEK_CUR 1 /* current position in stream (see fseek) */
N#define SEEK_END 2 /* end of stream (see fseek) */
N
N    /*
N     * _IOBIN is the flag passed to _sys_write to denote a binary
N     * file.
N     */
N#define _IOBIN            0x04     /* binary stream */
N
N#define __STDIN_BUFSIZ  (64)  /* default stdin buffer size */
N#define __STDOUT_BUFSIZ (64)  /* default stdout buffer size */
N#define __STDERR_BUFSIZ (16)  /* default stderr buffer size */
N
Nextern _ARMABI int remove(const char * /*filename*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int remove(const char *  ) __attribute__((__nonnull__(1)));
N   /*
N    * causes the file whose name is the string pointed to by filename to be
N    * removed. Subsequent attempts to open the file will fail, unless it is
N    * created anew. If the file is open, the behaviour of the remove function
N    * is implementation-defined.
N    * Returns: zero if the operation succeeds, nonzero if it fails.
N    */
Nextern _ARMABI int rename(const char * /*old*/, const char * /*new*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int rename(const char *  , const char *  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * causes the file whose name is the string pointed to by old to be
N    * henceforth known by the name given by the string pointed to by new. The
N    * file named old is effectively removed. If a file named by the string
N    * pointed to by new exists prior to the call of the rename function, the
N    * behaviour is implementation-defined.
N    * Returns: zero if the operation succeeds, nonzero if it fails, in which
N    *          case if the file existed previously it is still known by its
N    *          original name.
N    */
Nextern _ARMABI FILE *tmpfile(void);
Xextern __declspec(__nothrow) FILE *tmpfile(void);
N   /*
N    * creates a temporary binary file that will be automatically removed when
N    * it is closed or at program termination. The file is opened for update.
N    * Returns: a pointer to the stream of the file that it created. If the file
N    *          cannot be created, a null pointer is returned.
N    */
Nextern _ARMABI char *tmpnam(char * /*s*/);
Xextern __declspec(__nothrow) char *tmpnam(char *  );
N   /*
N    * generates a string that is not the same as the name of an existing file.
N    * The tmpnam function generates a different string each time it is called,
N    * up to TMP_MAX times. If it is called more than TMP_MAX times, the
N    * behaviour is implementation-defined.
N    * Returns: If the argument is a null pointer, the tmpnam function leaves
N    *          its result in an internal static object and returns a pointer to
N    *          that object. Subsequent calls to the tmpnam function may modify
N    *          the same object. if the argument is not a null pointer, it is
N    *          assumed to point to an array of at least L_tmpnam characters;
N    *          the tmpnam function writes its result in that array and returns
N    *          the argument as its value.
N    */
N
Nextern _ARMABI int fclose(FILE * /*stream*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int fclose(FILE *  ) __attribute__((__nonnull__(1)));
N   /*
N    * causes the stream pointed to by stream to be flushed and the associated
N    * file to be closed. Any unwritten buffered data for the stream are
N    * delivered to the host environment to be written to the file; any unread
N    * buffered data are discarded. The stream is disassociated from the file.
N    * If the associated buffer was automatically allocated, it is deallocated.
N    * Returns: zero if the stream was succesfully closed, or nonzero if any
N    *          errors were detected or if the stream was already closed.
N    */
Nextern _ARMABI int fflush(FILE * /*stream*/);
Xextern __declspec(__nothrow) int fflush(FILE *  );
N   /*
N    * If the stream points to an output or update stream in which the most
N    * recent operation was output, the fflush function causes any unwritten
N    * data for that stream to be delivered to the host environment to be
N    * written to the file. If the stream points to an input or update stream,
N    * the fflush function undoes the effect of any preceding ungetc operation
N    * on the stream.
N    * Returns: nonzero if a write error occurs.
N    */
Nextern _ARMABI FILE *fopen(const char * __restrict /*filename*/,
Xextern __declspec(__nothrow) FILE *fopen(const char * __restrict  ,
N                           const char * __restrict /*mode*/) __attribute__((__nonnull__(1,2)));
N   /*
N    * opens the file whose name is the string pointed to by filename, and
N    * associates a stream with it.
N    * The argument mode points to a string beginning with one of the following
N    * sequences:
N    * "r"         open text file for reading
N    * "w"         create text file for writing, or truncate to zero length
N    * "a"         append; open text file or create for writing at eof
N    * "rb"        open binary file for reading
N    * "wb"        create binary file for writing, or truncate to zero length
N    * "ab"        append; open binary file or create for writing at eof
N    * "r+"        open text file for update (reading and writing)
N    * "w+"        create text file for update, or truncate to zero length
N    * "a+"        append; open text file or create for update, writing at eof
N    * "r+b"/"rb+" open binary file for update (reading and writing)
N    * "w+b"/"wb+" create binary file for update, or truncate to zero length
N    * "a+b"/"ab+" append; open binary file or create for update, writing at eof
N    *
N    * Opening a file with read mode ('r' as the first character in the mode
N    * argument) fails if the file does not exist or cannot be read.
N    * Opening a file with append mode ('a' as the first character in the mode
N    * argument) causes all subsequent writes to be forced to the current end of
N    * file, regardless of intervening calls to the fseek function. In some
N    * implementations, opening a binary file with append mode ('b' as the
N    * second or third character in the mode argument) may initially position
N    * the file position indicator beyond the last data written, because of the
N    * NUL padding.
N    * When a file is opened with update mode ('+' as the second or third
N    * character in the mode argument), both input and output may be performed
N    * on the associated stream. However, output may not be directly followed
N    * by input without an intervening call to the fflush fuction or to a file
N    * positioning function (fseek, fsetpos, or rewind), and input be not be
N    * directly followed by output without an intervening call to the fflush
N    * fuction or to a file positioning function, unless the input operation
N    * encounters end-of-file. Opening a file with update mode may open or
N    * create a binary stream in some implementations. When opened, a stream
N    * is fully buffered if and only if it does not refer to an interactive
N    * device. The error and end-of-file indicators for the stream are
N    * cleared.
N    * Returns: a pointer to the object controlling the stream. If the open
N    *          operation fails, fopen returns a null pointer.
N    */
Nextern _ARMABI FILE *freopen(const char * __restrict /*filename*/,
Xextern __declspec(__nothrow) FILE *freopen(const char * __restrict  ,
N                    const char * __restrict /*mode*/,
N                    FILE * __restrict /*stream*/) __attribute__((__nonnull__(2,3)));
N   /*
N    * opens the file whose name is the string pointed to by filename and
N    * associates the stream pointed to by stream with it. The mode argument is
N    * used just as in the fopen function.
N    * The freopen function first attempts to close any file that is associated
N    * with the specified stream. Failure to close the file successfully is
N    * ignored. The error and end-of-file indicators for the stream are cleared.
N    * Returns: a null pointer if the operation fails. Otherwise, freopen
N    *          returns the value of the stream.
N    */
Nextern _ARMABI void setbuf(FILE * __restrict /*stream*/,
Xextern __declspec(__nothrow) void setbuf(FILE * __restrict  ,
N                    char * __restrict /*buf*/) __attribute__((__nonnull__(1)));
N   /*
N    * Except that it returns no value, the setbuf function is equivalent to the
N    * setvbuf function invoked with the values _IOFBF for mode and BUFSIZ for
N    * size, or (if buf is a null pointer), with the value _IONBF for mode.
N    * Returns: no value.
N    */
Nextern _ARMABI int setvbuf(FILE * __restrict /*stream*/,
Xextern __declspec(__nothrow) int setvbuf(FILE * __restrict  ,
N                   char * __restrict /*buf*/,
N                   int /*mode*/, size_t /*size*/) __attribute__((__nonnull__(1)));
N   /*
N    * may be used after the stream pointed to by stream has been associated
N    * with an open file but before it is read or written. The argument mode
N    * determines how stream will be buffered, as follows: _IOFBF causes
N    * input/output to be fully buffered; _IOLBF causes output to be line
N    * buffered (the buffer will be flushed when a new-line character is
N    * written, when the buffer is full, or when input is requested); _IONBF
N    * causes input/output to be completely unbuffered. If buf is not the null
N    * pointer, the array it points to may be used instead of an automatically
N    * allocated buffer (the buffer must have a lifetime at least as great as
N    * the open stream, so the stream should be closed before a buffer that has
N    * automatic storage duration is deallocated upon block exit). The argument
N    * size specifies the size of the array. The contents of the array at any
N    * time are indeterminate.
N    * Returns: zero on success, or nonzero if an invalid value is given for
N    *          mode or size, or if the request cannot be honoured.
N    */
N#pragma __printf_args
Nextern _ARMABI int fprintf(FILE * __restrict /*stream*/,
Xextern __declspec(__nothrow) int fprintf(FILE * __restrict  ,
N                    const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2)));
N   /*
N    * writes output to the stream pointed to by stream, under control of the
N    * string pointed to by format that specifies how subsequent arguments are
N    * converted for output. If there are insufficient arguments for the format,
N    * the behaviour is undefined. If the format is exhausted while arguments
N    * remain, the excess arguments are evaluated but otherwise ignored. The
N    * fprintf function returns when the end of the format string is reached.
N    * The format shall be a multibyte character sequence, beginning and ending
N    * in its initial shift state. The format is composed of zero or more
N    * directives: ordinary multibyte characters (not %), which are copied
N    * unchanged to the output stream; and conversion specifiers, each of which
N    * results in fetching zero or more subsequent arguments. Each conversion
N    * specification is introduced by the character %. For a description of the
N    * available conversion specifiers refer to section 4.9.6.1 in the ANSI
N    * draft mentioned at the start of this file or to any modern textbook on C.
N    * The minimum value for the maximum number of characters producable by any
N    * single conversion is at least 509.
N    * Returns: the number of characters transmitted, or a negative value if an
N    *          output error occurred.
N    */
N#pragma __printf_args
Nextern _ARMABI int _fprintf(FILE * __restrict /*stream*/,
Xextern __declspec(__nothrow) int _fprintf(FILE * __restrict  ,
N                     const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2)));
N   /*
N    * is equivalent to fprintf, but does not support floating-point formats.
N    * You can use instead of fprintf to improve code size.
N    * Returns: as fprintf.
N    */
N#pragma __printf_args
Nextern _ARMABI int printf(const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int printf(const char * __restrict  , ...) __attribute__((__nonnull__(1)));
N   /*
N    * is equivalent to fprintf with the argument stdout interposed before the
N    * arguments to printf.
N    * Returns: the number of characters transmitted, or a negative value if an
N    *          output error occurred.
N    */
N#pragma __printf_args
Nextern _ARMABI int _printf(const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int _printf(const char * __restrict  , ...) __attribute__((__nonnull__(1)));
N   /*
N    * is equivalent to printf, but does not support floating-point formats.
N    * You can use instead of printf to improve code size.
N    * Returns: as printf.
N    */
N#pragma __printf_args
Nextern _ARMABI int sprintf(char * __restrict /*s*/, const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int sprintf(char * __restrict  , const char * __restrict  , ...) __attribute__((__nonnull__(1,2)));
N   /*
N    * is equivalent to fprintf, except that the argument s specifies an array
N    * into which the generated output is to be written, rather than to a
N    * stream. A null character is written at the end of the characters written;
N    * it is not counted as part of the returned sum.
N    * Returns: the number of characters written to the array, not counting the
N    *          terminating null character.
N    */
N#pragma __printf_args
Nextern _ARMABI int _sprintf(char * __restrict /*s*/, const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int _sprintf(char * __restrict  , const char * __restrict  , ...) __attribute__((__nonnull__(1,2)));
N   /*
N    * is equivalent to sprintf, but does not support floating-point formats.
N    * You can use instead of sprintf to improve code size.
N    * Returns: as sprintf.
N    */
N
N#pragma __printf_args
Nextern _ARMABI int __ARM_snprintf(char * __restrict /*s*/, size_t /*n*/,
Xextern __declspec(__nothrow) int __ARM_snprintf(char * __restrict  , size_t  ,
N                     const char * __restrict /*format*/, ...) __attribute__((__nonnull__(3)));
N
N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus)
X#if !0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus)
N#pragma __printf_args
Nextern _ARMABI int snprintf(char * __restrict /*s*/, size_t /*n*/,
Xextern __declspec(__nothrow) int snprintf(char * __restrict  , size_t  ,
N                     const char * __restrict /*format*/, ...) __attribute__((__nonnull__(3)));
N   /*
N    * is equivalent to fprintf, except that the argument s specifies an array
N    * into which the generated output is to be written, rather than to a
N    * stream. The argument n specifies the size of the output array, so as to
N    * avoid overflowing the buffer.
N    * A null character is written at the end of the characters written, even
N    * if the formatting was not completed; it is not counted as part of the
N    * returned sum. At most n characters of the output buffer are used,
N    * _including_ the null character.
N    * Returns: the number of characters that would have been written to the
N    *          array, not counting the terminating null character, if the
N    *          array had been big enough. So if the return is >=0 and <n, then
N    *          the entire string was successfully formatted; if the return is
N    *          >=n, the string was truncated (but there is still a null char
N    *          at the end of what was written); if the return is <0, there was
N    *          an error.
N    */
N#endif
N#pragma __printf_args
Nextern _ARMABI int _snprintf(char * __restrict /*s*/, size_t /*n*/,
Xextern __declspec(__nothrow) int _snprintf(char * __restrict  , size_t  ,
N                      const char * __restrict /*format*/, ...) __attribute__((__nonnull__(3)));
N   /*
N    * is equivalent to snprintf, but does not support floating-point formats.
N    * You can use instead of snprintf to improve code size.
N    * Returns: as snprintf.
N    */
N#pragma __scanf_args
Nextern _ARMABI int fscanf(FILE * __restrict /*stream*/,
Xextern __declspec(__nothrow) int fscanf(FILE * __restrict  ,
N                    const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2)));
N   /*
N    * reads input from the stream pointed to by stream, under control of the
N    * string pointed to by format that specifies the admissible input sequences
N    * and how thay are to be converted for assignment, using subsequent
N    * arguments as pointers to the objects to receive the converted input. If
N    * there are insufficient arguments for the format, the behaviour is
N    * undefined. If the format is exhausted while arguments remain, the excess
N    * arguments are evaluated but otherwise ignored.
N    * The format is composed of zero or more directives: one or more
N    * white-space characters; an ordinary character (not %); or a conversion
N    * specification. Each conversion specification is introduced by the
N    * character %. For a description of the available conversion specifiers
N    * refer to section 4.9.6.2 in the ANSI draft mentioned at the start of this
N    * file, or to any modern textbook on C.
N    * If end-of-file is encountered during input, conversion is terminated. If
N    * end-of-file occurs before any characters matching the current directive
N    * have been read (other than leading white space, where permitted),
N    * execution of the current directive terminates with an input failure;
N    * otherwise, unless execution of the current directive is terminated with a
N    * matching failure, execution of the following directive (if any) is
N    * terminated with an input failure.
N    * If conversions terminates on a conflicting input character, the offending
N    * input character is left unread in the input strem. Trailing white space
N    * (including new-line characters) is left unread unless matched by a
N    * directive. The success of literal matches and suppressed asignments is
N    * not directly determinable other than via the %n directive.
N    * Returns: the value of the macro EOF if an input failure occurs before any
N    *          conversion. Otherwise, the fscanf function returns the number of
N    *          input items assigned, which can be fewer than provided for, or
N    *          even zero, in the event of an early conflict between an input
N    *          character and the format.
N    */
N#pragma __scanf_args
Nextern _ARMABI int _fscanf(FILE * __restrict /*stream*/,
Xextern __declspec(__nothrow) int _fscanf(FILE * __restrict  ,
N                     const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2)));
N   /*
N    * is equivalent to fscanf, but does not support floating-point formats.
N    * You can use instead of fscanf to improve code size.
N    * Returns: as fscanf.
N    */
N#pragma __scanf_args
Nextern _ARMABI int scanf(const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int scanf(const char * __restrict  , ...) __attribute__((__nonnull__(1)));
N   /*
N    * is equivalent to fscanf with the argument stdin interposed before the
N    * arguments to scanf.
N    * Returns: the value of the macro EOF if an input failure occurs before any
N    *          conversion. Otherwise, the scanf function returns the number of
N    *          input items assigned, which can be fewer than provided for, or
N    *          even zero, in the event of an early matching failure.
N    */
N#pragma __scanf_args
Nextern _ARMABI int _scanf(const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int _scanf(const char * __restrict  , ...) __attribute__((__nonnull__(1)));
N   /*
N    * is equivalent to scanf, but does not support floating-point formats.
N    * You can use instead of scanf to improve code size.
N    * Returns: as scanf.
N    */
N#pragma __scanf_args
Nextern _ARMABI int sscanf(const char * __restrict /*s*/,
Xextern __declspec(__nothrow) int sscanf(const char * __restrict  ,
N                    const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2)));
N   /*
N    * is equivalent to fscanf except that the argument s specifies a string
N    * from which the input is to be obtained, rather than from a stream.
N    * Reaching the end of the string is equivalent to encountering end-of-file
N    * for the fscanf function.
N    * Returns: the value of the macro EOF if an input failure occurs before any
N    *          conversion. Otherwise, the scanf function returns the number of
N    *          input items assigned, which can be fewer than provided for, or
N    *          even zero, in the event of an early matching failure.
N    */
N#pragma __scanf_args
Nextern _ARMABI int _sscanf(const char * __restrict /*s*/,
Xextern __declspec(__nothrow) int _sscanf(const char * __restrict  ,
N                     const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2)));
N   /*
N    * is equivalent to sscanf, but does not support floating-point formats.
N    * You can use instead of sscanf to improve code size.
N    * Returns: as sscanf.
N    */
N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus)
X#if !0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus)
N/* C99 additions */
Nextern _ARMABI int vfscanf(FILE * __restrict /*stream*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int vfscanf(FILE * __restrict  , const char * __restrict  , __va_list) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI int vscanf(const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int vscanf(const char * __restrict  , __va_list) __attribute__((__nonnull__(1)));
Nextern _ARMABI int vsscanf(const char * __restrict /*s*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int vsscanf(const char * __restrict  , const char * __restrict  , __va_list) __attribute__((__nonnull__(1,2)));
N#endif
Nextern _ARMABI int _vfscanf(FILE * __restrict /*stream*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int _vfscanf(FILE * __restrict  , const char * __restrict  , __va_list) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI int _vscanf(const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int _vscanf(const char * __restrict  , __va_list) __attribute__((__nonnull__(1)));
Nextern _ARMABI int _vsscanf(const char * __restrict /*s*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int _vsscanf(const char * __restrict  , const char * __restrict  , __va_list) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI int __ARM_vsscanf(const char * __restrict /*s*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int __ARM_vsscanf(const char * __restrict  , const char * __restrict  , __va_list) __attribute__((__nonnull__(1,2)));
N
Nextern _ARMABI int vprintf(const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int vprintf(const char * __restrict  , __va_list  ) __attribute__((__nonnull__(1)));
N   /*
N    * is equivalent to printf, with the variable argument list replaced by arg,
N    * which has been initialised by the va_start macro (and possibly subsequent
N    * va_arg calls). The vprintf function does not invoke the va_end function.
N    * Returns: the number of characters transmitted, or a negative value if an
N    *          output error occurred.
N    */
Nextern _ARMABI int _vprintf(const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int _vprintf(const char * __restrict  , __va_list  ) __attribute__((__nonnull__(1)));
N   /*
N    * is equivalent to vprintf, but does not support floating-point formats.
N    * You can use instead of vprintf to improve code size.
N    * Returns: as vprintf.
N    */
Nextern _ARMABI int vfprintf(FILE * __restrict /*stream*/,
Xextern __declspec(__nothrow) int vfprintf(FILE * __restrict  ,
N                    const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1,2)));
N   /*
N    * is equivalent to fprintf, with the variable argument list replaced by
N    * arg, which has been initialised by the va_start macro (and possibly
N    * subsequent va_arg calls). The vfprintf function does not invoke the
N    * va_end function.
N    * Returns: the number of characters transmitted, or a negative value if an
N    *          output error occurred.
N    */
Nextern _ARMABI int vsprintf(char * __restrict /*s*/,
Xextern __declspec(__nothrow) int vsprintf(char * __restrict  ,
N                     const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1,2)));
N   /*
N    * is equivalent to sprintf, with the variable argument list replaced by
N    * arg, which has been initialised by the va_start macro (and possibly
N    * subsequent va_arg calls). The vsprintf function does not invoke the
N    * va_end function.
N    * Returns: the number of characters written in the array, not counting the
N    *          terminating null character.
N    */
Nextern _ARMABI int __ARM_vsnprintf(char * __restrict /*s*/, size_t /*n*/,
Xextern __declspec(__nothrow) int __ARM_vsnprintf(char * __restrict  , size_t  ,
N                     const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(3)));
N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus)
X#if !0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus)
Nextern _ARMABI int vsnprintf(char * __restrict /*s*/, size_t /*n*/,
Xextern __declspec(__nothrow) int vsnprintf(char * __restrict  , size_t  ,
N                     const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(3)));
N   /*
N    * is equivalent to snprintf, with the variable argument list replaced by
N    * arg, which has been initialised by the va_start macro (and possibly
N    * subsequent va_arg calls). The vsprintf function does not invoke the
N    * va_end function.
N    * Returns: the number of characters that would have been written in the
N    *          array, not counting the terminating null character. As
N    *          snprintf.
N    */
N#endif
Nextern _ARMABI int _vsprintf(char * __restrict /*s*/,
Xextern __declspec(__nothrow) int _vsprintf(char * __restrict  ,
N                      const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1,2)));
N   /*
N    * is equivalent to vsprintf, but does not support floating-point formats.
N    * You can use instead of vsprintf to improve code size.
N    * Returns: as vsprintf.
N    */
Nextern _ARMABI int _vfprintf(FILE * __restrict /*stream*/,
Xextern __declspec(__nothrow) int _vfprintf(FILE * __restrict  ,
N                     const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1,2)));
N   /*
N    * is equivalent to vfprintf, but does not support floating-point formats.
N    * You can use instead of vfprintf to improve code size.
N    * Returns: as vfprintf.
N    */
Nextern _ARMABI int _vsnprintf(char * __restrict /*s*/, size_t /*n*/,
Xextern __declspec(__nothrow) int _vsnprintf(char * __restrict  , size_t  ,
N                      const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(3)));
N   /*
N    * is equivalent to vsnprintf, but does not support floating-point formats.
N    * You can use instead of vsnprintf to improve code size.
N    * Returns: as vsnprintf.
N    */
N#if !defined(__STRICT_ANSI__)
X#if !0L
N#pragma __printf_args
Nextern _ARMABI int asprintf(char ** /*strp*/, const char * __restrict /*format*/, ...) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) int asprintf(char **  , const char * __restrict  , ...) __attribute__((__nonnull__(2)));
Nextern _ARMABI int vasprintf(char ** /*strp*/, const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) int vasprintf(char **  , const char * __restrict  , __va_list  ) __attribute__((__nonnull__(2)));
N#endif
N#pragma __printf_args
Nextern _ARMABI int __ARM_asprintf(char ** /*strp*/, const char * __restrict /*format*/, ...) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) int __ARM_asprintf(char **  , const char * __restrict  , ...) __attribute__((__nonnull__(2)));
Nextern _ARMABI int __ARM_vasprintf(char ** /*strp*/, const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) int __ARM_vasprintf(char **  , const char * __restrict  , __va_list  ) __attribute__((__nonnull__(2)));
N   /*
N    * dynamically allocates a buffer of the right size for the
N    * formatted string, and returns it in (*strp). Formal return value
N    * is the same as any other printf variant, except that it returns
N    * -1 if the buffer could not be allocated.
N    *
N    * (The functions with __ARM_ prefixed names are identical to the
N    * ones without, but are available in all compilation modes without
N    * violating user namespace.)
N    */
N
Nextern _ARMABI int fgetc(FILE * /*stream*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int fgetc(FILE *  ) __attribute__((__nonnull__(1)));
N   /*
N    * obtains the next character (if present) as an unsigned char converted to
N    * an int, from the input stream pointed to by stream, and advances the
N    * associated file position indicator (if defined).
N    * Returns: the next character from the input stream pointed to by stream.
N    *          If the stream is at end-of-file, the end-of-file indicator is
N    *          set and fgetc returns EOF. If a read error occurs, the error
N    *          indicator is set and fgetc returns EOF.
N    */
Nextern _ARMABI char *fgets(char * __restrict /*s*/, int /*n*/,
Xextern __declspec(__nothrow) char *fgets(char * __restrict  , int  ,
N                    FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,3)));
N   /*
N    * reads at most one less than the number of characters specified by n from
N    * the stream pointed to by stream into the array pointed to by s. No
N    * additional characters are read after a new-line character (which is
N    * retained) or after end-of-file. A null character is written immediately
N    * after the last character read into the array.
N    * Returns: s if successful. If end-of-file is encountered and no characters
N    *          have been read into the array, the contents of the array remain
N    *          unchanged and a null pointer is returned. If a read error occurs
N    *          during the operation, the array contents are indeterminate and a
N    *          null pointer is returned.
N    */
Nextern _ARMABI int fputc(int /*c*/, FILE * /*stream*/) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) int fputc(int  , FILE *  ) __attribute__((__nonnull__(2)));
N   /*
N    * writes the character specified by c (converted to an unsigned char) to
N    * the output stream pointed to by stream, at the position indicated by the
N    * asociated file position indicator (if defined), and advances the
N    * indicator appropriately. If the file position indicator is not defined,
N    * the character is appended to the output stream.
N    * Returns: the character written. If a write error occurs, the error
N    *          indicator is set and fputc returns EOF.
N    */
Nextern _ARMABI int fputs(const char * __restrict /*s*/, FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int fputs(const char * __restrict  , FILE * __restrict  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * writes the string pointed to by s to the stream pointed to by stream.
N    * The terminating null character is not written.
N    * Returns: EOF if a write error occurs; otherwise it returns a nonnegative
N    *          value.
N    */
Nextern _ARMABI int getc(FILE * /*stream*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int getc(FILE *  ) __attribute__((__nonnull__(1)));
N   /*
N    * is equivalent to fgetc except that it may be implemented as an unsafe
N    * macro (stream may be evaluated more than once, so the argument should
N    * never be an expression with side-effects).
N    * Returns: the next character from the input stream pointed to by stream.
N    *          If the stream is at end-of-file, the end-of-file indicator is
N    *          set and getc returns EOF. If a read error occurs, the error
N    *          indicator is set and getc returns EOF.
N    */
N#ifdef __cplusplus
S    inline int getchar() { return getc(stdin); }
N#else
N    #define getchar() getc(stdin)
N    extern _ARMABI int (getchar)(void);
X    extern __declspec(__nothrow) int (getchar)(void);
N#endif
N   /*
N    * is equivalent to getc with the argument stdin.
N    * Returns: the next character from the input stream pointed to by stdin.
N    *          If the stream is at end-of-file, the end-of-file indicator is
N    *          set and getchar returns EOF. If a read error occurs, the error
N    *          indicator is set and getchar returns EOF.
N    */
Nextern _ARMABI char *gets(char * /*s*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) char *gets(char *  ) __attribute__((__nonnull__(1)));
N   /*
N    * reads characters from the input stream pointed to by stdin into the array
N    * pointed to by s, until end-of-file is encountered or a new-line character
N    * is read. Any new-line character is discarded, and a null character is
N    * written immediately after the last character read into the array.
N    * Returns: s if successful. If end-of-file is encountered and no characters
N    *          have been read into the array, the contents of the array remain
N    *          unchanged and a null pointer is returned. If a read error occurs
N    *          during the operation, the array contents are indeterminate and a
N    *          null pointer is returned.
N    */
Nextern _ARMABI int putc(int /*c*/, FILE * /*stream*/) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) int putc(int  , FILE *  ) __attribute__((__nonnull__(2)));
N   /*
N    * is equivalent to fputc except that it may be implemented as aan unsafe
N    * macro (stream may be evaluated more than once, so the argument should
N    * never be an expression with side-effects).
N    * Returns: the character written. If a write error occurs, the error
N    *          indicator is set and putc returns EOF.
N    */
N#ifdef __cplusplus
S    inline int putchar(int __c) { return putc(__c, stdout); }
N#else
N    #define putchar(c) putc(c, stdout)
N    extern _ARMABI int (putchar)(int /*c*/);
X    extern __declspec(__nothrow) int (putchar)(int  );
N#endif
N   /*
N    * is equivalent to putc with the second argument stdout.
N    * Returns: the character written. If a write error occurs, the error
N    *          indicator is set and putc returns EOF.
N    */
Nextern _ARMABI int puts(const char * /*s*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int puts(const char *  ) __attribute__((__nonnull__(1)));
N   /*
N    * writes the string pointed to by s to the stream pointed to by stdout, and
N    * appends a new-line character to the output. The terminating null
N    * character is not written.
N    * Returns: EOF if a write error occurs; otherwise it returns a nonnegative
N    *          value.
N    */
Nextern _ARMABI int ungetc(int /*c*/, FILE * /*stream*/) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) int ungetc(int  , FILE *  ) __attribute__((__nonnull__(2)));
N   /*
N    * pushes the character specified by c (converted to an unsigned char) back
N    * onto the input stream pointed to by stream. The character will be
N    * returned by the next read on that stream. An intervening call to the
N    * fflush function or to a file positioning function (fseek, fsetpos,
N    * rewind) discards any pushed-back characters. The extern _ARMABIal storage
N    * corresponding to the stream is unchanged.
N    * One character pushback is guaranteed. If the unget function is called too
N    * many times on the same stream without an intervening read or file
N    * positioning operation on that stream, the operation may fail.
N    * If the value of c equals that of the macro EOF, the operation fails and
N    * the input stream is unchanged.
N    * A successful call to the ungetc function clears the end-of-file
N    * indicator. The value of the file position indicator after reading or
N    * discarding all pushed-back characters shall be the same as it was before
N    * the characters were pushed back. For a text stream, the value of the file
N    * position indicator after a successful call to the ungetc function is
N    * unspecified until all pushed-back characters are read or discarded. For a
N    * binary stream, the file position indicator is decremented by each
N    * successful call to the ungetc function; if its value was zero before a
N    * call, it is indeterminate after the call.
N    * Returns: the character pushed back after conversion, or EOF if the
N    *          operation fails.
N    */
N
Nextern _ARMABI size_t fread(void * __restrict /*ptr*/,
Xextern __declspec(__nothrow) size_t fread(void * __restrict  ,
N                    size_t /*size*/, size_t /*nmemb*/, FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,4)));
N   /*
N    * reads into the array pointed to by ptr, up to nmemb members whose size is
N    * specified by size, from the stream pointed to by stream. The file
N    * position indicator (if defined) is advanced by the number of characters
N    * successfully read. If an error occurs, the resulting value of the file
N    * position indicator is indeterminate. If a partial member is read, its
N    * value is indeterminate. The ferror or feof function shall be used to
N    * distinguish between a read error and end-of-file.
N    * Returns: the number of members successfully read, which may be less than
N    *          nmemb if a read error or end-of-file is encountered. If size or
N    *          nmemb is zero, fread returns zero and the contents of the array
N    *          and the state of the stream remain unchanged.
N    */
N
Nextern _ARMABI size_t __fread_bytes_avail(void * __restrict /*ptr*/,
Xextern __declspec(__nothrow) size_t __fread_bytes_avail(void * __restrict  ,
N                    size_t /*count*/, FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,3)));
N   /*
N    * reads into the array pointed to by ptr, up to count characters from the
N    * stream pointed to by stream. The file position indicator (if defined)
N    * is advanced by the number of characters successfully read. If an error
N    * occurs, the resulting value of the file position indicator is
N    * indeterminate. The ferror or feof function shall be used to
N    * distinguish between a read error and end-of-file.  The call will block
N    * only if no characters are available.
N    * Returns: the number of characters successfully read, which may be less than
N    *          count. If count is zero, __fread_bytes_avail returns zero and
N    *          the contents of the array and the state of the stream remain
N    *          unchanged.
N    */
N
Nextern _ARMABI size_t fwrite(const void * __restrict /*ptr*/,
Xextern __declspec(__nothrow) size_t fwrite(const void * __restrict  ,
N                    size_t /*size*/, size_t /*nmemb*/, FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,4)));
N   /*
N    * writes, from the array pointed to by ptr up to nmemb members whose size
N    * is specified by size, to the stream pointed to by stream. The file
N    * position indicator (if defined) is advanced by the number of characters
N    * successfully written. If an error occurs, the resulting value of the file
N    * position indicator is indeterminate.
N    * Returns: the number of members successfully written, which will be less
N    *          than nmemb only if a write error is encountered.
N    */
N
Nextern _ARMABI int fgetpos(FILE * __restrict /*stream*/, fpos_t * __restrict /*pos*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int fgetpos(FILE * __restrict  , fpos_t * __restrict  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * stores the current value of the file position indicator for the stream
N    * pointed to by stream in the object pointed to by pos. The value stored
N    * contains unspecified information usable by the fsetpos function for
N    * repositioning the stream to its position at the time  of the call to the
N    * fgetpos function.
N    * Returns: zero, if successful. Otherwise nonzero is returned and the
N    *          integer expression errno is set to an implementation-defined
N    *          nonzero value.
N    */
Nextern _ARMABI int fseek(FILE * /*stream*/, long int /*offset*/, int /*whence*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int fseek(FILE *  , long int  , int  ) __attribute__((__nonnull__(1)));
N   /*
N    * sets the file position indicator for the stream pointed to by stream.
N    * For a binary stream, the new position is at the signed number of
N    * characters specified by offset away from the point specified by whence.
N    * The specified point is the beginning of the file for SEEK_SET, the
N    * current position in the file for SEEK_CUR, or end-of-file for SEEK_END.
N    * A binary stream need not meaningfully support fseek calls with a whence
N    * value of SEEK_END.
N    * For a text stream, either offset shall be zero, or offset shall be a
N    * value returned by an earlier call to the ftell function on the same
N    * stream and whence shall be SEEK_SET.
N    * The fseek function clears the end-of-file indicator and undoes any
N    * effects of the ungetc function on the same stream. After an fseek call,
N    * the next operation on an update stream may be either input or output.
N    * Returns: nonzero only for a request that cannot be satisfied.
N    */
Nextern _ARMABI int fsetpos(FILE * __restrict /*stream*/, const fpos_t * __restrict /*pos*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int fsetpos(FILE * __restrict  , const fpos_t * __restrict  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * sets  the file position indicator for the stream pointed to by stream
N    * according to the value of the object pointed to by pos, which shall be a
N    * value returned by an earlier call to the fgetpos function on the same
N    * stream.
N    * The fsetpos function clears the end-of-file indicator and undoes any
N    * effects of the ungetc function on the same stream. After an fsetpos call,
N    * the next operation on an update stream may be either input or output.
N    * Returns: zero, if successful. Otherwise nonzero is returned and the
N    *          integer expression errno is set to an implementation-defined
N    *          nonzero value.
N    */
Nextern _ARMABI long int ftell(FILE * /*stream*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) long int ftell(FILE *  ) __attribute__((__nonnull__(1)));
N   /*
N    * obtains the current value of the file position indicator for the stream
N    * pointed to by stream. For a binary stream, the value is the number of
N    * characters from the beginning of the file. For a text stream, the file
N    * position indicator contains unspecified information, usable by the fseek
N    * function for returning the file position indicator to its position at the
N    * time of the ftell call; the difference between two such return values is
N    * not necessarily a meaningful measure of the number of characters written
N    * or read.
N    * Returns: if successful, the current value of the file position indicator.
N    *          On failure, the ftell function returns -1L and sets the integer
N    *          expression errno to an implementation-defined nonzero value.
N    */
Nextern _ARMABI void rewind(FILE * /*stream*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) void rewind(FILE *  ) __attribute__((__nonnull__(1)));
N   /*
N    * sets the file position indicator for the stream pointed to by stream to
N    * the beginning of the file. It is equivalent to
N    *          (void)fseek(stream, 0L, SEEK_SET)
N    * except that the error indicator for the stream is also cleared.
N    * Returns: no value.
N    */
N
Nextern _ARMABI void clearerr(FILE * /*stream*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) void clearerr(FILE *  ) __attribute__((__nonnull__(1)));
N   /*
N    * clears the end-of-file and error indicators for the stream pointed to by
N    * stream. These indicators are cleared only when the file is opened or by
N    * an explicit call to the clearerr function or to the rewind function.
N    * Returns: no value.
N    */
N
Nextern _ARMABI int feof(FILE * /*stream*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int feof(FILE *  ) __attribute__((__nonnull__(1)));
N   /*
N    * tests the end-of-file indicator for the stream pointed to by stream.
N    * Returns: nonzero iff the end-of-file indicator is set for stream.
N    */
Nextern _ARMABI int ferror(FILE * /*stream*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int ferror(FILE *  ) __attribute__((__nonnull__(1)));
N   /*
N    * tests the error indicator for the stream pointed to by stream.
N    * Returns: nonzero iff the error indicator is set for stream.
N    */
Nextern _ARMABI void perror(const char * /*s*/);
Xextern __declspec(__nothrow) void perror(const char *  );
N   /*
N    * maps the error number  in the integer expression errno to an error
N    * message. It writes a sequence of characters to the standard error stream
N    * thus: first (if s is not a null pointer and the character pointed to by
N    * s is not the null character), the string pointed to by s followed by a
N    * colon and a space; then an appropriate error message string followed by
N    * a new-line character. The contents of the error message strings are the
N    * same as those returned by the strerror function with argument errno,
N    * which are implementation-defined.
N    * Returns: no value.
N    */
N
Nextern _ARMABI int _fisatty(FILE * /*stream*/ ) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int _fisatty(FILE *   ) __attribute__((__nonnull__(1)));
N    /* Returns 1 if the stream is tty (stdin), 0 otherwise. Not ANSI compliant.
N     */
N
Nextern _ARMABI void __use_no_semihosting_swi(void);
Xextern __declspec(__nothrow) void __use_no_semihosting_swi(void);
Nextern _ARMABI void __use_no_semihosting(void);
Xextern __declspec(__nothrow) void __use_no_semihosting(void);
N    /*
N     * Referencing either of these symbols will cause a link-time
N     * error if any library functions that use semihosting SWI
N     * calls are also present in the link, i.e. you define it if
N     * you want to make sure you haven't accidentally used any such
N     * SWIs.
N     */
N
N    #ifdef __cplusplus
S        }  /* extern "C" */
S      }  /* namespace std */
N    #endif
N  #endif /* __STDIO_DECLS */
N
N  #if _AEABI_PORTABILITY_LEVEL != 0 && !defined _AEABI_PORTABLE
X  #if _AEABI_PORTABILITY_LEVEL != 0 && !0L
S    #define _AEABI_PORTABLE
N  #endif
N
N  #if defined(__cplusplus) && !defined(__STDIO_NO_EXPORTS)
X  #if 0L && !0L
S    using ::std::size_t;
S    using ::std::fpos_t;
S    using ::std::FILE;
S    using ::std::remove;
S    using ::std::rename;
S    using ::std::tmpfile;
S    using ::std::tmpnam;
S    using ::std::fclose;
S    using ::std::fflush;
S    using ::std::fopen;
S    using ::std::freopen;
S    using ::std::setbuf;
S    using ::std::setvbuf;
S    using ::std::fprintf;
S    using ::std::_fprintf;
S    using ::std::printf;
S    using ::std::_printf;
S    using ::std::sprintf;
S    using ::std::_sprintf;
S    #if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus)
S      using ::std::snprintf;
S      using ::std::vsnprintf;
S      using ::std::vfscanf;
S      using ::std::vscanf;
S      using ::std::vsscanf;
S    #endif
S    using ::std::_snprintf;
S    using ::std::_vsnprintf;
S#if !defined(__STRICT_ANSI__)
S    using ::std::asprintf;
S    using ::std::vasprintf;
S#endif
S    using ::std::__ARM_asprintf;
S    using ::std::__ARM_vasprintf;
S    using ::std::__ARM_vsnprintf;
S    using ::std::__ARM_snprintf;
S    using ::std::__ARM_vsscanf;
S    using ::std::fscanf;
S    using ::std::_fscanf;
S    using ::std::scanf;
S    using ::std::_scanf;
S    using ::std::sscanf;
S    using ::std::_sscanf;
S    using ::std::_vfscanf;
S    using ::std::_vscanf;
S    using ::std::_vsscanf;
S    using ::std::vprintf;
S    using ::std::_vprintf;
S    using ::std::vfprintf;
S    using ::std::_vfprintf;
S    using ::std::vsprintf;
S    using ::std::_vsprintf;
S    using ::std::fgetc;
S    using ::std::fgets;
S    using ::std::fputc;
S    using ::std::fputs;
S    using ::std::getc;
S    using ::std::getchar;
S    using ::std::gets;
S    using ::std::putc;
S    using ::std::putchar;
S    using ::std::puts;
S    using ::std::ungetc;
S    using ::std::fread;
S    using ::std::__fread_bytes_avail;
S    using ::std::fwrite;
S    using ::std::fgetpos;
S    using ::std::fseek;
S    using ::std::fsetpos;
S    using ::std::ftell;
S    using ::std::rewind;
S    using ::std::clearerr;
S    using ::std::feof;
S    using ::std::ferror;
S    using ::std::perror;
S    using ::std::_fisatty;
S    using ::std::__use_no_semihosting_swi;
S    using ::std::__use_no_semihosting;
N  #endif
N
N#endif /* ndef __stdio_h */
N
N/* end of stdio.h */
N
L 55 "..\..\User\bsp\bsp.h" 2
N#include <string.h>
L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h" 1
N/* string.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.11 */
N/* Copyright (C) Codemist Ltd., 1988-1993.                        */
N/* Copyright 1991-1993 ARM Limited. All rights reserved.          */
N/* version 0.04 */
N
N/*
N * RCS $Revision$
N * Checkin $Date$
N */
N
N/*
N * string.h declares one type and several functions, and defines one macro
N * useful for manipulating character arrays and other objects treated as
N * character arrays. Various methods are used for determining the lengths of
N * the arrays, but in all cases a char * or void * argument points to the
N * initial (lowest addresses) character of the array. If an array is written
N * beyond the end of an object, the behaviour is undefined.
N */
N
N#ifndef __string_h
N#define __string_h
N#define __ARMCLIB_VERSION 5060037
N
N#define _ARMABI __declspec(__nothrow)
N
N  #ifndef __STRING_DECLS
N  #define __STRING_DECLS
N
N    #undef __CLIBNS
N
N    #ifdef __cplusplus
S        namespace std {
S        #define __CLIBNS std::
S        extern "C" {
N    #else
N      #define __CLIBNS
N    #endif  /* __cplusplus */
N
N#if defined(__cplusplus) || !defined(__STRICT_ANSI__)
X#if 0L || !0L
N /* unconditional in C++ and non-strict C for consistency of debug info */
N  #if __sizeof_ptr == 8
X  #if 4 == 8
S    typedef unsigned long size_t;   /* see <stddef.h> */
N  #else
N    typedef unsigned int size_t;   /* see <stddef.h> */
N  #endif
N#elif !defined(__size_t)
S  #define __size_t 1
S  #if __sizeof_ptr == 8
S    typedef unsigned long size_t;   /* see <stddef.h> */
S  #else
S    typedef unsigned int size_t;   /* see <stddef.h> */
S  #endif
N#endif
N
N#undef NULL
N#define NULL 0                   /* see <stddef.h> */
N
Nextern _ARMABI void *memcpy(void * __restrict /*s1*/,
Xextern __declspec(__nothrow) void *memcpy(void * __restrict  ,
N                    const void * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2)));
N   /*
N    * copies n characters from the object pointed to by s2 into the object
N    * pointed to by s1. If copying takes place between objects that overlap,
N    * the behaviour is undefined.
N    * Returns: the value of s1.
N    */
Nextern _ARMABI void *memmove(void * /*s1*/,
Xextern __declspec(__nothrow) void *memmove(void *  ,
N                    const void * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2)));
N   /*
N    * copies n characters from the object pointed to by s2 into the object
N    * pointed to by s1. Copying takes place as if the n characters from the
N    * object pointed to by s2 are first copied into a temporary array of n
N    * characters that does not overlap the objects pointed to by s1 and s2,
N    * and then the n characters from the temporary array are copied into the
N    * object pointed to by s1.
N    * Returns: the value of s1.
N    */
Nextern _ARMABI char *strcpy(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) char *strcpy(char * __restrict  , const char * __restrict  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * copies the string pointed to by s2 (including the terminating nul
N    * character) into the array pointed to by s1. If copying takes place
N    * between objects that overlap, the behaviour is undefined.
N    * Returns: the value of s1.
N    */
Nextern _ARMABI char *strncpy(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) char *strncpy(char * __restrict  , const char * __restrict  , size_t  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * copies not more than n characters (characters that follow a null
N    * character are not copied) from the array pointed to by s2 into the array
N    * pointed to by s1. If copying takes place between objects that overlap,
N    * the behaviour is undefined.
N    * Returns: the value of s1.
N    */
N
Nextern _ARMABI char *strcat(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) char *strcat(char * __restrict  , const char * __restrict  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * appends a copy of the string pointed to by s2 (including the terminating
N    * null character) to the end of the string pointed to by s1. The initial
N    * character of s2 overwrites the null character at the end of s1.
N    * Returns: the value of s1.
N    */
Nextern _ARMABI char *strncat(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) char *strncat(char * __restrict  , const char * __restrict  , size_t  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * appends not more than n characters (a null character and characters that
N    * follow it are not appended) from the array pointed to by s2 to the end of
N    * the string pointed to by s1. The initial character of s2 overwrites the
N    * null character at the end of s1. A terminating null character is always
N    * appended to the result.
N    * Returns: the value of s1.
N    */
N
N/*
N * The sign of a nonzero value returned by the comparison functions is
N * determined by the sign of the difference between the values of the first
N * pair of characters (both interpreted as unsigned char) that differ in the
N * objects being compared.
N */
N
Nextern _ARMABI int memcmp(const void * /*s1*/, const void * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int memcmp(const void *  , const void *  , size_t  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * compares the first n characters of the object pointed to by s1 to the
N    * first n characters of the object pointed to by s2.
N    * Returns: an integer greater than, equal to, or less than zero, according
N    *          as the object pointed to by s1 is greater than, equal to, or
N    *          less than the object pointed to by s2.
N    */
Nextern _ARMABI int strcmp(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int strcmp(const char *  , const char *  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * compares the string pointed to by s1 to the string pointed to by s2.
N    * Returns: an integer greater than, equal to, or less than zero, according
N    *          as the string pointed to by s1 is greater than, equal to, or
N    *          less than the string pointed to by s2.
N    */
Nextern _ARMABI int strncmp(const char * /*s1*/, const char * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int strncmp(const char *  , const char *  , size_t  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * compares not more than n characters (characters that follow a null
N    * character are not compared) from the array pointed to by s1 to the array
N    * pointed to by s2.
N    * Returns: an integer greater than, equal to, or less than zero, according
N    *          as the string pointed to by s1 is greater than, equal to, or
N    *          less than the string pointed to by s2.
N    */
Nextern _ARMABI int strcasecmp(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int strcasecmp(const char *  , const char *  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * compares the string pointed to by s1 to the string pointed to by s2,
N    * case-insensitively as defined by the current locale.
N    * Returns: an integer greater than, equal to, or less than zero, according
N    *          as the string pointed to by s1 is greater than, equal to, or
N    *          less than the string pointed to by s2.
N    */
Nextern _ARMABI int strncasecmp(const char * /*s1*/, const char * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int strncasecmp(const char *  , const char *  , size_t  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * compares not more than n characters (characters that follow a null
N    * character are not compared) from the array pointed to by s1 to the array
N    * pointed to by s2, case-insensitively as defined by the current locale.
N    * Returns: an integer greater than, equal to, or less than zero, according
N    *          as the string pointed to by s1 is greater than, equal to, or
N    *          less than the string pointed to by s2.
N    */
Nextern _ARMABI int strcoll(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) int strcoll(const char *  , const char *  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * compares the string pointed to by s1 to the string pointed to by s2, both
N    * interpreted as appropriate to the LC_COLLATE category of the current
N    * locale.
N    * Returns: an integer greater than, equal to, or less than zero, according
N    *          as the string pointed to by s1 is greater than, equal to, or
N    *          less than the string pointed to by s2 when both are interpreted
N    *          as appropriate to the current locale.
N    */
N
Nextern _ARMABI size_t strxfrm(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) size_t strxfrm(char * __restrict  , const char * __restrict  , size_t  ) __attribute__((__nonnull__(2)));
N   /*
N    * transforms the string pointed to by s2 and places the resulting string
N    * into the array pointed to by s1. The transformation function is such that
N    * if the strcmp function is applied to two transformed strings, it returns
N    * a value greater than, equal to or less than zero, corresponding to the
N    * result of the strcoll function applied to the same two original strings.
N    * No more than n characters are placed into the resulting array pointed to
N    * by s1, including the terminating null character. If n is zero, s1 is
N    * permitted to be a null pointer. If copying takes place between objects
N    * that overlap, the behaviour is undefined.
N    * Returns: The length of the transformed string is returned (not including
N    *          the terminating null character). If the value returned is n or
N    *          more, the contents of the array pointed to by s1 are
N    *          indeterminate.
N    */
N
N
N#ifdef __cplusplus
Sextern _ARMABI const void *memchr(const void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1)));
Sextern "C++" void *memchr(void * __s, int __c, size_t __n) __attribute__((__nonnull__(1)));
Sextern "C++" inline void *memchr(void * __s, int __c, size_t __n)
S    { return const_cast<void *>(memchr(const_cast<const void *>(__s), __c, __n)); }
N#else
Nextern _ARMABI void *memchr(const void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) void *memchr(const void *  , int  , size_t  ) __attribute__((__nonnull__(1)));
N#endif
N   /*
N    * locates the first occurence of c (converted to an unsigned char) in the
N    * initial n characters (each interpreted as unsigned char) of the object
N    * pointed to by s.
N    * Returns: a pointer to the located character, or a null pointer if the
N    *          character does not occur in the object.
N    */
N
N#ifdef __cplusplus
Sextern _ARMABI const char *strchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1)));
Sextern "C++" char *strchr(char * __s, int __c) __attribute__((__nonnull__(1)));
Sextern "C++" inline char *strchr(char * __s, int __c)
S    { return const_cast<char *>(strchr(const_cast<const char *>(__s), __c)); }
N#else
Nextern _ARMABI char *strchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) char *strchr(const char *  , int  ) __attribute__((__nonnull__(1)));
N#endif
N   /*
N    * locates the first occurence of c (converted to an char) in the string
N    * pointed to by s (including the terminating null character).
N    * Returns: a pointer to the located character, or a null pointer if the
N    *          character does not occur in the string.
N    */
N
Nextern _ARMABI size_t strcspn(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) size_t strcspn(const char *  , const char *  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * computes the length of the initial segment of the string pointed to by s1
N    * which consists entirely of characters not from the string pointed to by
N    * s2. The terminating null character is not considered part of s2.
N    * Returns: the length of the segment.
N    */
N
N#ifdef __cplusplus
Sextern _ARMABI const char *strpbrk(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2)));
Sextern "C++" char *strpbrk(char * __s1, const char * __s2) __attribute__((__nonnull__(1,2)));
Sextern "C++" inline char *strpbrk(char * __s1, const char * __s2)
S    { return const_cast<char *>(strpbrk(const_cast<const char *>(__s1), __s2)); }
N#else
Nextern _ARMABI char *strpbrk(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) char *strpbrk(const char *  , const char *  ) __attribute__((__nonnull__(1,2)));
N#endif
N   /*
N    * locates the first occurence in the string pointed to by s1 of any
N    * character from the string pointed to by s2.
N    * Returns: returns a pointer to the character, or a null pointer if no
N    *          character form s2 occurs in s1.
N    */
N
N#ifdef __cplusplus
Sextern _ARMABI const char *strrchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1)));
Sextern "C++" char *strrchr(char * __s, int __c) __attribute__((__nonnull__(1)));
Sextern "C++" inline char *strrchr(char * __s, int __c)
S    { return const_cast<char *>(strrchr(const_cast<const char *>(__s), __c)); }
N#else
Nextern _ARMABI char *strrchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) char *strrchr(const char *  , int  ) __attribute__((__nonnull__(1)));
N#endif
N   /*
N    * locates the last occurence of c (converted to a char) in the string
N    * pointed to by s. The terminating null character is considered part of
N    * the string.
N    * Returns: returns a pointer to the character, or a null pointer if c does
N    *          not occur in the string.
N    */
N
Nextern _ARMABI size_t strspn(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) size_t strspn(const char *  , const char *  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * computes the length of the initial segment of the string pointed to by s1
N    * which consists entirely of characters from the string pointed to by S2
N    * Returns: the length of the segment.
N    */
N
N#ifdef __cplusplus
Sextern _ARMABI const char *strstr(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2)));
Sextern "C++" char *strstr(char * __s1, const char * __s2) __attribute__((__nonnull__(1,2)));
Sextern "C++" inline char *strstr(char * __s1, const char * __s2)
S    { return const_cast<char *>(strstr(const_cast<const char *>(__s1), __s2)); }
N#else
Nextern _ARMABI char *strstr(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) char *strstr(const char *  , const char *  ) __attribute__((__nonnull__(1,2)));
N#endif
N   /*
N    * locates the first occurence in the string pointed to by s1 of the
N    * sequence of characters (excluding the terminating null character) in the
N    * string pointed to by s2.
N    * Returns: a pointer to the located string, or a null pointer if the string
N    *          is not found.
N    */
N
Nextern _ARMABI char *strtok(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) char *strtok(char * __restrict  , const char * __restrict  ) __attribute__((__nonnull__(2)));
Nextern _ARMABI char *_strtok_r(char * /*s1*/, const char * /*s2*/, char ** /*ptr*/) __attribute__((__nonnull__(2,3)));
Xextern __declspec(__nothrow) char *_strtok_r(char *  , const char *  , char **  ) __attribute__((__nonnull__(2,3)));
N#ifndef __STRICT_ANSI__
Nextern _ARMABI char *strtok_r(char * /*s1*/, const char * /*s2*/, char ** /*ptr*/) __attribute__((__nonnull__(2,3)));
Xextern __declspec(__nothrow) char *strtok_r(char *  , const char *  , char **  ) __attribute__((__nonnull__(2,3)));
N#endif
N   /*
N    * A sequence of calls to the strtok function breaks the string pointed to
N    * by s1 into a sequence of tokens, each of which is delimited by a
N    * character from the string pointed to by s2. The first call in the
N    * sequence has s1 as its first argument, and is followed by calls with a
N    * null pointer as their first argument. The separator string pointed to by
N    * s2 may be different from call to call.
N    * The first call in the sequence searches for the first character that is
N    * not contained in the current separator string s2. If no such character
N    * is found, then there are no tokens in s1 and the strtok function returns
N    * a null pointer. If such a character is found, it is the start of the
N    * first token.
N    * The strtok function then searches from there for a character that is
N    * contained in the current separator string. If no such character is found,
N    * the current token extends to the end of the string pointed to by s1, and
N    * subsequent searches for a token will fail. If such a character is found,
N    * it is overwritten by a null character, which terminates the current
N    * token. The strtok function saves a pointer to the following character,
N    * from which the next search for a token will start.
N    * Each subsequent call, with a null pointer as the value for the first
N    * argument, starts searching from the saved pointer and behaves as
N    * described above.
N    * Returns: pointer to the first character of a token, or a null pointer if
N    *          there is no token.
N    *
N    * strtok_r() is a common extension which works exactly like
N    * strtok(), but instead of storing its state in a hidden
N    * library variable, requires the user to pass in a pointer to a
N    * char * variable which will be used instead. Any sequence of
N    * calls to strtok_r() passing the same char ** pointer should
N    * behave exactly like the corresponding sequence of calls to
N    * strtok(). This means that strtok_r() can safely be used in
N    * multi-threaded programs, and also that you can tokenise two
N    * strings in parallel.
N    */
N
Nextern _ARMABI void *memset(void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) void *memset(void *  , int  , size_t  ) __attribute__((__nonnull__(1)));
N   /*
N    * copies the value of c (converted to an unsigned char) into each of the
N    * first n charactes of the object pointed to by s.
N    * Returns: the value of s.
N    */
Nextern _ARMABI char *strerror(int /*errnum*/);
Xextern __declspec(__nothrow) char *strerror(int  );
N   /*
N    * maps the error number in errnum to an error message string.
N    * Returns: a pointer to the string, the contents of which are
N    *          implementation-defined. The array pointed to shall not be
N    *          modified by the program, but may be overwritten by a
N    *          subsequent call to the strerror function.
N    */
Nextern _ARMABI size_t strlen(const char * /*s*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) size_t strlen(const char *  ) __attribute__((__nonnull__(1)));
N   /*
N    * computes the length of the string pointed to by s.
N    * Returns: the number of characters that precede the terminating null
N    *          character.
N    */
N
Nextern _ARMABI size_t strlcpy(char * /*dst*/, const char * /*src*/, size_t /*len*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) size_t strlcpy(char *  , const char *  , size_t  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * copies the string src into the string dst, using no more than
N    * len bytes of dst. Always null-terminates dst _within the
N    * length len (i.e. will copy at most len-1 bytes of string plus
N    * a NUL), unless len is actually zero.
N    * 
N    * Return value is the length of the string that _would_ have
N    * been written, i.e. the length of src. Thus, the operation
N    * succeeded without truncation if and only if ret < len;
N    * otherwise, the value in ret tells you how big to make dst if
N    * you decide to reallocate it. (That value does _not_ include
N    * the NUL.)
N    * 
N    * This is a BSD-derived library extension, which we are
N    * permitted to declare in a standard header because ISO defines
N    * function names beginning with 'str' as reserved for future
N    * expansion of <string.h>.
N    */
N
Nextern _ARMABI size_t strlcat(char * /*dst*/, const char * /*src*/, size_t /*len*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) size_t strlcat(char *  , const char *  , size_t  ) __attribute__((__nonnull__(1,2)));
N   /*
N    * concatenates the string src to the string dst, using no more
N    * than len bytes of dst. Always null-terminates dst _within the
N    * length len (i.e. will copy at most len-1 bytes of string plus
N    * a NUL), unless len is actually zero.
N    * 
N    * Return value is the length of the string that _would_ have
N    * been written, i.e. the length of src plus the original length
N    * of dst. Thus, the operation succeeded without truncation if
N    * and only if ret < len; otherwise, the value in ret tells you
N    * how big to make dst if you decide to reallocate it. (That
N    * value does _not_ include the NUL.)
N    * 
N    * If no NUL is encountered within the first len bytes of dst,
N    * then the length of dst is considered to have been equal to
N    * len for the purposes of the return value (as if there were a
N    * NUL at dst[len]). Thus, the return value in this case is len
N    * + strlen(src).
N    * 
N    * This is a BSD-derived library extension, which we are
N    * permitted to declare in a standard header because ISO defines
N    * function names beginning with 'str' as reserved for future
N    * expansion of <string.h>.
N    */
N
Nextern _ARMABI void _membitcpybl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) void _membitcpybl(void *  , const void *  , int  , int  , size_t  ) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI void _membitcpybb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) void _membitcpybb(void *  , const void *  , int  , int  , size_t  ) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI void _membitcpyhl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) void _membitcpyhl(void *  , const void *  , int  , int  , size_t  ) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI void _membitcpyhb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) void _membitcpyhb(void *  , const void *  , int  , int  , size_t  ) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI void _membitcpywl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) void _membitcpywl(void *  , const void *  , int  , int  , size_t  ) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI void _membitcpywb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) void _membitcpywb(void *  , const void *  , int  , int  , size_t  ) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI void _membitmovebl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) void _membitmovebl(void *  , const void *  , int  , int  , size_t  ) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI void _membitmovebb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) void _membitmovebb(void *  , const void *  , int  , int  , size_t  ) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI void _membitmovehl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) void _membitmovehl(void *  , const void *  , int  , int  , size_t  ) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI void _membitmovehb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) void _membitmovehb(void *  , const void *  , int  , int  , size_t  ) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI void _membitmovewl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) void _membitmovewl(void *  , const void *  , int  , int  , size_t  ) __attribute__((__nonnull__(1,2)));
Nextern _ARMABI void _membitmovewb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2)));
Xextern __declspec(__nothrow) void _membitmovewb(void *  , const void *  , int  , int  , size_t  ) __attribute__((__nonnull__(1,2)));
N    /*
N     * Copies or moves a piece of memory from one place to another,
N     * with one-bit granularity. So you can start or finish a copy
N     * part way through a byte, and you can copy between regions
N     * with different alignment within a byte.
N     * 
N     * All these functions have the same prototype: two void *
N     * pointers for destination and source, then two integers
N     * giving the bit offset from those pointers, and finally the
N     * number of bits to copy.
N     * 
N     * Just like memcpy and memmove, the "cpy" functions copy as
N     * fast as they can in the assumption that the memory regions
N     * do not overlap, while the "move" functions cope correctly
N     * with overlap.
N     *
N     * Treating memory as a stream of individual bits requires
N     * defining a convention about what order those bits are
N     * considered to be arranged in. The above functions support
N     * multiple conventions:
N     * 
N     *  - the "bl" functions consider the unit of memory to be the
N     *    byte, and consider the bits within each byte to be
N     *    arranged in little-endian fashion, so that the LSB comes
N     *    first. (For example, membitcpybl(a,b,0,7,1) would copy
N     *    the MSB of the byte at b to the LSB of the byte at a.)
N     * 
N     *  - the "bb" functions consider the unit of memory to be the
N     *    byte, and consider the bits within each byte to be
N     *    arranged in big-endian fashion, so that the MSB comes
N     *    first.
N     * 
N     *  - the "hl" functions consider the unit of memory to be the
N     *    16-bit halfword, and consider the bits within each word
N     *    to be arranged in little-endian fashion.
N     * 
N     *  - the "hb" functions consider the unit of memory to be the
N     *    16-bit halfword, and consider the bits within each word
N     *    to be arranged in big-endian fashion.
N     * 
N     *  - the "wl" functions consider the unit of memory to be the
N     *    32-bit word, and consider the bits within each word to be
N     *    arranged in little-endian fashion.
N     * 
N     *  - the "wb" functions consider the unit of memory to be the
N     *    32-bit word, and consider the bits within each word to be
N     *    arranged in big-endian fashion.
N     */
N
N    #ifdef __cplusplus
S         }  /* extern "C" */
S      }  /* namespace std */
N    #endif /* __cplusplus */
N  #endif /* __STRING_DECLS */
N
N  #ifdef __cplusplus
S    #ifndef __STRING_NO_EXPORTS
S      using ::std::size_t;
S      using ::std::memcpy;
S      using ::std::memmove;
S      using ::std::strcpy;
S      using ::std::strncpy;
S      using ::std::strcat;
S      using ::std::strncat;
S      using ::std::memcmp;
S      using ::std::strcmp;
S      using ::std::strncmp;
S      using ::std::strcasecmp;
S      using ::std::strncasecmp;
S      using ::std::strcoll;
S      using ::std::strxfrm;
S      using ::std::memchr;
S      using ::std::strchr;
S      using ::std::strcspn;
S      using ::std::strpbrk;
S      using ::std::strrchr;
S      using ::std::strspn;
S      using ::std::strstr;
S      using ::std::strtok;
S#ifndef __STRICT_ANSI__
S      using ::std::strtok_r;
S#endif
S      using ::std::_strtok_r;
S      using ::std::memset;
S      using ::std::strerror;
S      using ::std::strlen;
S      using ::std::strlcpy;
S      using ::std::strlcat;
S      using ::std::_membitcpybl;
S      using ::std::_membitcpybb;
S      using ::std::_membitcpyhl;
S      using ::std::_membitcpyhb;
S      using ::std::_membitcpywl;
S      using ::std::_membitcpywb;
S      using ::std::_membitmovebl;
S      using ::std::_membitmovebb;
S      using ::std::_membitmovehl;
S      using ::std::_membitmovehb;
S      using ::std::_membitmovewl;
S      using ::std::_membitmovewb;
S    #endif /* __STRING_NO_EXPORTS */
N  #endif /* __cplusplus */
N
N#endif
N
N/* end of string.h */
N
L 56 "..\..\User\bsp\bsp.h" 2
N#include <stdlib.h>
L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h" 1
N/* stdlib.h: ANSI draft (X3J11 May 88) library header, section 4.10 */
N/* Copyright (C) Codemist Ltd., 1988-1993.                          */
N/* Copyright 1991-1998,2014 ARM Limited. All rights reserved.       */
N/*
N * RCS $Revision$
N * Checkin $Date$
N * Revising $Author: agrant $
N */
N 
N/*
N * stdlib.h declares four types, several general purpose functions,
N * and defines several macros.
N */
N
N#ifndef __stdlib_h
N#define __stdlib_h
N#define __ARMCLIB_VERSION 5060037
N
N#if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__))
X#if 0L || (1L && !0L)
N  /* armclang and non-strict armcc allow 'long long' in system headers */
N  #define __LONGLONG long long
N#else
S  /* strict armcc has '__int64' */
S  #define __LONGLONG __int64
N#endif
N
N#define _ARMABI __declspec(__nothrow)
N#define _ARMABI_PURE __declspec(__nothrow) __attribute__((const))
N#define _ARMABI_NORETURN __declspec(__nothrow) __declspec(__noreturn)
N#define _ARMABI_THROW
N
N  #ifndef __STDLIB_DECLS
N  #define __STDLIB_DECLS
N
N  /*
N   * Some of these declarations are new in C99.  To access them in C++
N   * you can use -D__USE_C99_STDLIB (or -D__USE_C99ALL).
N   */
N  #ifndef __USE_C99_STDLIB
N    #if defined(__USE_C99_ALL) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus)
X    #if 0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus)
N      #define __USE_C99_STDLIB 1
N    #endif
N  #endif
N
N    #undef __CLIBNS
N
N    #ifdef __cplusplus
S      namespace std {
S          #define __CLIBNS ::std::
S          extern "C" {
N    #else
N      #define __CLIBNS
N    #endif  /* __cplusplus */
N
N#if defined(__cplusplus) || !defined(__STRICT_ANSI__)
X#if 0L || !0L
N /* unconditional in C++ and non-strict C for consistency of debug info */
N  #if __sizeof_ptr == 8
X  #if 4 == 8
S    typedef unsigned long size_t;   /* see <stddef.h> */
N  #else
N    typedef unsigned int size_t;   /* see <stddef.h> */
N  #endif
N#elif !defined(__size_t)
S  #define __size_t 1
S  #if __sizeof_ptr == 8
S    typedef unsigned long size_t;   /* see <stddef.h> */
S  #else
S    typedef unsigned int size_t;   /* see <stddef.h> */
S  #endif
N#endif
N
N#undef NULL
N#define NULL 0                   /* see <stddef.h> */
N
N#ifndef __cplusplus  /* wchar_t is a builtin type for C++ */
N  #if !defined(__STRICT_ANSI__)
X  #if !0L
N   /* unconditional in non-strict C for consistency of debug info */
N   #if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4)
X   #if 0L || (0L && __ARM_SIZEOF_WCHAR_T == 4)
S    typedef unsigned int wchar_t; /* see <stddef.h> */
N   #else
N    typedef unsigned short wchar_t; /* see <stddef.h> */
N   #endif
N  #elif !defined(__wchar_t)
S    #define __wchar_t 1
S   #if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4)
S    typedef unsigned int wchar_t; /* see <stddef.h> */
S   #else
S    typedef unsigned short wchar_t; /* see <stddef.h> */
S   #endif
N  #endif
N#endif
N
Ntypedef struct div_t { int quot, rem; } div_t;
N   /* type of the value returned by the div function. */
Ntypedef struct ldiv_t { long int quot, rem; } ldiv_t;
N   /* type of the value returned by the ldiv function. */
N#if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB
X#if !0L || 1
Ntypedef struct lldiv_t { __LONGLONG quot, rem; } lldiv_t;
Xtypedef struct lldiv_t { long long quot, rem; } lldiv_t;
N   /* type of the value returned by the lldiv function. */
N#endif
N
N#ifdef __EXIT_FAILURE
S#  define EXIT_FAILURE __EXIT_FAILURE
S   /*
S    * an integral expression which may be used as an argument to the exit
S    * function to return unsuccessful termination status to the host
S    * environment.
S    */
N#else
N#  define EXIT_FAILURE 1  /* unixoid */
N#endif
N#define EXIT_SUCCESS 0
N   /*
N    * an integral expression which may be used as an argument to the exit
N    * function to return successful termination status to the host
N    * environment.
N    */
N
N   /*
N    * Defining __USE_ANSI_EXAMPLE_RAND at compile time switches to
N    * the example implementation of rand() and srand() provided in
N    * the ANSI C standard. This implementation is very poor, but is
N    * provided for completeness.
N    */
N#ifdef __USE_ANSI_EXAMPLE_RAND
S#define srand _ANSI_srand
S#define rand _ANSI_rand
S#define RAND_MAX 0x7fff
N#else
N#define RAND_MAX 0x7fffffff
N#endif
N   /*
N    * RAND_MAX: an integral constant expression, the value of which
N    * is the maximum value returned by the rand function.
N    */
Nextern _ARMABI int __aeabi_MB_CUR_MAX(void);
Xextern __declspec(__nothrow) int __aeabi_MB_CUR_MAX(void);
N#define MB_CUR_MAX ( __aeabi_MB_CUR_MAX() )
N   /*
N    * a positive integer expression whose value is the maximum number of bytes
N    * in a multibyte character for the extended character set specified by the
N    * current locale (category LC_CTYPE), and whose value is never greater
N    * than MB_LEN_MAX.
N    */
N
N   /*
N    * If the compiler supports signalling nans as per N965 then it
N    * will define __SUPPORT_SNAN__, in which case a user may define
N    * _WANT_SNAN in order to obtain a compliant version of the strtod
N    * family of functions.
N    */
N#if defined(__SUPPORT_SNAN__) && defined(_WANT_SNAN)
X#if 0L && 0L
S#pragma import(__use_snan)
N#endif
N
Nextern _ARMABI double atof(const char * /*nptr*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) double atof(const char *  ) __attribute__((__nonnull__(1)));
N   /*
N    * converts the initial part of the string pointed to by nptr to double
N    * representation.
N    * Returns: the converted value.
N    */
Nextern _ARMABI int atoi(const char * /*nptr*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int atoi(const char *  ) __attribute__((__nonnull__(1)));
N   /*
N    * converts the initial part of the string pointed to by nptr to int
N    * representation.
N    * Returns: the converted value.
N    */
Nextern _ARMABI long int atol(const char * /*nptr*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) long int atol(const char *  ) __attribute__((__nonnull__(1)));
N   /*
N    * converts the initial part of the string pointed to by nptr to long int
N    * representation.
N    * Returns: the converted value.
N    */
N#if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB
X#if !0L || 1
Nextern _ARMABI __LONGLONG atoll(const char * /*nptr*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) long long atoll(const char *  ) __attribute__((__nonnull__(1)));
N   /*
N    * converts the initial part of the string pointed to by nptr to
N    * long long int representation.
N    * Returns: the converted value.
N    */
N#endif
N
Nextern _ARMABI double strtod(const char * __restrict /*nptr*/, char ** __restrict /*endptr*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) double strtod(const char * __restrict  , char ** __restrict  ) __attribute__((__nonnull__(1)));
N   /*
N    * converts the initial part of the string pointed to by nptr to double
N    * representation. First it decomposes the input string into three parts:
N    * an initial, possibly empty, sequence of white-space characters (as
N    * specified by the isspace function), a subject sequence resembling a
N    * floating point constant; and a final string of one or more unrecognised
N    * characters, including the terminating null character of the input string.
N    * Then it attempts to convert the subject sequence to a floating point
N    * number, and returns the result. A pointer to the final string is stored
N    * in the object pointed to by endptr, provided that endptr is not a null
N    * pointer.
N    * Returns: the converted value if any. If no conversion could be performed,
N    *          zero is returned. If the correct value is outside the range of
N    *          representable values, plus or minus HUGE_VAL is returned
N    *          (according to the sign of the value), and the value of the macro
N    *          ERANGE is stored in errno. If the correct value would cause
N    *          underflow, zero is returned and the value of the macro ERANGE is
N    *          stored in errno.
N    */
N#if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB
X#if !0L || 1
Nextern _ARMABI float strtof(const char * __restrict /*nptr*/, char ** __restrict /*endptr*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) float strtof(const char * __restrict  , char ** __restrict  ) __attribute__((__nonnull__(1)));
Nextern _ARMABI long double strtold(const char * __restrict /*nptr*/, char ** __restrict /*endptr*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) long double strtold(const char * __restrict  , char ** __restrict  ) __attribute__((__nonnull__(1)));
N   /*
N    * same as strtod, but return float and long double respectively.
N    */
N#endif
Nextern _ARMABI long int strtol(const char * __restrict /*nptr*/,
Xextern __declspec(__nothrow) long int strtol(const char * __restrict  ,
N                        char ** __restrict /*endptr*/, int /*base*/) __attribute__((__nonnull__(1)));
N   /*
N    * converts the initial part of the string pointed to by nptr to long int
N    * representation. First it decomposes the input string into three parts:
N    * an initial, possibly empty, sequence of white-space characters (as
N    * specified by the isspace function), a subject sequence resembling an
N    * integer represented in some radix determined by the value of base, and a
N    * final string of one or more unrecognised characters, including the
N    * terminating null character of the input string. Then it attempts to
N    * convert the subject sequence to an integer, and returns the result.
N    * If the value of base is 0, the expected form of the subject sequence is
N    * that of an integer constant (described in ANSI Draft, section 3.1.3.2),
N    * optionally preceded by a '+' or '-' sign, but not including an integer
N    * suffix. If the value of base is between 2 and 36, the expected form of
N    * the subject sequence is a sequence of letters and digits representing an
N    * integer with the radix specified by base, optionally preceded by a plus
N    * or minus sign, but not including an integer suffix. The letters from a
N    * (or A) through z (or Z) are ascribed the values 10 to 35; only letters
N    * whose ascribed values are less than that of the base are permitted. If
N    * the value of base is 16, the characters 0x or 0X may optionally precede
N    * the sequence of letters and digits following the sign if present.
N    * A pointer to the final string is stored in the object
N    * pointed to by endptr, provided that endptr is not a null pointer.
N    * Returns: the converted value if any. If no conversion could be performed,
N    *          zero is returned and nptr is stored in *endptr.
N    *          If the correct value is outside the range of
N    *          representable values, LONG_MAX or LONG_MIN is returned
N    *          (according to the sign of the value), and the value of the
N    *          macro ERANGE is stored in errno.
N    */
Nextern _ARMABI unsigned long int strtoul(const char * __restrict /*nptr*/,
Xextern __declspec(__nothrow) unsigned long int strtoul(const char * __restrict  ,
N                                       char ** __restrict /*endptr*/, int /*base*/) __attribute__((__nonnull__(1)));
N   /*
N    * converts the initial part of the string pointed to by nptr to unsigned
N    * long int representation. First it decomposes the input string into three
N    * parts: an initial, possibly empty, sequence of white-space characters (as
N    * determined by the isspace function), a subject sequence resembling an
N    * unsigned integer represented in some radix determined by the value of
N    * base, and a final string of one or more unrecognised characters,
N    * including the terminating null character of the input string. Then it
N    * attempts to convert the subject sequence to an unsigned integer, and
N    * returns the result. If the value of base is zero, the expected form of
N    * the subject sequence is that of an integer constant (described in ANSI
N    * Draft, section 3.1.3.2), optionally preceded by a '+' or '-' sign, but
N    * not including an integer suffix. If the value of base is between 2 and
N    * 36, the expected form of the subject sequence is a sequence of letters
N    * and digits representing an integer with the radix specified by base,
N    * optionally preceded by a '+' or '-' sign, but not including an integer
N    * suffix. The letters from a (or A) through z (or Z) stand for the values
N    * 10 to 35; only letters whose ascribed values are less than that of the
N    * base are permitted. If the value of base is 16, the characters 0x or 0X
N    * may optionally precede the sequence of letters and digits following the
N    * sign, if present. A pointer to the final string is stored in the object
N    * pointed to by endptr, provided that endptr is not a null pointer.
N    * Returns: the converted value if any. If no conversion could be performed,
N    *          zero is returned and nptr is stored in *endptr.
N    *          If the correct value is outside the range of
N    *          representable values, ULONG_MAX is returned, and the value of
N    *          the macro ERANGE is stored in errno.
N    */
N
N/* C90 reserves all names beginning with 'str' */
Nextern _ARMABI __LONGLONG strtoll(const char * __restrict /*nptr*/,
Xextern __declspec(__nothrow) long long strtoll(const char * __restrict  ,
N                                  char ** __restrict /*endptr*/, int /*base*/)
N                          __attribute__((__nonnull__(1)));
N   /*
N    * as strtol but returns a long long int value.  If the correct value is
N    * outside the range of representable values,  LLONG_MAX or LLONG_MIN is
N    * returned (according to the sign of the value), and the value of the
N    * macro ERANGE is stored in errno.
N    */
Nextern _ARMABI unsigned __LONGLONG strtoull(const char * __restrict /*nptr*/,
Xextern __declspec(__nothrow) unsigned long long strtoull(const char * __restrict  ,
N                                            char ** __restrict /*endptr*/, int /*base*/)
N                                   __attribute__((__nonnull__(1)));
N   /*
N    * as strtoul but returns an unsigned long long int value.  If the correct
N    * value is outside the range of representable values, ULLONG_MAX is returned,
N    * and the value of the macro ERANGE is stored in errno.
N    */
N
Nextern _ARMABI int rand(void);
Xextern __declspec(__nothrow) int rand(void);
N   /*
N    * Computes a sequence of pseudo-random integers in the range 0 to RAND_MAX.
N    * Uses an additive generator (Mitchell & Moore) of the form:
N    *   Xn = (X[n-24] + X[n-55]) MOD 2^31
N    * This is described in section 3.2.2 of Knuth, vol 2. It's period is
N    * in excess of 2^55 and its randomness properties, though unproven, are
N    * conjectured to be good. Empirical testing since 1958 has shown no flaws.
N    * Returns: a pseudo-random integer.
N    */
Nextern _ARMABI void srand(unsigned int /*seed*/);
Xextern __declspec(__nothrow) void srand(unsigned int  );
N   /*
N    * uses its argument as a seed for a new sequence of pseudo-random numbers
N    * to be returned by subsequent calls to rand. If srand is then called with
N    * the same seed value, the sequence of pseudo-random numbers is repeated.
N    * If rand is called before any calls to srand have been made, the same
N    * sequence is generated as when srand is first called with a seed value
N    * of 1.
N    */
N
Nstruct _rand_state { int __x[57]; };
Nextern _ARMABI int _rand_r(struct _rand_state *);
Xextern __declspec(__nothrow) int _rand_r(struct _rand_state *);
Nextern _ARMABI void _srand_r(struct _rand_state *, unsigned int);
Xextern __declspec(__nothrow) void _srand_r(struct _rand_state *, unsigned int);
Nstruct _ANSI_rand_state { int __x[1]; };
Nextern _ARMABI int _ANSI_rand_r(struct _ANSI_rand_state *);
Xextern __declspec(__nothrow) int _ANSI_rand_r(struct _ANSI_rand_state *);
Nextern _ARMABI void _ANSI_srand_r(struct _ANSI_rand_state *, unsigned int);
Xextern __declspec(__nothrow) void _ANSI_srand_r(struct _ANSI_rand_state *, unsigned int);
N   /*
N    * Re-entrant variants of both flavours of rand, which operate on
N    * an explicitly supplied state buffer.
N    */
N
Nextern _ARMABI void *calloc(size_t /*nmemb*/, size_t /*size*/);
Xextern __declspec(__nothrow) void *calloc(size_t  , size_t  );
N   /*
N    * allocates space for an array of nmemb objects, each of whose size is
N    * 'size'. The space is initialised to all bits zero.
N    * Returns: either a null pointer or a pointer to the allocated space.
N    */
Nextern _ARMABI void free(void * /*ptr*/);
Xextern __declspec(__nothrow) void free(void *  );
N   /*
N    * causes the space pointed to by ptr to be deallocated (i.e., made
N    * available for further allocation). If ptr is a null pointer, no action
N    * occurs. Otherwise, if ptr does not match a pointer earlier returned by
N    * calloc, malloc or realloc or if the space has been deallocated by a call
N    * to free or realloc, the behaviour is undefined.
N    */
Nextern _ARMABI void *malloc(size_t /*size*/);
Xextern __declspec(__nothrow) void *malloc(size_t  );
N   /*
N    * allocates space for an object whose size is specified by 'size' and whose
N    * value is indeterminate.
N    * Returns: either a null pointer or a pointer to the allocated space.
N    */
Nextern _ARMABI void *realloc(void * /*ptr*/, size_t /*size*/);
Xextern __declspec(__nothrow) void *realloc(void *  , size_t  );
N   /*
N    * changes the size of the object pointed to by ptr to the size specified by
N    * size. The contents of the object shall be unchanged up to the lesser of
N    * the new and old sizes. If the new size is larger, the value of the newly
N    * allocated portion of the object is indeterminate. If ptr is a null
N    * pointer, the realloc function behaves like a call to malloc for the
N    * specified size. Otherwise, if ptr does not match a pointer earlier
N    * returned by calloc, malloc or realloc, or if the space has been
N    * deallocated by a call to free or realloc, the behaviour is undefined.
N    * If the space cannot be allocated, the object pointed to by ptr is
N    * unchanged. If size is zero and ptr is not a null pointer, the object it
N    * points to is freed.
N    * Returns: either a null pointer or a pointer to the possibly moved
N    *          allocated space.
N    */
N#if !defined(__STRICT_ANSI__)
X#if !0L
Nextern _ARMABI int posix_memalign(void ** /*ret*/, size_t /*alignment*/, size_t /*size*/);
Xextern __declspec(__nothrow) int posix_memalign(void **  , size_t  , size_t  );
N   /*
N    * allocates space for an object of size 'size', aligned to a
N    * multiple of 'alignment' (which must be a power of two and at
N    * least 4).
N    *
N    * On success, a pointer to the allocated object is stored in
N    * *ret, and zero is returned. On failure, the return value is
N    * either ENOMEM (allocation failed because no suitable piece of
N    * memory was available) or EINVAL (the 'alignment' parameter was
N    * invalid).
N    */
N#endif
Ntypedef int (*__heapprt)(void *, char const *, ...);
Nextern _ARMABI void __heapstats(int (* /*dprint*/)(void * /*param*/,
Xextern __declspec(__nothrow) void __heapstats(int (*  )(void *  ,
N                                           char const * /*format*/, ...),
N                        void * /*param*/) __attribute__((__nonnull__(1)));
N   /*
N    * reports current heap statistics (eg. number of free blocks in
N    * the free-list). Output is as implementation-defined free-form
N    * text, provided via the dprint function. `param' gives an
N    * extra data word to pass to dprint. You can call
N    * __heapstats(fprintf,stdout) by casting fprintf to the above
N    * function type; the typedef `__heapprt' is provided for this
N    * purpose.
N    *
N    * `dprint' will not be called while the heap is being examined,
N    * so it can allocate memory itself without trouble.
N    */
Nextern _ARMABI int __heapvalid(int (* /*dprint*/)(void * /*param*/,
Xextern __declspec(__nothrow) int __heapvalid(int (*  )(void *  ,
N                                           char const * /*format*/, ...),
N                       void * /*param*/, int /*verbose*/) __attribute__((__nonnull__(1)));
N   /*
N    * performs a consistency check on the heap. Errors are reported
N    * through dprint, like __heapstats. If `verbose' is nonzero,
N    * full diagnostic information on the heap state is printed out.
N    *
N    * This routine probably won't work if the heap isn't a
N    * contiguous chunk (for example, if __user_heap_extend has been
N    * overridden).
N    *
N    * `dprint' may be called while the heap is being examined or
N    * even in an invalid state, so it must perform no memory
N    * allocation. In particular, if `dprint' calls (or is) a stdio
N    * function, the stream it outputs to must already have either
N    * been written to or been setvbuf'ed, or else the system will
N    * allocate buffer space for it on the first call to dprint.
N    */
Nextern _ARMABI_NORETURN void abort(void);
Xextern __declspec(__nothrow) __declspec(__noreturn) void abort(void);
N   /*
N    * causes abnormal program termination to occur, unless the signal SIGABRT
N    * is being caught and the signal handler does not return. Whether open
N    * output streams are flushed or open streams are closed or temporary
N    * files removed is implementation-defined.
N    * An implementation-defined form of the status 'unsuccessful termination'
N    * is returned to the host environment by means of a call to
N    * raise(SIGABRT).
N    */
N
Nextern _ARMABI int atexit(void (* /*func*/)(void)) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) int atexit(void (*  )(void)) __attribute__((__nonnull__(1)));
N   /*
N    * registers the function pointed to by func, to be called without its
N    * arguments at normal program termination. It is possible to register at
N    * least 32 functions.
N    * Returns: zero if the registration succeeds, nonzero if it fails.
N    */
N#if defined(__EDG__) && !defined(__GNUC__)
X#if 1L && !0L
N#define __LANGUAGE_LINKAGE_CHANGES_FUNCTION_TYPE
N#endif
N#if defined(__cplusplus) && defined(__LANGUAGE_LINKAGE_CHANGES_FUNCTION_TYPE) 
X#if 0L && 1L 
S    /* atexit that takes a ptr to a function with C++ linkage 
S     * but not in GNU mode  
S     */
S    typedef void (* __C_exitfuncptr)();
S    extern "C++"
S    inline int atexit(void (* __func)()) {
S      return atexit((__C_exitfuncptr)__func);
S    }
N#endif
N
N
Nextern _ARMABI_NORETURN void exit(int /*status*/);
Xextern __declspec(__nothrow) __declspec(__noreturn) void exit(int  );
N   /*
N    * causes normal program termination to occur. If more than one call to the
N    * exit function is executed by a program, the behaviour is undefined.
N    * First, all functions registered by the atexit function are called, in the
N    * reverse order of their registration.
N    * Next, all open output streams are flushed, all open streams are closed,
N    * and all files created by the tmpfile function are removed.
N    * Finally, control is returned to the host environment. If the value of
N    * status is zero or EXIT_SUCCESS, an implementation-defined form of the
N    * status 'successful termination' is returned. If the value of status is
N    * EXIT_FAILURE, an implementation-defined form of the status
N    * 'unsuccessful termination' is returned. Otherwise the status returned
N    * is implementation-defined.
N    */
N
Nextern _ARMABI_NORETURN void _Exit(int /*status*/);
Xextern __declspec(__nothrow) __declspec(__noreturn) void _Exit(int  );
N   /*
N    * causes normal program termination to occur. No functions registered
N    * by the atexit function are called.
N    * In this implementation, all open output streams are flushed, all
N    * open streams are closed, and all files created by the tmpfile function
N    * are removed.
N    * Control is returned to the host environment. The status returned to
N    * the host environment is determined in the same way as for 'exit'.
N    */     
N
Nextern _ARMABI char *getenv(const char * /*name*/) __attribute__((__nonnull__(1)));
Xextern __declspec(__nothrow) char *getenv(const char *  ) __attribute__((__nonnull__(1)));
N   /*
N    * searches the environment list, provided by the host environment, for a
N    * string that matches the string pointed to by name. The set of environment
N    * names and the method for altering the environment list are
N    * implementation-defined.
N    * Returns: a pointer to a string associated with the matched list member.
N    *          The array pointed to shall not be modified by the program, but
N    *          may be overwritten by a subsequent call to the getenv function.
N    *          If the specified name cannot be found, a null pointer is
N    *          returned.
N    */
N
Nextern _ARMABI int  system(const char * /*string*/);
Xextern __declspec(__nothrow) int  system(const char *  );
N   /*
N    * passes the string pointed to by string to the host environment to be
N    * executed by a command processor in an implementation-defined manner.
N    * A null pointer may be used for string, to inquire whether a command
N    * processor exists.
N    *
N    * Returns: If the argument is a null pointer, the system function returns
N    *          non-zero only if a command processor is available. If the
N    *          argument is not a null pointer, the system function returns an
N    *          implementation-defined value.
N    */
N
Nextern _ARMABI_THROW void *bsearch(const void * /*key*/, const void * /*base*/,
Xextern  void *bsearch(const void *  , const void *  ,
N              size_t /*nmemb*/, size_t /*size*/,
N              int (* /*compar*/)(const void *, const void *)) __attribute__((__nonnull__(1,2,5)));
N   /*
N    * searches an array of nmemb objects, the initial member of which is
N    * pointed to by base, for a member that matches the object pointed to by
N    * key. The size of each member of the array is specified by size.
N    * The contents of the array shall be in ascending sorted order according to
N    * a comparison function pointed to by compar, which is called with two
N    * arguments that point to the key object and to an array member, in that
N    * order. The function shall return an integer less than, equal to, or
N    * greater than zero if the key object is considered, respectively, to be
N    * less than, to match, or to be greater than the array member.
N    * Returns: a pointer to a matching member of the array, or a null pointer
N    *          if no match is found. If two members compare as equal, which
N    *          member is matched is unspecified.
N    */
N#if defined(__cplusplus) && defined(__LANGUAGE_LINKAGE_CHANGES_FUNCTION_TYPE)
X#if 0L && 1L
S    /* bsearch that takes a ptr to a function with C++ linkage 
S     * but not in GNU mode
S     */
S    typedef int (* __C_compareprocptr)(const void *, const void *);
S    extern "C++"
S    void *bsearch(const void * __key, const void * __base,
S              size_t __nmemb, size_t __size,
S              int (* __compar)(const void *, const void *)) __attribute__((__nonnull__(1,2,5)));
S    extern "C++"
S    inline void *bsearch(const void * __key, const void * __base,
S              size_t __nmemb, size_t __size,
S              int (* __compar)(const void *, const void *)) {
S      return bsearch(__key, __base, __nmemb, __size, (__C_compareprocptr)__compar);
S    }
N#endif
N
N
Nextern _ARMABI_THROW void qsort(void * /*base*/, size_t /*nmemb*/, size_t /*size*/,
Xextern  void qsort(void *  , size_t  , size_t  ,
N           int (* /*compar*/)(const void *, const void *)) __attribute__((__nonnull__(1,4)));
N   /*
N    * sorts an array of nmemb objects, the initial member of which is pointed
N    * to by base. The size of each object is specified by size.
N    * The contents of the array shall be in ascending order according to a
N    * comparison function pointed to by compar, which is called with two
N    * arguments that point to the objects being compared. The function shall
N    * return an integer less than, equal to, or greater than zero if the first
N    * argument is considered to be respectively less than, equal to, or greater
N    * than the second. If two members compare as equal, their order in the
N    * sorted array is unspecified.
N    */
N
N#if defined(__cplusplus) && defined(__LANGUAGE_LINKAGE_CHANGES_FUNCTION_TYPE)
X#if 0L && 1L
S    /* qsort that takes a ptr to a function with C++ linkage 
S     * but not in GNU mode
S     */    
S    extern "C++"
S    void qsort(void * __base, size_t __nmemb, size_t __size,
S               int (* __compar)(const void *, const void *)) __attribute__((__nonnull__(1,4)));
S    extern "C++"
S    inline void qsort(void * __base, size_t __nmemb, size_t __size,
S                      int (* __compar)(const void *, const void *)) {
S      qsort(__base, __nmemb, __size, (__C_compareprocptr)__compar);
S    }
N#endif
N
Nextern _ARMABI_PURE int abs(int /*j*/);
Xextern __declspec(__nothrow) __attribute__((const)) int abs(int  );
N   /*
N    * computes the absolute value of an integer j. If the result cannot be
N    * represented, the behaviour is undefined.
N    * Returns: the absolute value.
N    */
N
Nextern _ARMABI_PURE div_t div(int /*numer*/, int /*denom*/);
Xextern __declspec(__nothrow) __attribute__((const)) div_t div(int  , int  );
N   /*
N    * computes the quotient and remainder of the division of the numerator
N    * numer by the denominator denom. If the division is inexact, the resulting
N    * quotient is the integer of lesser magnitude that is the nearest to the
N    * algebraic quotient. If the result cannot be represented, the behaviour is
N    * undefined; otherwise, quot * denom + rem shall equal numer.
N    * Returns: a structure of type div_t, comprising both the quotient and the
N    *          remainder. the structure shall contain the following members,
N    *          in either order.
N    *          int quot; int rem;
N    */
Nextern _ARMABI_PURE long int labs(long int /*j*/);
Xextern __declspec(__nothrow) __attribute__((const)) long int labs(long int  );
N   /*
N    * computes the absolute value of an long integer j. If the result cannot be
N    * represented, the behaviour is undefined.
N    * Returns: the absolute value.
N    */
N#ifdef __cplusplus
S   extern "C++" inline _ARMABI_PURE long abs(long int x) { return labs(x); }
N#endif
N
Nextern _ARMABI_PURE ldiv_t ldiv(long int /*numer*/, long int /*denom*/);
Xextern __declspec(__nothrow) __attribute__((const)) ldiv_t ldiv(long int  , long int  );
N   /*
N    * computes the quotient and remainder of the division of the numerator
N    * numer by the denominator denom. If the division is inexact, the sign of
N    * the resulting quotient is that of the algebraic quotient, and the
N    * magnitude of the resulting quotient is the largest integer less than the
N    * magnitude of the algebraic quotient. If the result cannot be represented,
N    * the behaviour is undefined; otherwise, quot * denom + rem shall equal
N    * numer.
N    * Returns: a structure of type ldiv_t, comprising both the quotient and the
N    *          remainder. the structure shall contain the following members,
N    *          in either order.
N    *          long int quot; long int rem;
N    */
N#ifdef __cplusplus
S   extern "C++" inline _ARMABI_PURE ldiv_t div(long int __numer, long int __denom) {
S       return ldiv(__numer, __denom);
S   }
N#endif
N
N#if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB
X#if !0L || 1
Nextern _ARMABI_PURE __LONGLONG llabs(__LONGLONG /*j*/);
Xextern __declspec(__nothrow) __attribute__((const)) long long llabs(long long  );
N   /*
N    * computes the absolute value of a long long integer j. If the
N    * result cannot be represented, the behaviour is undefined.
N    * Returns: the absolute value.
N    */
N#ifdef __cplusplus
S   extern "C++" inline _ARMABI_PURE __LONGLONG abs(__LONGLONG x) { return llabs(x); }
N#endif
N
Nextern _ARMABI_PURE lldiv_t lldiv(__LONGLONG /*numer*/, __LONGLONG /*denom*/);
Xextern __declspec(__nothrow) __attribute__((const)) lldiv_t lldiv(long long  , long long  );
N   /*
N    * computes the quotient and remainder of the division of the numerator
N    * numer by the denominator denom. If the division is inexact, the sign of
N    * the resulting quotient is that of the algebraic quotient, and the
N    * magnitude of the resulting quotient is the largest integer less than the
N    * magnitude of the algebraic quotient. If the result cannot be represented,
N    * the behaviour is undefined; otherwise, quot * denom + rem shall equal
N    * numer.
N    * Returns: a structure of type lldiv_t, comprising both the quotient and the
N    *          remainder. the structure shall contain the following members,
N    *          in either order.
N    *          long long quot; long long rem;
N    */
N#ifdef __cplusplus
S   extern "C++" inline _ARMABI_PURE lldiv_t div(__LONGLONG __numer, __LONGLONG __denom) {
S       return lldiv(__numer, __denom);
S   }
N#endif
N#endif
N
N#if !(__ARM_NO_DEPRECATED_FUNCTIONS)
N/*
N * ARM real-time divide functions for guaranteed performance
N */
Ntypedef struct __sdiv32by16 { int quot, rem; } __sdiv32by16;
Ntypedef struct __udiv32by16 { unsigned int quot, rem; } __udiv32by16;
N   /* used int so that values return in separate regs, although 16-bit */
Ntypedef struct __sdiv64by32 { int rem, quot; } __sdiv64by32;
N
N__value_in_regs extern _ARMABI_PURE __sdiv32by16 __rt_sdiv32by16(
X__value_in_regs extern __declspec(__nothrow) __attribute__((const)) __sdiv32by16 __rt_sdiv32by16(
N     int /*numer*/,
N     short int /*denom*/);
N   /*
N    * Signed divide: (16-bit quot), (16-bit rem) = (32-bit) / (16-bit)
N    */
N__value_in_regs extern _ARMABI_PURE __udiv32by16 __rt_udiv32by16(
X__value_in_regs extern __declspec(__nothrow) __attribute__((const)) __udiv32by16 __rt_udiv32by16(
N     unsigned int /*numer*/,
N     unsigned short /*denom*/);
N   /*
N    * Unsigned divide: (16-bit quot), (16-bit rem) = (32-bit) / (16-bit)
N    */
N__value_in_regs extern _ARMABI_PURE __sdiv64by32 __rt_sdiv64by32(
X__value_in_regs extern __declspec(__nothrow) __attribute__((const)) __sdiv64by32 __rt_sdiv64by32(
N     int /*numer_h*/, unsigned int /*numer_l*/,
N     int /*denom*/);
N   /*
N    * Signed divide: (32-bit quot), (32-bit rem) = (64-bit) / (32-bit)
N    */
N#endif
N
N/*
N * ARM floating-point mask/status function (for both hardfp and softfp)
N */
Nextern _ARMABI unsigned int __fp_status(unsigned int /*mask*/, unsigned int /*flags*/);
Xextern __declspec(__nothrow) unsigned int __fp_status(unsigned int  , unsigned int  );
N   /*
N    * mask and flags are bit-fields which correspond directly to the
N    * floating point status register in the FPE/FPA and fplib.  
N    * __fp_status returns the current value of the status register,
N    * and also sets the writable bits of the word
N    * (the exception control and flag bytes) to:
N    *
N    *     new = (old & ~mask) ^ flags;
N    */
N#define __fpsr_IXE  0x100000
N#define __fpsr_UFE  0x80000
N#define __fpsr_OFE  0x40000
N#define __fpsr_DZE  0x20000
N#define __fpsr_IOE  0x10000
N
N#define __fpsr_IXC  0x10
N#define __fpsr_UFC  0x8
N#define __fpsr_OFC  0x4
N#define __fpsr_DZC  0x2
N#define __fpsr_IOC  0x1
N
N/*
N * Multibyte Character Functions.
N * The behaviour of the multibyte character functions is affected by the
N * LC_CTYPE category of the current locale. For a state-dependent encoding,
N * each function is placed into its initial state by a call for which its
N * character pointer argument, s, is a null pointer. Subsequent calls with s
N * as other than a null pointer cause the internal state of the function to be
N * altered as necessary. A call with s as a null pointer causes these functions
N * to return a nonzero value if encodings have state dependency, and a zero
N * otherwise. After the LC_CTYPE category is changed, the shift state of these
N * functions is indeterminate.
N */
Nextern _ARMABI int mblen(const char * /*s*/, size_t /*n*/);
Xextern __declspec(__nothrow) int mblen(const char *  , size_t  );
N   /*
N    * If s is not a null pointer, the mblen function determines the number of
N    * bytes compromising the multibyte character pointed to by s. Except that
N    * the shift state of the mbtowc function is not affected, it is equivalent
N    * to   mbtowc((wchar_t *)0, s, n);
N    * Returns: If s is a null pointer, the mblen function returns a nonzero or
N    *          zero value, if multibyte character encodings, respectively, do
N    *          or do not have state-dependent encodings. If s is not a null
N    *          pointer, the mblen function either returns a 0 (if s points to a
N    *          null character), or returns the number of bytes that compromise
N    *          the multibyte character (if the next n of fewer bytes form a
N    *          valid multibyte character), or returns -1 (they do not form a
N    *          valid multibyte character).
N    */
Nextern _ARMABI int mbtowc(wchar_t * __restrict /*pwc*/,
Xextern __declspec(__nothrow) int mbtowc(wchar_t * __restrict  ,
N                   const char * __restrict /*s*/, size_t /*n*/);
N   /*
N    * If s is not a null pointer, the mbtowc function determines the number of
N    * bytes that compromise the multibyte character pointed to by s. It then
N    * determines the code for value of type wchar_t that corresponds to that
N    * multibyte character. (The value of the code corresponding to the null
N    * character is zero). If the multibyte character is valid and pwc is not a
N    * null pointer, the mbtowc function stores the code in the object pointed
N    * to by pwc. At most n bytes of the array pointed to by s will be examined.
N    * Returns: If s is a null pointer, the mbtowc function returns a nonzero or
N    *          zero value, if multibyte character encodings, respectively, do
N    *          or do not have state-dependent encodings. If s is not a null
N    *          pointer, the mbtowc function either returns a 0 (if s points to
N    *          a null character), or returns the number of bytes that
N    *          compromise the converted multibyte character (if the next n of
N    *          fewer bytes form a valid multibyte character), or returns -1
N    *          (they do not form a valid multibyte character).
N    */
Nextern _ARMABI int wctomb(char * /*s*/, wchar_t /*wchar*/);
Xextern __declspec(__nothrow) int wctomb(char *  , wchar_t  );
N   /*
N    * determines the number of bytes need to represent the multibyte character
N    * corresponding to the code whose value is wchar (including any change in
N    * shift state). It stores the multibyte character representation in the
N    * array object pointed to by s (if s is not a null pointer). At most
N    * MB_CUR_MAX characters are stored. If the value of wchar is zero, the
N    * wctomb function is left in the initial shift state).
N    * Returns: If s is a null pointer, the wctomb function returns a nonzero or
N    *          zero value, if multibyte character encodings, respectively, do
N    *          or do not have state-dependent encodings. If s is not a null
N    *          pointer, the wctomb function returns a -1 if the value of wchar
N    *          does not correspond to a valid multibyte character, or returns
N    *          the number of bytes that compromise the multibyte character
N    *          corresponding to the value of wchar.
N    */
N
N/*
N * Multibyte String Functions.
N * The behaviour of the multibyte string functions is affected by the LC_CTYPE
N * category of the current locale.
N */
Nextern _ARMABI size_t mbstowcs(wchar_t * __restrict /*pwcs*/,
Xextern __declspec(__nothrow) size_t mbstowcs(wchar_t * __restrict  ,
N                      const char * __restrict /*s*/, size_t /*n*/) __attribute__((__nonnull__(2)));
N   /*
N    * converts a sequence of multibyte character that begins in the initial
N    * shift state from the array pointed to by s into a sequence of
N    * corresponding codes and stores not more than n codes into the array
N    * pointed to by pwcs. No multibyte character that follow a null character
N    * (which is converted into a code with value zero) will be examined or
N    * converted. Each multibyte character is converted as if by a call to
N    * mbtowc function, except that the shift state of the mbtowc function is
N    * not affected. No more than n elements will be modified in the array
N    * pointed to by pwcs. If copying takes place between objects that overlap,
N    * the behaviour is undefined.
N    * Returns: If an invalid multibyte character is encountered, the mbstowcs
N    *          function returns (size_t)-1. Otherwise, the mbstowcs function
N    *          returns the number of array elements modified, not including
N    *          a terminating zero code, if any.
N    */
Nextern _ARMABI size_t wcstombs(char * __restrict /*s*/,
Xextern __declspec(__nothrow) size_t wcstombs(char * __restrict  ,
N                      const wchar_t * __restrict /*pwcs*/, size_t /*n*/) __attribute__((__nonnull__(2)));
N   /*
N    * converts a sequence of codes that correspond to multibyte characters
N    * from the array pointed to by pwcs into a sequence of multibyte
N    * characters that begins in the initial shift state and stores these
N    * multibyte characters into the array pointed to by s, stopping if a
N    * multibyte character would exceed the limit of n total bytes or if a
N    * null character is stored. Each code is converted as if by a call to the
N    * wctomb function, except that the shift state of the wctomb function is
N    * not affected. No more than n elements will be modified in the array
N    * pointed to by s. If copying takes place between objects that overlap,
N    * the behaviour is undefined.
N    * Returns: If a code is encountered that does not correspond to a valid
N    *          multibyte character, the wcstombs function returns (size_t)-1.
N    *          Otherwise, the wcstombs function returns the number of bytes
N    *          modified, not including a terminating null character, if any.
N    */
N
Nextern _ARMABI void __use_realtime_heap(void);
Xextern __declspec(__nothrow) void __use_realtime_heap(void);
Nextern _ARMABI void __use_realtime_division(void);
Xextern __declspec(__nothrow) void __use_realtime_division(void);
Nextern _ARMABI void __use_two_region_memory(void);
Xextern __declspec(__nothrow) void __use_two_region_memory(void);
Nextern _ARMABI void __use_no_heap(void);
Xextern __declspec(__nothrow) void __use_no_heap(void);
Nextern _ARMABI void __use_no_heap_region(void);
Xextern __declspec(__nothrow) void __use_no_heap_region(void);
N
Nextern _ARMABI char const *__C_library_version_string(void);
Xextern __declspec(__nothrow) char const *__C_library_version_string(void);
Nextern _ARMABI int __C_library_version_number(void);
Xextern __declspec(__nothrow) int __C_library_version_number(void);
N
N    #ifdef __cplusplus
S         }  /* extern "C" */
S      }  /* namespace std */
N    #endif /* __cplusplus */
N  #endif /* __STDLIB_DECLS */
N
N  #if _AEABI_PORTABILITY_LEVEL != 0 && !defined _AEABI_PORTABLE
X  #if _AEABI_PORTABILITY_LEVEL != 0 && !0L
S    #define _AEABI_PORTABLE
N  #endif
N
N  #ifdef __cplusplus
S    #ifndef __STDLIB_NO_EXPORTS
S      #if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB
S        using ::std::atoll;
S        using ::std::lldiv_t;
S      #endif /* !defined(__STRICT_ANSI__) || __USE_C99_STDLIB */
S      using ::std::div_t;
S      using ::std::ldiv_t;
S      using ::std::atof;
S      using ::std::atoi;
S      using ::std::atol;
S      using ::std::strtod;
S#if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB
S      using ::std::strtof;
S      using ::std::strtold;
S#endif
S      using ::std::strtol;
S      using ::std::strtoul;
S      using ::std::strtoll;
S      using ::std::strtoull;
S      using ::std::rand;
S      using ::std::srand;
S      using ::std::_rand_state;
S      using ::std::_rand_r;
S      using ::std::_srand_r;
S      using ::std::_ANSI_rand_state;
S      using ::std::_ANSI_rand_r;
S      using ::std::_ANSI_srand_r;
S      using ::std::calloc;
S      using ::std::free;
S      using ::std::malloc;
S      using ::std::realloc;
S#if !defined(__STRICT_ANSI__)
S      using ::std::posix_memalign;
S#endif
S      using ::std::__heapprt;
S      using ::std::__heapstats;
S      using ::std::__heapvalid;
S      using ::std::abort;
S      using ::std::atexit;
S      using ::std::exit;
S      using ::std::_Exit;
S      using ::std::getenv;
S      using ::std::system;
S      using ::std::bsearch;
S      using ::std::qsort;
S      using ::std::abs;
S      using ::std::div;
S      using ::std::labs;
S      using ::std::ldiv;
S      #if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB
S        using ::std::llabs;
S        using ::std::lldiv;
S      #endif /* !defined(__STRICT_ANSI__) || __USE_C99_STDLIB */
S#if !(__ARM_NO_DEPRECATED_FUNCTIONS)
S      using ::std::__sdiv32by16;
S      using ::std::__udiv32by16;
S      using ::std::__sdiv64by32;
S      using ::std::__rt_sdiv32by16;
S      using ::std::__rt_udiv32by16;
S      using ::std::__rt_sdiv64by32;
S#endif
S      using ::std::__fp_status;
S      using ::std::mblen;
S      using ::std::mbtowc;
S      using ::std::wctomb;
S      using ::std::mbstowcs;
S      using ::std::wcstombs;
S      using ::std::__use_realtime_heap;
S      using ::std::__use_realtime_division;
S      using ::std::__use_two_region_memory;
S      using ::std::__use_no_heap;
S      using ::std::__use_no_heap_region;
S      using ::std::__C_library_version_string;
S      using ::std::__C_library_version_number;
S      using ::std::size_t;
S      using ::std::__aeabi_MB_CUR_MAX;
S    #endif /* __STDLIB_NO_EXPORTS */
N  #endif /* __cplusplus */
N
N#undef __LONGLONG
N
N#endif /* __stdlib_h */
N
N/* end of stdlib.h */
L 57 "..\..\User\bsp\bsp.h" 2
N#include "stm32f4xx_can.h"
N#include "stm32f4xx_conf.h"
L 1 "..\..\User\bsp\stm32f4xx_conf.h" 1
N/**
N  ******************************************************************************
N  * @file    Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h  
N  * @author  MCD Application Team
N  * @version V1.5.0
N  * @date    06-March-2015
N  * @brief   Library configuration file.
N  ******************************************************************************
N  * @attention
N  *
N  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
N  *
N  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
N  * You may not use this file except in compliance with the License.
N  * You may obtain a copy of the License at:
N  *
N  *        http://www.st.com/software_license_agreement_liberty_v2
N  *
N  * Unless required by applicable law or agreed to in writing, software 
N  * distributed under the License is distributed on an "AS IS" BASIS, 
N  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
N  * See the License for the specific language governing permissions and
N  * limitations under the License.
N  *
N  ******************************************************************************
N  */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F4xx_CONF_H
S#define __STM32F4xx_CONF_H
S
S/* Includes ------------------------------------------------------------------*/
S/* Uncomment the line below to enable peripheral header file inclusion */
S#include "stm32f4xx_adc.h"
S#include "stm32f4xx_crc.h"
S#include "stm32f4xx_dbgmcu.h"
S#include "stm32f4xx_dma.h"
S#include "stm32f4xx_exti.h"
S#include "stm32f4xx_flash.h"
S#include "stm32f4xx_gpio.h"
S#include "stm32f4xx_i2c.h"
S#include "stm32f4xx_iwdg.h"
S#include "stm32f4xx_pwr.h"
S#include "stm32f4xx_rcc.h"
S#include "stm32f4xx_rtc.h"
S#include "stm32f4xx_sdio.h"
S#include "stm32f4xx_spi.h"
S#include "stm32f4xx_syscfg.h"
S#include "stm32f4xx_tim.h"
S#include "stm32f4xx_usart.h"
S#include "stm32f4xx_wwdg.h"
S#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
S
S#if defined (STM32F429_439xx) || defined(STM32F446xx)
S#include "stm32f4xx_cryp.h"
S#include "stm32f4xx_hash.h"
S#include "stm32f4xx_rng.h"
S#include "stm32f4xx_can.h"
S#include "stm32f4xx_dac.h"
S#include "stm32f4xx_dcmi.h"
S#include "stm32f4xx_dma2d.h"
S#include "stm32f4xx_fmc.h"
S#include "stm32f4xx_ltdc.h"
S#include "stm32f4xx_sai.h"
S#endif /* STM32F429_439xx || STM32F446xx */
S
S#if defined (STM32F427_437xx)
S#include "stm32f4xx_cryp.h"
S#include "stm32f4xx_hash.h"
S#include "stm32f4xx_rng.h"
S#include "stm32f4xx_can.h"
S#include "stm32f4xx_dac.h"
S#include "stm32f4xx_dcmi.h"
S#include "stm32f4xx_dma2d.h"
S#include "stm32f4xx_fmc.h"
S#include "stm32f4xx_sai.h"
S#endif /* STM32F427_437xx */
S
S#if defined (STM32F40_41xxx)
S#include "stm32f4xx_cryp.h"
S#include "stm32f4xx_hash.h"
S#include "stm32f4xx_rng.h"
S#include "stm32f4xx_can.h"
S#include "stm32f4xx_dac.h"
S#include "stm32f4xx_dcmi.h"
S#include "stm32f4xx_fsmc.h"
S#endif /* STM32F40_41xxx */
S
S#if defined (STM32F411xE)
S#include "stm32f4xx_flash_ramfunc.h"
S#endif /* STM32F411xE */
S
S#if defined (STM32F446xx)
S#include "stm32f4xx_qspi.h"
S#include "stm32f4xx_fmpi2c.h"
S#include "stm32f4xx_spdifrx.h"
S#include "stm32f4xx_cec.h"
S#endif /* STM32F446xx */
S
S
S/* Exported types ------------------------------------------------------------*/
S/* Exported constants --------------------------------------------------------*/
S
S/* If an external clock source is used, then the value of the following define 
S   should be set to the value of the external clock source, else, if no external 
S   clock is used, keep this define commented */
S/*#define I2S_EXTERNAL_CLOCK_VAL   12288000 */ /* Value of the external clock in Hz */
S
S
S/* Uncomment the line below to expanse the "assert_param" macro in the 
S   Standard Peripheral Library drivers code */
S/* #define USE_FULL_ASSERT    1 */
S
S/* Exported macro ------------------------------------------------------------*/
S#ifdef  USE_FULL_ASSERT
S
S/**
S  * @brief  The assert_param macro is used for function's parameters check.
S  * @param  expr: If expr is false, it calls assert_failed function
S  *   which reports the name of the source file and the source
S  *   line number of the call that failed. 
S  *   If expr is true, it returns no value.
S  * @retval None
S  */
S  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
S/* Exported functions ------------------------------------------------------- */
S  void assert_failed(uint8_t* file, uint32_t line);
S#else
S  #define assert_param(expr) ((void)0)
S#endif /* USE_FULL_ASSERT */
S
N#endif /* __STM32F4xx_CONF_H */
N
N/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
L 59 "..\..\User\bsp\bsp.h" 2
N
N#include "stdbool.h"
L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.h" 1
N/* stdbool.h: ISO/IEC 9899:1999 (C99), section 7.16 */
N
N/* Copyright (C) ARM Ltd., 2002
N * All rights reserved
N * RCS $Revision$
N * Checkin $Date$
N * Revising $Author: drodgman $
N */
N
N#ifndef __bool_true_false_are_defined
N#define __bool_true_false_are_defined 1
N#define __ARMCLIB_VERSION 5060037
N
N  #ifndef __cplusplus /* In C++, 'bool', 'true' and 'false' and keywords */
N    #define bool _Bool
N    #define true 1
N    #define false 0
N  #else
S    #ifdef __GNUC__
S      /* GNU C++ supports direct inclusion of stdbool.h to provide C99
S         compatibility by defining _Bool */
S      #define _Bool bool
S    #endif
N  #endif
N
N#endif /* __bool_true_false_are_defined */
N
L 61 "..\..\User\bsp\bsp.h" 2
N#include <stdarg.h>
L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h" 1
N/* stdarg.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.8 */
N/* Copyright (C) Codemist Ltd., 1988                            */
N/* Copyright (C) ARM Ltd., 1991-1999. All rights reserved */
N
N/*
N * RCS $Revision$
N * Checkin $Date$
N * Revising $Author: agrant $
N */
N
N#ifndef __stdarg_h
N#define __stdarg_h
N#define __ARMCLIB_VERSION 5060037
N
N  #ifndef __STDARG_DECLS
N  #define __STDARG_DECLS
N
N    #undef __CLIBNS
N
N    #ifdef __cplusplus
S      namespace std {
S          #define __CLIBNS ::std::
S          extern "C" {
N    #else
N      #define __CLIBNS
N    #endif  /* __cplusplus */
N
N/*
N * stdarg.h declares a type and defines macros for advancing through a
N * list of arguments whose number and types are not known to the called
N * function when it is translated. A function may be called with a variable
N * number of arguments of differing types. Its parameter list contains one or
N * more parameters. The rightmost parameter plays a special role in the access
N * mechanism, and will be called parmN in this description.
N */
N
N/* N.B. <stdio.h> is required to declare vfprintf() without defining      */
N/* va_list.  Clearly the type __va_list there must keep in step.          */
N#ifdef __clang__
S  typedef __builtin_va_list va_list;
S  #define va_start(ap, param) __builtin_va_start(ap, param)
S  #define va_end(ap)          __builtin_va_end(ap)
S  #define va_arg(ap, type)    __builtin_va_arg(ap, type)
S  #if __STDC_VERSION__ >= 199900L || __cplusplus >= 201103L || !defined(__STRICT_ANSI__)
S  #define va_copy(dest, src)  __builtin_va_copy(dest, src)
S  #endif
N#else
N  #ifdef __TARGET_ARCH_AARCH64
S    typedef struct __va_list {
S      void *__stack;
S      void *__gr_top;
S      void *__vr_top;
S      int __gr_offs;
S      int __vr_offs;
S    } va_list;
N  #else
N    typedef struct __va_list { void *__ap; } va_list;
N  #endif
N   /*
N    * an array type suitable for holding information needed by the macro va_arg
N    * and the function va_end. The called function shall declare a variable
N    * (referred to as ap) having type va_list. The variable ap may be passed as
N    * an argument to another function.
N    * Note: va_list is an array type so that when an object of that type
N    * is passed as an argument it gets passed by reference.
N    */
N  #define va_start(ap, parmN) __va_start(ap, parmN)
N
N   /*
N    * The va_start macro shall be executed before any access to the unnamed
N    * arguments. The parameter ap points to an object that has type va_list.
N    * The va_start macro initialises ap for subsequent use by va_arg and
N    * va_end. The parameter parmN is the identifier of the rightmost parameter
N    * in the variable parameter list in the function definition (the one just
N    * before the '...'). If the parameter parmN is declared with the register
N    * storage class an error is given.
N    * If parmN is a narrow type (char, short, float) an error is given in
N    * strict ANSI mode, or a warning otherwise.
N    * Returns: no value.
N    */
N  #define va_arg(ap, type) __va_arg(ap, type)
N
N   /*
N    * The va_arg macro expands to an expression that has the type and value of
N    * the next argument in the call. The parameter ap shall be the same as the
N    * va_list ap initialised by va_start. Each invocation of va_arg modifies
N    * ap so that successive arguments are returned in turn. The parameter
N    * 'type' is a type name such that the type of a pointer to an object that
N    * has the specified type can be obtained simply by postfixing a * to
N    * 'type'. If type is a narrow type, an error is given in strict ANSI
N    * mode, or a warning otherwise. If the type is an array or function type,
N    * an error is given.
N    * In non-strict ANSI mode, 'type' is allowed to be any expression.
N    * Returns: The first invocation of the va_arg macro after that of the
N    *          va_start macro returns the value of the argument after that
N    *          specified by parmN. Successive invocations return the values of
N    *          the remaining arguments in succession.
N    *          The result is cast to 'type', even if 'type' is narrow.
N    */
N
N#define __va_copy(dest, src) ((void)((dest) = (src)))
N
N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus)
X#if !0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus)
N   /* va_copy is in C99 and non-strict C90 and non-strict C++
N    * __va_copy is always present.
N    */
N  #define va_copy(dest, src) ((void)((dest) = (src)))
N
N   /* The va_copy macro makes the va_list dest be a copy of
N    * the va_list src, as if the va_start macro had been applied
N    * to it followed by the same sequence of uses of the va_arg
N    * macro as had previously been used to reach the present state
N    * of src.
N    */
N#endif
N
N#define va_end(ap) __va_end(ap)
N   /*
N    * The va_end macro facilitates a normal return from the function whose
N    * variable argument list was referenced by the expansion of va_start that
N    * initialised the va_list ap. If the va_end macro is not invoked before
N    * the return, the behaviour is undefined.
N    * Returns: no value.
N    */
N#endif /* __clang__ */
N
N    #ifdef __cplusplus
S         }  /* extern "C" */
S      }  /* namespace std */
N    #endif /* __cplusplus */
N
N    #ifdef __GNUC__
S     /* be cooperative with glibc */
S     typedef __CLIBNS va_list __gnuc_va_list;
S     #define __GNUC_VA_LIST
S     #undef __need___va_list
N    #endif
N
N  #endif /* __STDARG_DECLS */
N
N  #ifdef __cplusplus
S    #ifndef __STDARG_NO_EXPORTS
S      using ::std::va_list;
S    #endif
N  #endif /* __cplusplus */
N#endif
N
N/* end of stdarg.h */
N
L 62 "..\..\User\bsp\bsp.h" 2
N#include  <math.h>
L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h" 1
N/*
N * math.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.5
N * Copyright (C) Codemist Ltd., 1988
N * Copyright 1991-1998,2004-2006,2014 ARM Limited. All rights reserved
N */
N
N/*
N * RCS $Revision$ Codemist 0.03
N * Checkin $Date$
N * Revising $Author: statham $
N */
N
N/*
N * Parts of this file are based upon fdlibm:
N *
N * ====================================================
N * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
N *
N * Developed at SunSoft, a Sun Microsystems, Inc. business.
N * Permission to use, copy, modify, and distribute this
N * software is freely granted, provided that this notice
N * is preserved.
N * ====================================================
N */
N
N#ifndef __math_h
N#define __math_h
N#define __ARMCLIB_VERSION 5060037
N
N#if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__))
X#if 0L || (1L && !0L)
N  /* armclang and non-strict armcc allow 'long long' in system headers */
N  #define __LONGLONG long long
N#else
S  /* strict armcc has '__int64' */
S  #define __LONGLONG __int64
N#endif
N
N/*
N * Some of these declarations are new in C99.  To access them in C++
N * you can use -D__USE_C99_MATH (or -D__USE_C99_ALL).
N */
N#ifndef __USE_C99_MATH
N  #if defined(__USE_C99_ALL) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus)
X  #if 0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus)
N    #define __USE_C99_MATH 1
N  #endif
N#endif
N
N#define _ARMABI __declspec(__nothrow)
N#ifdef __TARGET_ARCH_AARCH64
S# define _ARMABI_SOFTFP __declspec(__nothrow)
N#else
N# define _ARMABI_SOFTFP __declspec(__nothrow) __attribute__((__pcs__("aapcs")))
N# define __HAVE_LONGDOUBLE 1
N#endif
N#define _ARMABI_PURE __declspec(__nothrow) __attribute__((const))
N#ifdef __FP_FENV_EXCEPTIONS
S# define _ARMABI_FPEXCEPT _ARMABI
N#else
N# define _ARMABI_FPEXCEPT _ARMABI __attribute__((const))
N#endif
N
N#ifdef __cplusplus
S#define _ARMABI_INLINE inline
S#define _ARMABI_INLINE_DEF inline
S#elif defined __GNUC__ || defined _USE_STATIC_INLINE
X#elif 0L || 0L
S#define _ARMABI_INLINE static __inline
S#define _ARMABI_INLINE_DEF static __inline
N#elif (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__)
X#elif (1L && 199901L <= 199901L)
N#define _ARMABI_INLINE inline
N#define _ARMABI_INLINE_DEF static inline
N#else
S#define _ARMABI_INLINE __inline
S#define _ARMABI_INLINE_DEF __inline
N#endif
N
N#ifdef __TARGET_ARCH_AARCH64
S#  define _SOFTFP
N#else
N#  define _SOFTFP __attribute__((__pcs__("aapcs")))
N#endif
N
N   /*
N    * If the compiler supports signalling nans as per N965 then it
N    * will define __SUPPORT_SNAN__, in which case a user may define
N    * _WANT_SNAN in order to obtain the nans function, as well as the
N    * FP_NANS and FP_NANQ classification macros.
N    */
N#if defined(__SUPPORT_SNAN__) && defined(_WANT_SNAN)
X#if 0L && 0L
S#pragma import(__use_snan)
N#endif
N
N/*
N * Macros for our inline functions down below.
N * unsigned& __FLT(float x) - returns the bit pattern of x
N * unsigned& __HI(double x) - returns the bit pattern of the high part of x
N *                            (high part has exponent & sign bit in it)
N * unsigned& __LO(double x) - returns the bit pattern of the low part of x
N *
N * We can assign to __FLT, __HI, and __LO and the appropriate bits get set in
N * the floating point variable used.
N *
N * __HI & __LO are affected by the endianness and the target FPU.
N */
N#define __FLT(x) (*(unsigned *)&(x))
N#if defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN)
X#if 0L || 0L
S#  define __LO(x) (*(1 + (unsigned *)&(x)))
S#  define __HI(x) (*(unsigned *)&(x))
N#else /* !defined(__ARM_BIG_ENDIAN) && !defined(__BIG_ENDIAN) */
N#  define __HI(x) (*(1 + (unsigned *)&(x)))
N#  define __LO(x) (*(unsigned *)&(x))
N#endif /* !defined(__ARM_BIG_ENDIAN) && !defined(__BIG_ENDIAN) */
N
N#   ifndef __MATH_DECLS
N#   define __MATH_DECLS
N
N
N/*
N * A set of functions that we don't actually want to put in the standard
N * namespace ever.  These are all called by the C99 macros.  As they're
N * not specified by any standard they can't belong in ::std::.  The
N * macro #defines are below amongst the standard function declarations.
N * We only include these if we actually need them later on
N */
N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)
X#if !0L || 1L
N#   ifdef __cplusplus
S      extern "C" {
N#   endif /* __cplusplus */
N
Nextern _SOFTFP unsigned __ARM_dcmp4(double /*x*/, double /*y*/);
Xextern __attribute__((__pcs__("aapcs"))) unsigned __ARM_dcmp4(double  , double  );
Nextern _SOFTFP unsigned __ARM_fcmp4(float /*x*/, float /*y*/);
Xextern __attribute__((__pcs__("aapcs"))) unsigned __ARM_fcmp4(float  , float  );
N    /*
N     * Compare x and y and return the CPSR in r0.  These means we can test for
N     * result types with bit pattern matching.
N     *
N     * These are a copy of the declarations in rt_fp.h keep in sync.
N     */
N
Nextern _ARMABI_SOFTFP int __ARM_fpclassifyf(float /*x*/);
Xextern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassifyf(float  );
Nextern _ARMABI_SOFTFP int __ARM_fpclassify(double /*x*/);
Xextern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassify(double  );
N    /* Classify x into NaN, infinite, normal, subnormal, zero */
N    /* Used by fpclassify macro */
N
N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isfinitef(float __x)
Xstatic inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinitef(float __x)
N{
N    return ((__FLT(__x) >> 23) & 0xff) != 0xff;
X    return (((*(unsigned *)&(__x)) >> 23) & 0xff) != 0xff;
N}
N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isfinite(double __x)
Xstatic inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinite(double __x)
N{
N    return ((__HI(__x) >> 20) & 0x7ff) != 0x7ff;
X    return (((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff) != 0x7ff;
N}
N    /* Return 1 if __x is finite, 0 otherwise */
N    /* Used by isfinite macro */
N
N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isinff(float __x)
Xstatic inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinff(float __x)
N{
N    return (__FLT(__x) << 1) == 0xff000000;
X    return ((*(unsigned *)&(__x)) << 1) == 0xff000000;
N}
N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isinf(double __x)
Xstatic inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinf(double __x)
N{
N    return ((__HI(__x) << 1) == 0xffe00000) && (__LO(__x) == 0);
X    return (((*(1 + (unsigned *)&(__x))) << 1) == 0xffe00000) && ((*(unsigned *)&(__x)) == 0);
N}
N    /* Return 1 if __x is infinite, 0 otherwise */
N    /* Used by isinf macro */
N
N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_islessgreaterf(float __x, float __y)
Xstatic inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreaterf(float __x, float __y)
N{
N    unsigned __f = __ARM_fcmp4(__x, __y) >> 28;
N    return (__f == 8) || (__f == 2); /* Just N set or Just Z set */
N}
N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_islessgreater(double __x, double __y)
Xstatic inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreater(double __x, double __y)
N{
N    unsigned __f = __ARM_dcmp4(__x, __y) >> 28;
N    return (__f == 8) || (__f == 2); /* Just N set or Just Z set */
N}
N    /*
N     * Compare __x and __y and return 1 if __x < __y or __x > __y, 0 otherwise
N     * Used by islessgreater macro
N     */
N
N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnanf(float __x)
Xstatic inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnanf(float __x)
N{
N    return (0x7f800000 - (__FLT(__x) & 0x7fffffff)) >> 31;
X    return (0x7f800000 - ((*(unsigned *)&(__x)) & 0x7fffffff)) >> 31;
N}
N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnan(double __x)
Xstatic inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnan(double __x)
N{
N    unsigned __xf = __HI(__x) | ((__LO(__x) == 0) ? 0 : 1);
X    unsigned __xf = (*(1 + (unsigned *)&(__x))) | (((*(unsigned *)&(__x)) == 0) ? 0 : 1);
N    return (0x7ff00000 - (__xf & 0x7fffffff)) >> 31;
N}
N    /* Return 1 if __x is a NaN, 0 otherwise */
N    /* Used by isnan macro */
N
N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnormalf(float __x)
Xstatic inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormalf(float __x)
N{
N    unsigned __xe = (__FLT(__x) >> 23) & 0xff;
X    unsigned __xe = ((*(unsigned *)&(__x)) >> 23) & 0xff;
N    return (__xe != 0xff) && (__xe != 0);
N}
N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnormal(double __x)
Xstatic inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormal(double __x)
N{
N    unsigned __xe = (__HI(__x) >> 20) & 0x7ff;
X    unsigned __xe = ((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff;
N    return (__xe != 0x7ff) && (__xe != 0);
N}
N    /* Return 1 if __x is a normalised number, 0 otherwise */
N    /* used by isnormal macro */
N
N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_signbitf(float __x)
Xstatic inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbitf(float __x)
N{
N    return __FLT(__x) >> 31;
X    return (*(unsigned *)&(__x)) >> 31;
N}
N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_signbit(double __x)
Xstatic inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbit(double __x)
N{
N    return __HI(__x) >> 31;
X    return (*(1 + (unsigned *)&(__x))) >> 31;
N}
N    /* Return signbit of __x */
N    /* Used by signbit macro */
N
N#   ifdef __cplusplus
S      } /* extern "C" */
N#   endif /* __cplusplus */
N#endif /* Strict ANSI */
N
N#   undef __CLIBNS
N
N#   ifdef __cplusplus
S      namespace std {
S#       define __CLIBNS ::std::
S        extern "C" {
N#   else
N#       define __CLIBNS
N#   endif  /* __cplusplus */
N
N
N#ifndef __has_builtin
N  #define __has_builtin(x) 0
N#endif
N
N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)
X#if !0L || 1L
N  /* C99 additions */
N  typedef float float_t;
N  typedef double double_t;
N#if __has_builtin(__builtin_inf)
X#if 0
S#   define HUGE_VALF __builtin_inff()
S#   define HUGE_VALL __builtin_infl()
S#   define INFINITY __builtin_inff()
S#   define NAN __builtin_nanf("")
N# else
N#   define HUGE_VALF ((float)__INFINITY__)
N#   define HUGE_VALL ((long double)__INFINITY__)
N#   define INFINITY ((float)__INFINITY__)
N#   define NAN (__ESCAPE__(0f_7FC00000))
N#endif
N
N#   define MATH_ERRNO 1
N#   define MATH_ERREXCEPT 2
Nextern const int math_errhandling;
N#endif
N#if __has_builtin(__builtin_inf)
X#if 0
S# define HUGE_VAL __builtin_inf()
N#else
N# define HUGE_VAL ((double)__INFINITY__)
N#endif
N
Nextern _ARMABI double acos(double /*x*/);
Xextern __declspec(__nothrow) double acos(double  );
N   /* computes the principal value of the arc cosine of x */
N   /* a domain error occurs for arguments not in the range -1 to 1 */
N   /* Returns: the arc cosine in the range 0 to Pi. */
Nextern _ARMABI double asin(double /*x*/);
Xextern __declspec(__nothrow) double asin(double  );
N   /* computes the principal value of the arc sine of x */
N   /* a domain error occurs for arguments not in the range -1 to 1 */
N   /* and -HUGE_VAL is returned. */
N   /* Returns: the arc sine in the range -Pi/2 to Pi/2. */
N
Nextern _ARMABI_PURE double atan(double /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) double atan(double  );
N   /* computes the principal value of the arc tangent of x */
N   /* Returns: the arc tangent in the range -Pi/2 to Pi/2. */
N
Nextern _ARMABI double atan2(double /*y*/, double /*x*/);
Xextern __declspec(__nothrow) double atan2(double  , double  );
N   /* computes the principal value of the arc tangent of y/x, using the */
N   /* signs of both arguments to determine the quadrant of the return value */
N   /* a domain error occurs if both args are zero, and -HUGE_VAL returned. */
N   /* Returns: the arc tangent of y/x, in the range -Pi to Pi. */
N
Nextern _ARMABI double cos(double /*x*/);
Xextern __declspec(__nothrow) double cos(double  );
N   /* computes the cosine of x (measured in radians). A large magnitude */
N   /* argument may yield a result with little or no significance. */
N   /* a domain error occurs for infinite input (C 7.12.1 footnote 196). */
N   /* Returns: the cosine value. */
Nextern _ARMABI double sin(double /*x*/);
Xextern __declspec(__nothrow) double sin(double  );
N   /* computes the sine of x (measured in radians). A large magnitude */
N   /* argument may yield a result with little or no significance. */
N   /* a domain error occurs for infinite input (C 7.12.1 footnote 196). */
N   /* Returns: the sine value. */
N
Nextern void __use_accurate_range_reduction(void);
N   /* reference this to select the larger, slower, but more accurate */
N   /* range reduction in sin, cos and tan */
N
Nextern _ARMABI double tan(double /*x*/);
Xextern __declspec(__nothrow) double tan(double  );
N   /* computes the tangent of x (measured in radians). A large magnitude */
N   /* argument may yield a result with little or no significance */
N   /* Returns: the tangent value. */
N   /*          if range error; returns HUGE_VAL. */
N
Nextern _ARMABI double cosh(double /*x*/);
Xextern __declspec(__nothrow) double cosh(double  );
N   /* computes the hyperbolic cosine of x. A range error occurs if the */
N   /* magnitude of x is too large. */
N   /* Returns: the hyperbolic cosine value. */
N   /*          if range error; returns HUGE_VAL. */
Nextern _ARMABI double sinh(double /*x*/);
Xextern __declspec(__nothrow) double sinh(double  );
N   /* computes the hyperbolic sine of x. A range error occurs if the */
N   /* magnitude of x is too large. */
N   /* Returns: the hyperbolic sine value. */
N   /*          if range error; returns -HUGE_VAL or HUGE_VAL depending */
N   /*          on the sign of the argument */
N
Nextern _ARMABI_PURE double tanh(double /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) double tanh(double  );
N   /* computes the hyperbolic tangent of x. */
N   /* Returns: the hyperbolic tangent value. */
N
Nextern _ARMABI double exp(double /*x*/);
Xextern __declspec(__nothrow) double exp(double  );
N   /* computes the exponential function of x. A range error occurs if the */
N   /* magnitude of x is too large. */
N   /* Returns: the exponential value. */
N   /*          if underflow range error; 0 is returned. */
N   /*          if overflow range error; HUGE_VAL is returned. */
N
Nextern _ARMABI double frexp(double /*value*/, int * /*exp*/) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) double frexp(double  , int *  ) __attribute__((__nonnull__(2)));
N   /* breaks a floating-point number into a normalised fraction and an */
N   /* integral power of 2. It stores the integer in the int object pointed */
N   /* to by exp. */
N   /* Returns: the value x, such that x is a double with magnitude in the */
N   /* interval 0.5 to 1.0 or zero, and value equals x times 2 raised to the */
N   /* power *exp. If value is zero, both parts of the result are zero. */
N
Nextern _ARMABI double ldexp(double /*x*/, int /*exp*/);
Xextern __declspec(__nothrow) double ldexp(double  , int  );
N   /* multiplies a floating-point number by an integral power of 2. */
N   /* A range error may occur. */
N   /* Returns: the value of x times 2 raised to the power of exp. */
N   /*          if range error; HUGE_VAL is returned. */
Nextern _ARMABI double log(double /*x*/);
Xextern __declspec(__nothrow) double log(double  );
N   /* computes the natural logarithm of x. A domain error occurs if the */
N   /* argument is negative, and -HUGE_VAL is returned. A range error occurs */
N   /* if the argument is zero. */
N   /* Returns: the natural logarithm. */
N   /*          if range error; -HUGE_VAL is returned. */
Nextern _ARMABI double log10(double /*x*/);
Xextern __declspec(__nothrow) double log10(double  );
N   /* computes the base-ten logarithm of x. A domain error occurs if the */
N   /* argument is negative. A range error occurs if the argument is zero. */
N   /* Returns: the base-ten logarithm. */
Nextern _ARMABI double modf(double /*value*/, double * /*iptr*/) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) double modf(double  , double *  ) __attribute__((__nonnull__(2)));
N   /* breaks the argument value into integral and fraction parts, each of */
N   /* which has the same sign as the argument. It stores the integral part */
N   /* as a double in the object pointed to by iptr. */
N   /* Returns: the signed fractional part of value. */
N
Nextern _ARMABI double pow(double /*x*/, double /*y*/);
Xextern __declspec(__nothrow) double pow(double  , double  );
N   /* computes x raised to the power of y. A domain error occurs if x is */
N   /* zero and y is less than or equal to zero, or if x is negative and y */
N   /* is not an integer, and -HUGE_VAL returned. A range error may occur. */
N   /* Returns: the value of x raised to the power of y. */
N   /*          if underflow range error; 0 is returned. */
N   /*          if overflow range error; HUGE_VAL is returned. */
Nextern _ARMABI double sqrt(double /*x*/);
Xextern __declspec(__nothrow) double sqrt(double  );
N   /* computes the non-negative square root of x. A domain error occurs */
N   /* if the argument is negative, and -HUGE_VAL returned. */
N   /* Returns: the value of the square root. */
N
N#if defined(__TARGET_FPU_VFP_DOUBLE) && !defined(__TARGET_FPU_SOFTVFP)
X#if 0L && !0L
S    _ARMABI_INLINE double _sqrt(double __x) { return __sqrt(__x); }
N#else
N    _ARMABI_INLINE double _sqrt(double __x) { return sqrt(__x); }
X    inline double _sqrt(double __x) { return sqrt(__x); }
N#endif
N#if defined(__TARGET_FPU_VFP_SINGLE) && !defined(__TARGET_FPU_SOFTVFP)
X#if 1L && !0L
N    _ARMABI_INLINE float _sqrtf(float __x) { return __sqrtf(__x); }
X    inline float _sqrtf(float __x) { return __sqrtf(__x); }
N#else
S    _ARMABI_INLINE float _sqrtf(float __x) { return (float)sqrt(__x); }
N#endif
N    /* With VFP, _sqrt and _sqrtf should expand inline as the native VFP square root
N     * instructions. They will not behave like the C sqrt() function, because
N     * they will report unusual values as IEEE exceptions (in fpmodes which
N     * support IEEE exceptions) rather than in errno. These function names
N     * are not specified in any standard. */
N
Nextern _ARMABI_PURE double ceil(double /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) double ceil(double  );
N   /* computes the smallest integer not less than x. */
N   /* Returns: the smallest integer not less than x, expressed as a double. */
Nextern _ARMABI_PURE double fabs(double /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) double fabs(double  );
N   /* computes the absolute value of the floating-point number x. */
N   /* Returns: the absolute value of x. */
N
Nextern _ARMABI_PURE double floor(double /*d*/);
Xextern __declspec(__nothrow) __attribute__((const)) double floor(double  );
N   /* computes the largest integer not greater than x. */
N   /* Returns: the largest integer not greater than x, expressed as a double */
N
Nextern _ARMABI double fmod(double /*x*/, double /*y*/);
Xextern __declspec(__nothrow) double fmod(double  , double  );
N   /* computes the floating-point remainder of x/y. */
N   /* Returns: the value x - i * y, for some integer i such that, if y is */
N   /*          nonzero, the result has the same sign as x and magnitude */
N   /*          less than the magnitude of y. If y is zero, a domain error */
N   /*          occurs and -HUGE_VAL is returned. */
N
N    /* Additional Mathlib functions not defined by the ANSI standard.
N     * Not guaranteed, and not necessarily very well tested.
N     * C99 requires the user to include <math.h> to use these functions
N     * declaring them "by hand" is not sufficient
N     *
N     * The above statement is not completely true now.  Some of the above
N     * C99 functionality has been added as per the Standard, and (where
N     * necessary) old Mathlib functionality withdrawn/changed.  Before
N     * including this header #define __ENABLE_MATHLIB_LEGACY if you want to
N     * re-enable the legacy functionality.
N     */
N
N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)
X#if !0L || 1L
N
Nextern _ARMABI double acosh(double /*x*/);
Xextern __declspec(__nothrow) double acosh(double  );
N    /*
N     * Inverse cosh. EDOM if argument < 1.0
N     */
Nextern _ARMABI double asinh(double /*x*/);
Xextern __declspec(__nothrow) double asinh(double  );
N    /*
N     * Inverse sinh.
N     */
Nextern _ARMABI double atanh(double /*x*/);
Xextern __declspec(__nothrow) double atanh(double  );
N    /*
N     * Inverse tanh. EDOM if |argument| > 1.0
N     */
Nextern _ARMABI double cbrt(double /*x*/);
Xextern __declspec(__nothrow) double cbrt(double  );
N    /*
N     * Cube root.
N     */
N_ARMABI_INLINE _ARMABI_PURE double copysign(double __x, double __y)
Xinline __declspec(__nothrow) __attribute__((const)) double copysign(double __x, double __y)
N    /*
N     * Returns x with sign bit replaced by sign of y.
N     */
N{
N    __HI(__x) = (__HI(__x) & 0x7fffffff) | (__HI(__y) & 0x80000000);
X    (*(1 + (unsigned *)&(__x))) = ((*(1 + (unsigned *)&(__x))) & 0x7fffffff) | ((*(1 + (unsigned *)&(__y))) & 0x80000000);
N    return __x;
N}
N_ARMABI_INLINE _ARMABI_PURE float copysignf(float __x, float __y)
Xinline __declspec(__nothrow) __attribute__((const)) float copysignf(float __x, float __y)
N    /*
N     * Returns x with sign bit replaced by sign of y.
N     */
N{
N    __FLT(__x) = (__FLT(__x) & 0x7fffffff) | (__FLT(__y) & 0x80000000);
X    (*(unsigned *)&(__x)) = ((*(unsigned *)&(__x)) & 0x7fffffff) | ((*(unsigned *)&(__y)) & 0x80000000);
N    return __x;
N}
Nextern _ARMABI double erf(double /*x*/);
Xextern __declspec(__nothrow) double erf(double  );
N    /*
N     * Error function. (2/sqrt(pi)) * integral from 0 to x of exp(-t*t) dt.
N     */
Nextern _ARMABI double erfc(double /*x*/);
Xextern __declspec(__nothrow) double erfc(double  );
N    /*
N     * 1-erf(x). (More accurate than just coding 1-erf(x), for large x.)
N     */
Nextern _ARMABI double expm1(double /*x*/);
Xextern __declspec(__nothrow) double expm1(double  );
N    /*
N     * exp(x)-1. (More accurate than just coding exp(x)-1, for small x.)
N     */
N#define fpclassify(x) \
N    ((sizeof(x) == sizeof(float)) ? \
N        __ARM_fpclassifyf(x) : __ARM_fpclassify(x))
X#define fpclassify(x)     ((sizeof(x) == sizeof(float)) ?         __ARM_fpclassifyf(x) : __ARM_fpclassify(x))
N    /*
N     * Classify a floating point number into one of the following values:
N     */
N#define FP_ZERO         (0)
N#define FP_SUBNORMAL    (4)
N#define FP_NORMAL       (5)
N#define FP_INFINITE     (3)
N#define FP_NAN          (7)
N
N#if defined(_WANT_SNAN) && defined(__SUPPORT_SNAN__)
X#if 0L && 0L
S/* 
S * Note that we'll never classify a number as FP_NAN, as all NaNs will 
S * be either FP_NANQ or FP_NANS
S */
S#  define FP_NANQ       (8)
S#  define FP_NANS       (9)
N#endif
N
N
Nextern _ARMABI double hypot(double /*x*/, double /*y*/);
Xextern __declspec(__nothrow) double hypot(double  , double  );
N    /*
N     * sqrt(x*x+y*y), ie the length of the vector (x,y) or the
N     * hypotenuse of a right triangle whose other two sides are x
N     * and y. Won't overflow unless the _answer_ is too big, even
N     * if the intermediate x*x+y*y is too big.
N     */
Nextern _ARMABI int ilogb(double /*x*/);
Xextern __declspec(__nothrow) int ilogb(double  );
N    /*
N     * Exponent of x (returns 0 for 1.0, 1 for 2.0, -1 for 0.5, etc.)
N     */
Nextern _ARMABI int ilogbf(float /*x*/);
Xextern __declspec(__nothrow) int ilogbf(float  );
N    /*
N     * Like ilogb but takes a float
N     */
Nextern _ARMABI int ilogbl(long double /*x*/);
Xextern __declspec(__nothrow) int ilogbl(long double  );
N    /*
N     * Exponent of x (returns 0 for 1.0, 1 for 2.0, -1 for 0.5, etc.)
N     */
N#define FP_ILOGB0   (-0x7fffffff) /* ilogb(0) == -INT_MAX */
N#define FP_ILOGBNAN ( 0x80000000) /* ilogb(NAN) == INT_MIN */
N
N#define isfinite(x) \
N    ((sizeof(x) == sizeof(float)) \
N        ? __ARM_isfinitef(x) \
N        : __ARM_isfinite(x))
X#define isfinite(x)     ((sizeof(x) == sizeof(float))         ? __ARM_isfinitef(x)         : __ARM_isfinite(x))
N    /*
N     * Returns true if x is a finite number, size independent.
N     */
N
N#define isgreater(x, y) \
N    (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \
N        ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) \
N        : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000))
X#define isgreater(x, y)     (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float)))         ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000)         : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000))
N    /*
N     * Returns true if x > y, throws no exceptions except on Signaling NaNs
N     *
N     * We want the C not set but the Z bit clear, V must be clear
N     */
N
N#define isgreaterequal(x, y) \
N    (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \
N        ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) \
N        : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000))
X#define isgreaterequal(x, y)     (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float)))         ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000)         : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000))
N    /*
N     * Returns true if x >= y, throws no exceptions except on Signaling NaNs
N     *
N     * We just need to see if the C bit is set or not and ensure V clear
N     */
N
N#define isinf(x) \
N    ((sizeof(x) == sizeof(float)) \
N        ? __ARM_isinff(x) \
N        : __ARM_isinf(x))
X#define isinf(x)     ((sizeof(x) == sizeof(float))         ? __ARM_isinff(x)         : __ARM_isinf(x))
N    /*
N     * Returns true if x is an infinity, size independent.
N     */
N
N#define isless(x, y)  \
N    (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \
N        ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) \
N        : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000))
X#define isless(x, y)      (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float)))         ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000)         : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000))
N    /*
N     * Returns true if x < y, throws no exceptions except on Signaling NaNs
N     *
N     * We're less than if N is set, V clear
N     */
N
N#define islessequal(x, y) \
N    (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \
N        ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) \
N        : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0))
X#define islessequal(x, y)     (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float)))         ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0)         : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0))
N    /*
N     * Returns true if x <= y, throws no exceptions except on Signaling NaNs
N     *
N     * We're less than or equal if one of N or Z is set, V clear
N     */
N
N#define islessgreater(x, y) \
N    (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \
N        ? __ARM_islessgreaterf((x), (y)) \
N        : __ARM_islessgreater((x), (y)))
X#define islessgreater(x, y)     (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float)))         ? __ARM_islessgreaterf((x), (y))         : __ARM_islessgreater((x), (y)))
N    /*
N     * Returns true if x <> y, throws no exceptions except on Signaling NaNs
N     * Unfortunately this test is too complicated to do in a macro without
N     * evaluating x & y twice.  Shame really...
N     */
N
N#define isnan(x) \
N    ((sizeof(x) == sizeof(float)) \
N        ? __ARM_isnanf(x) \
N        : __ARM_isnan(x))
X#define isnan(x)     ((sizeof(x) == sizeof(float))         ? __ARM_isnanf(x)         : __ARM_isnan(x))
N    /*
N     * Returns TRUE if x is a NaN.
N     */
N
N#define isnormal(x) \
N    ((sizeof(x) == sizeof(float)) \
N        ? __ARM_isnormalf(x) \
N        : __ARM_isnormal(x))
X#define isnormal(x)     ((sizeof(x) == sizeof(float))         ? __ARM_isnormalf(x)         : __ARM_isnormal(x))
N    /*
N     * Returns TRUE if x is a NaN.
N     */
N
N#define isunordered(x, y) \
N    (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \
N        ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) \
N        : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000))
X#define isunordered(x, y)     (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float)))         ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000)         : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000))
N    /*
N     * Returns true if x ? y, throws no exceptions except on Signaling NaNs
N     * Unordered occurs if and only if the V bit is set
N     */
N
Nextern _ARMABI double lgamma (double /*x*/);
Xextern __declspec(__nothrow) double lgamma (double  );
N    /*
N     * The log of the absolute value of the gamma function of x. The sign
N     * of the gamma function of x is returned in the global `signgam'.
N     */
Nextern _ARMABI double log1p(double /*x*/);
Xextern __declspec(__nothrow) double log1p(double  );
N    /*
N     * log(1+x). (More accurate than just coding log(1+x), for small x.)
N     */
Nextern _ARMABI double logb(double /*x*/);
Xextern __declspec(__nothrow) double logb(double  );
N    /*
N     * Like ilogb but returns a double.
N     */
Nextern _ARMABI float logbf(float /*x*/);
Xextern __declspec(__nothrow) float logbf(float  );
N    /*
N     * Like logb but takes and returns float
N     */
Nextern _ARMABI long double logbl(long double /*x*/);
Xextern __declspec(__nothrow) long double logbl(long double  );
N    /*
N     * Like logb but takes and returns long double
N     */
Nextern _ARMABI double nextafter(double /*x*/, double /*y*/);
Xextern __declspec(__nothrow) double nextafter(double  , double  );
N    /*
N     * Returns the next representable number after x, in the
N     * direction toward y.
N     */
Nextern _ARMABI float nextafterf(float /*x*/, float /*y*/);
Xextern __declspec(__nothrow) float nextafterf(float  , float  );
N    /*
N     * Returns the next representable number after x, in the
N     * direction toward y.
N     */
Nextern _ARMABI long double nextafterl(long double /*x*/, long double /*y*/);
Xextern __declspec(__nothrow) long double nextafterl(long double  , long double  );
N    /*
N     * Returns the next representable number after x, in the
N     * direction toward y.
N     */
Nextern _ARMABI double nexttoward(double /*x*/, long double /*y*/);
Xextern __declspec(__nothrow) double nexttoward(double  , long double  );
N    /*
N     * Returns the next representable number after x, in the
N     * direction toward y.
N     */
Nextern _ARMABI float nexttowardf(float /*x*/, long double /*y*/);
Xextern __declspec(__nothrow) float nexttowardf(float  , long double  );
N    /*
N     * Returns the next representable number after x, in the
N     * direction toward y.
N     */
Nextern _ARMABI long double nexttowardl(long double /*x*/, long double /*y*/);
Xextern __declspec(__nothrow) long double nexttowardl(long double  , long double  );
N    /*
N     * Returns the next representable number after x, in the
N     * direction toward y.
N     */
Nextern _ARMABI double remainder(double /*x*/, double /*y*/);
Xextern __declspec(__nothrow) double remainder(double  , double  );
N    /*
N     * Returns the remainder of x by y, in the IEEE 754 sense.
N     */
Nextern _ARMABI_FPEXCEPT double rint(double /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) double rint(double  );
N    /*
N     * Rounds x to an integer, in the IEEE 754 sense.
N     */
Nextern _ARMABI double scalbln(double /*x*/, long int /*n*/);
Xextern __declspec(__nothrow) double scalbln(double  , long int  );
N    /*
N     * Compute x times 2^n quickly.
N     */
Nextern _ARMABI float scalblnf(float /*x*/, long int /*n*/);
Xextern __declspec(__nothrow) float scalblnf(float  , long int  );
N    /*
N     * Compute x times 2^n quickly.
N     */
Nextern _ARMABI long double scalblnl(long double /*x*/, long int /*n*/);
Xextern __declspec(__nothrow) long double scalblnl(long double  , long int  );
N    /*
N     * Compute x times 2^n quickly.
N     */
Nextern _ARMABI double scalbn(double /*x*/, int /*n*/);
Xextern __declspec(__nothrow) double scalbn(double  , int  );
N    /*
N     * Compute x times 2^n quickly.
N     */
Nextern _ARMABI float scalbnf(float /*x*/, int /*n*/);
Xextern __declspec(__nothrow) float scalbnf(float  , int  );
N    /*
N     * Compute x times 2^n quickly.
N     */
Nextern _ARMABI long double scalbnl(long double /*x*/, int /*n*/);
Xextern __declspec(__nothrow) long double scalbnl(long double  , int  );
N    /*
N     * Compute x times 2^n quickly.
N     */
N#define signbit(x) \
N    ((sizeof(x) == sizeof(float)) \
N        ? __ARM_signbitf(x) \
N        : __ARM_signbit(x))
X#define signbit(x)     ((sizeof(x) == sizeof(float))         ? __ARM_signbitf(x)         : __ARM_signbit(x))
N    /*
N     * Returns the signbit of x, size independent macro
N     */
N#endif
N
N/* C99 float versions of functions.  math.h has always reserved these
N   identifiers for this purpose (7.13.4). */
Nextern _ARMABI_PURE float _fabsf(float); /* old ARM name */
Xextern __declspec(__nothrow) __attribute__((const)) float _fabsf(float);  
N_ARMABI_INLINE _ARMABI_PURE float fabsf(float __f) { return _fabsf(__f); }
Xinline __declspec(__nothrow) __attribute__((const)) float fabsf(float __f) { return _fabsf(__f); }
Nextern _ARMABI float sinf(float /*x*/);
Xextern __declspec(__nothrow) float sinf(float  );
Nextern _ARMABI float cosf(float /*x*/);
Xextern __declspec(__nothrow) float cosf(float  );
Nextern _ARMABI float tanf(float /*x*/);
Xextern __declspec(__nothrow) float tanf(float  );
Nextern _ARMABI float acosf(float /*x*/);
Xextern __declspec(__nothrow) float acosf(float  );
Nextern _ARMABI float asinf(float /*x*/);
Xextern __declspec(__nothrow) float asinf(float  );
Nextern _ARMABI float atanf(float /*x*/);
Xextern __declspec(__nothrow) float atanf(float  );
Nextern _ARMABI float atan2f(float /*y*/, float /*x*/);
Xextern __declspec(__nothrow) float atan2f(float  , float  );
Nextern _ARMABI float sinhf(float /*x*/);
Xextern __declspec(__nothrow) float sinhf(float  );
Nextern _ARMABI float coshf(float /*x*/);
Xextern __declspec(__nothrow) float coshf(float  );
Nextern _ARMABI float tanhf(float /*x*/);
Xextern __declspec(__nothrow) float tanhf(float  );
Nextern _ARMABI float expf(float /*x*/);
Xextern __declspec(__nothrow) float expf(float  );
Nextern _ARMABI float logf(float /*x*/);
Xextern __declspec(__nothrow) float logf(float  );
Nextern _ARMABI float log10f(float /*x*/);
Xextern __declspec(__nothrow) float log10f(float  );
Nextern _ARMABI float powf(float /*x*/, float /*y*/);
Xextern __declspec(__nothrow) float powf(float  , float  );
Nextern _ARMABI float sqrtf(float /*x*/);
Xextern __declspec(__nothrow) float sqrtf(float  );
Nextern _ARMABI float ldexpf(float /*x*/, int /*exp*/);
Xextern __declspec(__nothrow) float ldexpf(float  , int  );
Nextern _ARMABI float frexpf(float /*value*/, int * /*exp*/) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) float frexpf(float  , int *  ) __attribute__((__nonnull__(2)));
Nextern _ARMABI_PURE float ceilf(float /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) float ceilf(float  );
Nextern _ARMABI_PURE float floorf(float /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) float floorf(float  );
Nextern _ARMABI float fmodf(float /*x*/, float /*y*/);
Xextern __declspec(__nothrow) float fmodf(float  , float  );
Nextern _ARMABI float modff(float /*value*/, float * /*iptr*/) __attribute__((__nonnull__(2)));
Xextern __declspec(__nothrow) float modff(float  , float *  ) __attribute__((__nonnull__(2)));
N
N/* C99 long double versions of functions. */
N/* (also need to have 'using' declarations below) */
N#define _ARMDEFLD1(f) \
N    _ARMABI long double f##l(long double /*x*/)
X#define _ARMDEFLD1(f)     _ARMABI long double f##l(long double  )
N
N#define _ARMDEFLD1P(f, T) \
N    _ARMABI long double f##l(long double /*x*/, T /*p*/)
X#define _ARMDEFLD1P(f, T)     _ARMABI long double f##l(long double  , T  )
N
N#define _ARMDEFLD2(f) \
N    _ARMABI long double f##l(long double /*x*/, long double /*y*/)
X#define _ARMDEFLD2(f)     _ARMABI long double f##l(long double  , long double  )
N
N/*
N * Long double versions of C89 functions can be defined
N * unconditionally, because C89 reserved these names in "future
N * library directions".
N */
N_ARMDEFLD1(acos);
X__declspec(__nothrow) long double acosl(long double );
N_ARMDEFLD1(asin);
X__declspec(__nothrow) long double asinl(long double );
N_ARMDEFLD1(atan);
X__declspec(__nothrow) long double atanl(long double );
N_ARMDEFLD2(atan2);
X__declspec(__nothrow) long double atan2l(long double , long double );
N_ARMDEFLD1(ceil);
X__declspec(__nothrow) long double ceill(long double );
N_ARMDEFLD1(cos);
X__declspec(__nothrow) long double cosl(long double );
N_ARMDEFLD1(cosh);
X__declspec(__nothrow) long double coshl(long double );
N_ARMDEFLD1(exp);
X__declspec(__nothrow) long double expl(long double );
N_ARMDEFLD1(fabs);
X__declspec(__nothrow) long double fabsl(long double );
N_ARMDEFLD1(floor);
X__declspec(__nothrow) long double floorl(long double );
N_ARMDEFLD2(fmod);
X__declspec(__nothrow) long double fmodl(long double , long double );
N_ARMDEFLD1P(frexp, int*) __attribute__((__nonnull__(2)));
X__declspec(__nothrow) long double frexpl(long double , int* ) __attribute__((__nonnull__(2)));
N_ARMDEFLD1P(ldexp, int);
X__declspec(__nothrow) long double ldexpl(long double , int );
N_ARMDEFLD1(log);
X__declspec(__nothrow) long double logl(long double );
N_ARMDEFLD1(log10);
X__declspec(__nothrow) long double log10l(long double );
N_ARMABI long double modfl(long double /*x*/, long double * /*p*/) __attribute__((__nonnull__(2)));
X__declspec(__nothrow) long double modfl(long double  , long double *  ) __attribute__((__nonnull__(2)));
N_ARMDEFLD2(pow);
X__declspec(__nothrow) long double powl(long double , long double );
N_ARMDEFLD1(sin);
X__declspec(__nothrow) long double sinl(long double );
N_ARMDEFLD1(sinh);
X__declspec(__nothrow) long double sinhl(long double );
N_ARMDEFLD1(sqrt);
X__declspec(__nothrow) long double sqrtl(long double );
N_ARMDEFLD1(tan);
X__declspec(__nothrow) long double tanl(long double );
N_ARMDEFLD1(tanh);
X__declspec(__nothrow) long double tanhl(long double );
N
N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)
X#if !0L || 1L
N
N/*
N * C99 float and long double versions of extra-C89 functions.
N */
Nextern _ARMABI float acoshf(float /*x*/);
Xextern __declspec(__nothrow) float acoshf(float  );
N_ARMDEFLD1(acosh);
X__declspec(__nothrow) long double acoshl(long double );
Nextern _ARMABI float asinhf(float /*x*/);
Xextern __declspec(__nothrow) float asinhf(float  );
N_ARMDEFLD1(asinh);
X__declspec(__nothrow) long double asinhl(long double );
Nextern _ARMABI float atanhf(float /*x*/);
Xextern __declspec(__nothrow) float atanhf(float  );
N_ARMDEFLD1(atanh);
X__declspec(__nothrow) long double atanhl(long double );
N_ARMDEFLD2(copysign);
X__declspec(__nothrow) long double copysignl(long double , long double );
Nextern _ARMABI float cbrtf(float /*x*/);
Xextern __declspec(__nothrow) float cbrtf(float  );
N_ARMDEFLD1(cbrt);
X__declspec(__nothrow) long double cbrtl(long double );
Nextern _ARMABI float erff(float /*x*/);
Xextern __declspec(__nothrow) float erff(float  );
N_ARMDEFLD1(erf);
X__declspec(__nothrow) long double erfl(long double );
Nextern _ARMABI float erfcf(float /*x*/);
Xextern __declspec(__nothrow) float erfcf(float  );
N_ARMDEFLD1(erfc);
X__declspec(__nothrow) long double erfcl(long double );
Nextern _ARMABI float expm1f(float /*x*/);
Xextern __declspec(__nothrow) float expm1f(float  );
N_ARMDEFLD1(expm1);
X__declspec(__nothrow) long double expm1l(long double );
Nextern _ARMABI float log1pf(float /*x*/);
Xextern __declspec(__nothrow) float log1pf(float  );
N_ARMDEFLD1(log1p);
X__declspec(__nothrow) long double log1pl(long double );
Nextern _ARMABI float hypotf(float /*x*/, float /*y*/);
Xextern __declspec(__nothrow) float hypotf(float  , float  );
N_ARMDEFLD2(hypot);
X__declspec(__nothrow) long double hypotl(long double , long double );
Nextern _ARMABI float lgammaf(float /*x*/);
Xextern __declspec(__nothrow) float lgammaf(float  );
N_ARMDEFLD1(lgamma);
X__declspec(__nothrow) long double lgammal(long double );
Nextern _ARMABI float remainderf(float /*x*/, float /*y*/);
Xextern __declspec(__nothrow) float remainderf(float  , float  );
N_ARMDEFLD2(remainder);
X__declspec(__nothrow) long double remainderl(long double , long double );
Nextern _ARMABI float rintf(float /*x*/);
Xextern __declspec(__nothrow) float rintf(float  );
N_ARMDEFLD1(rint);
X__declspec(__nothrow) long double rintl(long double );
N
N#endif
N
N#if (defined(__clang__) && !defined(__STRICT_ANSI)) || defined(__USE_C99_MATH)
X#if (0L && !0L) || 1L
N/*
N * Functions new in C99.
N */
Nextern _ARMABI double exp2(double /*x*/); /* * 2.^x. */
Xextern __declspec(__nothrow) double exp2(double  );  
Nextern _ARMABI float exp2f(float /*x*/);
Xextern __declspec(__nothrow) float exp2f(float  );
N_ARMDEFLD1(exp2);
X__declspec(__nothrow) long double exp2l(long double );
Nextern _ARMABI double fdim(double /*x*/, double /*y*/);
Xextern __declspec(__nothrow) double fdim(double  , double  );
Nextern _ARMABI float fdimf(float /*x*/, float /*y*/);
Xextern __declspec(__nothrow) float fdimf(float  , float  );
N_ARMDEFLD2(fdim);
X__declspec(__nothrow) long double fdiml(long double , long double );
N#ifdef __FP_FAST_FMA
S#define FP_FAST_FMA
N#endif
N#ifdef __FP_FAST_FMAF
N#define FP_FAST_FMAF
N#endif
N#ifdef __FP_FAST_FMAL
S#define FP_FAST_FMAL
N#endif
Nextern _ARMABI double fma(double /*x*/, double /*y*/, double /*z*/);
Xextern __declspec(__nothrow) double fma(double  , double  , double  );
Nextern _ARMABI float fmaf(float /*x*/, float /*y*/, float /*z*/);
Xextern __declspec(__nothrow) float fmaf(float  , float  , float  );
N#ifdef __HAVE_LONGDOUBLE
N_ARMABI_INLINE _ARMABI long double fmal(long double __x, long double __y, long double __z) \
N    { return (long double)fma((double)__x, (double)__y, (double)__z); }
Xinline __declspec(__nothrow) long double fmal(long double __x, long double __y, long double __z)     { return (long double)fma((double)__x, (double)__y, (double)__z); }
N#endif
Nextern _ARMABI_FPEXCEPT double fmax(double /*x*/, double /*y*/);
Xextern __declspec(__nothrow) __attribute__((const)) double fmax(double  , double  );
Nextern _ARMABI_FPEXCEPT float fmaxf(float /*x*/, float /*y*/);
Xextern __declspec(__nothrow) __attribute__((const)) float fmaxf(float  , float  );
N_ARMDEFLD2(fmax);
X__declspec(__nothrow) long double fmaxl(long double , long double );
Nextern _ARMABI_FPEXCEPT double fmin(double /*x*/, double /*y*/);
Xextern __declspec(__nothrow) __attribute__((const)) double fmin(double  , double  );
Nextern _ARMABI_FPEXCEPT float fminf(float /*x*/, float /*y*/);
Xextern __declspec(__nothrow) __attribute__((const)) float fminf(float  , float  );
N_ARMDEFLD2(fmin);
X__declspec(__nothrow) long double fminl(long double , long double );
Nextern _ARMABI double log2(double /*x*/); /* * log base 2 of x. */
Xextern __declspec(__nothrow) double log2(double  );  
Nextern _ARMABI float log2f(float /*x*/);
Xextern __declspec(__nothrow) float log2f(float  );
N_ARMDEFLD1(log2);
X__declspec(__nothrow) long double log2l(long double );
Nextern _ARMABI long lrint(double /*x*/);
Xextern __declspec(__nothrow) long lrint(double  );
Nextern _ARMABI long lrintf(float /*x*/);
Xextern __declspec(__nothrow) long lrintf(float  );
N#ifdef __HAVE_LONGDOUBLE
N_ARMABI_INLINE _ARMABI long lrintl(long double __x) \
N    { return lrint((double)__x); }
Xinline __declspec(__nothrow) long lrintl(long double __x)     { return lrint((double)__x); }
N#endif
Nextern _ARMABI __LONGLONG llrint(double /*x*/);
Xextern __declspec(__nothrow) long long llrint(double  );
Nextern _ARMABI __LONGLONG llrintf(float /*x*/);
Xextern __declspec(__nothrow) long long llrintf(float  );
N#ifdef __HAVE_LONGDOUBLE
N_ARMABI_INLINE _ARMABI __LONGLONG llrintl(long double __x) \
N    { return llrint((double)__x); }
Xinline __declspec(__nothrow) long long llrintl(long double __x)     { return llrint((double)__x); }
N#endif
Nextern _ARMABI long lround(double /*x*/);
Xextern __declspec(__nothrow) long lround(double  );
Nextern _ARMABI long lroundf(float /*x*/);
Xextern __declspec(__nothrow) long lroundf(float  );
N#ifdef __HAVE_LONGDOUBLE
N_ARMABI_INLINE _ARMABI long lroundl(long double __x) \
N    { return lround((double)__x); }
Xinline __declspec(__nothrow) long lroundl(long double __x)     { return lround((double)__x); }
N#endif
Nextern _ARMABI __LONGLONG llround(double /*x*/);
Xextern __declspec(__nothrow) long long llround(double  );
Nextern _ARMABI __LONGLONG llroundf(float /*x*/);
Xextern __declspec(__nothrow) long long llroundf(float  );
N#ifdef __HAVE_LONGDOUBLE
N_ARMABI_INLINE _ARMABI __LONGLONG llroundl(long double __x) \
N    { return llround((double)__x); }
Xinline __declspec(__nothrow) long long llroundl(long double __x)     { return llround((double)__x); }
N#endif
Nextern _ARMABI_PURE double nan(const char */*tagp*/);
Xextern __declspec(__nothrow) __attribute__((const)) double nan(const char * );
Nextern _ARMABI_PURE float nanf(const char */*tagp*/);
Xextern __declspec(__nothrow) __attribute__((const)) float nanf(const char * );
N#ifdef __HAVE_LONGDOUBLE
N_ARMABI_INLINE _ARMABI_PURE long double nanl(const char *__t) \
N    { return (long double)nan(__t); }
Xinline __declspec(__nothrow) __attribute__((const)) long double nanl(const char *__t)     { return (long double)nan(__t); }
N#endif
N#if defined(_WANT_SNAN) && defined(__SUPPORT_SNAN__)
X#if 0L && 0L
Sextern _ARMABI_PURE double nans(const char */*tagp*/);
Sextern _ARMABI_PURE float nansf(const char */*tagp*/);
S#ifdef __HAVE_LONGDOUBLE
S_ARMABI_INLINE _ARMABI_FPEXCEPT long double nansl(const char *__t) \
S    { return (long double)nans(__t); }
X_ARMABI_INLINE _ARMABI_FPEXCEPT long double nansl(const char *__t)     { return (long double)nans(__t); }
S#endif
N#endif 
Nextern _ARMABI_FPEXCEPT double nearbyint(double /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) double nearbyint(double  );
Nextern _ARMABI_FPEXCEPT float nearbyintf(float /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) float nearbyintf(float  );
N_ARMDEFLD1(nearbyint);
X__declspec(__nothrow) long double nearbyintl(long double );
Nextern  double remquo(double /*x*/, double /*y*/, int */*quo*/);
Nextern  float remquof(float /*x*/, float /*y*/, int */*quo*/);
N#ifdef __HAVE_LONGDOUBLE
N_ARMABI_INLINE long double remquol(long double __x, long double __y, int *__q) \
N    { return (long double)remquo((double)__x, (double)__y, __q); }
Xinline long double remquol(long double __x, long double __y, int *__q)     { return (long double)remquo((double)__x, (double)__y, __q); }
N#endif
Nextern _ARMABI_FPEXCEPT double round(double /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) double round(double  );
Nextern _ARMABI_FPEXCEPT float roundf(float /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) float roundf(float  );
N_ARMDEFLD1(round);
X__declspec(__nothrow) long double roundl(long double );
Nextern _ARMABI double tgamma(double /*x*/); /* * The gamma function of x. */
Xextern __declspec(__nothrow) double tgamma(double  );  
Nextern _ARMABI float tgammaf(float /*x*/);
Xextern __declspec(__nothrow) float tgammaf(float  );
N_ARMDEFLD1(tgamma);
X__declspec(__nothrow) long double tgammal(long double );
Nextern _ARMABI_FPEXCEPT double trunc(double /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) double trunc(double  );
Nextern _ARMABI_FPEXCEPT float truncf(float /*x*/);
Xextern __declspec(__nothrow) __attribute__((const)) float truncf(float  );
N_ARMDEFLD1(trunc);
X__declspec(__nothrow) long double truncl(long double );
N#endif
N
N#undef _ARMDEFLD1
N#undef _ARMDEFLD1P
N#undef _ARMDEFLD2
N
N#if defined(__cplusplus) && ((!defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)) || defined(__ARMCOMPILER_LIBCXX))
X#if 0L && ((!0L || 1L) || 0L)
S  extern "C++" {
S    inline int (fpclassify)(double __x) { return fpclassify(__x); }
S    inline bool (isfinite)(double __x) { return isfinite(__x); }
S    inline bool (isgreater)(double __x, double __y) { return isgreater(__x, __y); }
S    inline bool (isgreaterequal)(double __x, double __y) { return isgreaterequal(__x, __y); }
S    inline bool (isinf)(double __x) { return isinf(__x); }
S    inline bool (isless)(double __x, double __y) { return isless(__x, __y); }
S    inline bool (islessequal)(double __x, double __y) { return islessequal(__x, __y); }
S    inline bool (islessgreater)(double __x, double __y) { return islessgreater(__x, __y); }
S    inline bool (isnan)(double __x) { return isnan(__x); }
S    inline bool (isnormal)(double __x) { return isnormal(__x); }
S    inline bool (isunordered)(double __x, double __y) { return isunordered(__x, __y); }
S
S  }
N#endif
N
N#if defined(__cplusplus) && !defined(__ARMCOMPILER_LIBCXX)
X#if 0L && !0L
S  extern "C++" {
S    inline float abs(float __x)   { return fabsf(__x); }
S    inline float acos(float __x)  { return acosf(__x); }
S    inline float asin(float __x)  { return asinf(__x); }
S    inline float atan(float __x)  { return atanf(__x); }
S    inline float atan2(float __y, float __x)    { return atan2f(__y,__x); }
S    inline float ceil(float __x)  { return ceilf(__x); }
S    inline float cos(float __x)   { return cosf(__x); }
S    inline float cosh(float __x)  { return coshf(__x); }
S    inline float exp(float __x)   { return expf(__x); }
S    inline float fabs(float __x)  { return fabsf(__x); }
S    inline float floor(float __x) { return floorf(__x); }
S    inline float fmod(float __x, float __y)     { return fmodf(__x, __y); }
S    float frexp(float __x, int* __exp) __attribute__((__nonnull__(2)));
S    inline float frexp(float __x, int* __exp)   { return frexpf(__x, __exp); }
S    inline float ldexp(float __x, int __exp)    { return ldexpf(__x, __exp);}
S    inline float log(float __x)   { return logf(__x); }
S    inline float log10(float __x) { return log10f(__x); }
S    float modf(float __x, float* __iptr) __attribute__((__nonnull__(2)));
S    inline float modf(float __x, float* __iptr) { return modff(__x, __iptr); }
S    inline float pow(float __x, float __y)      { return powf(__x,__y); }
S    inline float pow(float __x, int __y)     { return powf(__x, (float)__y); }
S    inline float sin(float __x)   { return sinf(__x); }
S    inline float sinh(float __x)  { return sinhf(__x); }
S    inline float sqrt(float __x)  { return sqrtf(__x); }
S    inline float _sqrt(float __x) { return _sqrtf(__x); }
S    inline float tan(float __x)   { return tanf(__x); }
S    inline float tanh(float __x)  { return tanhf(__x); }
S
S    inline double abs(double __x) { return fabs(__x); }
S    inline double pow(double __x, int __y)
S                { return pow(__x, (double) __y); }
S
S#ifdef __HAVE_LONGDOUBLE
S    inline long double abs(long double __x)
S                { return (long double)fabsl(__x); }
S    inline long double acos(long double __x)
S                { return (long double)acosl(__x); }
S    inline long double asin(long double __x)
S                { return (long double)asinl(__x); }
S    inline long double atan(long double __x)
S                { return (long double)atanl(__x); }
S    inline long double atan2(long double __y, long double __x)
S                { return (long double)atan2l(__y, __x); }
S    inline long double ceil(long double __x)
S                { return (long double)ceill( __x); }
S    inline long double cos(long double __x)
S                { return (long double)cosl(__x); }
S    inline long double cosh(long double __x)
S                { return (long double)coshl(__x); }
S    inline long double exp(long double __x)
S                { return (long double)expl(__x); }
S    inline long double fabs(long double __x)
S                { return (long double)fabsl(__x); }
S    inline long double floor(long double __x)
S                { return (long double)floorl(__x); }
S    inline long double fmod(long double __x, long double __y)
S                { return (long double)fmodl(__x, __y); }
S    long double frexp(long double __x, int* __p) __attribute__((__nonnull__(2)));
S    inline long double frexp(long double __x, int* __p)
S                { return (long double)frexpl(__x, __p); }
S    inline long double ldexp(long double __x, int __exp)
S                { return (long double)ldexpl(__x, __exp); }
S    inline long double log(long double __x)
S                { return (long double)logl(__x); }
S    inline long double log10(long double __x)
S                { return (long double)log10l(__x); }
S    long double modf(long double __x, long double* __p) __attribute__((__nonnull__(2)));
S    inline long double modf(long double __x, long double* __p)
S                { return (long double)modfl(__x, __p); }
S    inline long double pow(long double __x, long double __y)
S                { return (long double)powl(__x, __y); }
S    inline long double pow(long double __x, int __y)
S                { return (long double)powl(__x, __y); }
S    inline long double sin(long double __x)
S                { return (long double)sinl(__x); }
S    inline long double sinh(long double __x)
S                { return (long double)sinhl(__x); }
S    inline long double sqrt(long double __x)
S                { return (long double)sqrtl(__x); }
S    inline long double _sqrt(long double __x)
S                { return (long double)_sqrt((double) __x); }
S    inline long double tan(long double __x)
S                { return (long double)tanl(__x); }
S    inline long double tanh(long double __x)
S                { return (long double)tanhl(__x); }
S#endif
S
S#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)
S    inline float acosh(float __x) { return acoshf(__x); }
S    inline float asinh(float __x) { return asinhf(__x); }
S    inline float atanh(float __x) { return atanhf(__x); }
S    inline float cbrt(float __x) { return cbrtf(__x); }
S    inline float erf(float __x) { return erff(__x); }
S    inline float erfc(float __x) { return erfcf(__x); }
S    inline float expm1(float __x) { return expm1f(__x); }
S    inline float log1p(float __x) { return log1pf(__x); }
S    inline float hypot(float __x, float __y) { return hypotf(__x, __y); }
S    inline float lgamma(float __x) { return lgammaf(__x); }
S    inline float remainder(float __x, float __y) { return remainderf(__x, __y); }
S    inline float rint(float __x) { return rintf(__x); }
S#endif
S
S#ifdef __USE_C99_MATH
S    inline float exp2(float __x) { return exp2f(__x); }
S    inline float fdim(float __x, float __y) { return fdimf(__x, __y); }
S    inline float fma(float __x, float __y, float __z) { return fmaf(__x, __y, __z); }
S    inline float fmax(float __x, float __y) { return fmaxf(__x, __y); }
S    inline float fmin(float __x, float __y) { return fminf(__x, __y); }
S    inline float log2(float __x) { return log2f(__x); }
S    inline _ARMABI long lrint(float __x) { return lrintf(__x); }
S    inline _ARMABI __LONGLONG llrint(float __x) { return llrintf(__x); }
S    inline _ARMABI long lround(float __x) { return lroundf(__x); }
S    inline _ARMABI __LONGLONG llround(float __x) { return llroundf(__x); }
S    inline _ARMABI_FPEXCEPT float nearbyint(float __x) { return nearbyintf(__x); }
S    inline float remquo(float __x, float __y, int *__q) { return remquof(__x, __y, __q); }
S    inline _ARMABI_FPEXCEPT float round(float __x) { return roundf(__x); }
S    inline float tgamma(float __x) { return tgammaf(__x); }
S    inline _ARMABI_FPEXCEPT float trunc(float __x) { return truncf(__x); }
S
S    inline int (fpclassify)(float __x) { return fpclassify(__x); }
S    inline bool (isfinite)(float __x) { return isfinite(__x); }
S    inline bool (isgreater)(float __x, float __y) { return isgreater(__x, __y); }
S    inline bool (isgreaterequal)(float __x, float __y) { return isgreaterequal(__x, __y); }
S    inline bool (isinf)(float __x) { return isinf(__x); }
S    inline bool (isless)(float __x, float __y) { return isless(__x, __y); }
S    inline bool (islessequal)(float __x, float __y) { return islessequal(__x, __y); }
S    inline bool (islessgreater)(float __x, float __y) { return islessgreater(__x, __y); }
S    inline bool (isnan)(float __x) { return isnan(__x); }
S    inline bool (isnormal)(float __x) { return isnormal(__x); }
S    inline bool (isunordered)(float __x, float __y) { return isunordered(__x, __y); }
S
S#ifdef __HAVE_LONGDOUBLE
S    inline long double acosh(long double __x) { return acoshl(__x); }
S    inline long double asinh(long double __x) { return asinhl(__x); }
S    inline long double atanh(long double __x) { return atanhl(__x); }
S    inline long double cbrt(long double __x) { return cbrtl(__x); }
S    inline long double erf(long double __x) { return erfl(__x); }
S    inline long double erfc(long double __x) { return erfcl(__x); }
S    inline long double expm1(long double __x) { return expm1l(__x); }
S    inline long double log1p(long double __x) { return log1pl(__x); }
S    inline long double hypot(long double __x, long double __y) { return hypotl(__x, __y); }
S    inline long double lgamma(long double __x) { return lgammal(__x); }
S    inline long double remainder(long double __x, long double __y) { return remainderl(__x, __y); }
S    inline long double rint(long double __x) { return rintl(__x); }
S    inline long double exp2(long double __x) { return exp2l(__x); }
S    inline long double fdim(long double __x, long double __y) { return fdiml(__x, __y); }
S    inline long double fma(long double __x, long double __y, long double __z) { return fmal(__x, __y, __z); }
S    inline long double fmax(long double __x, long double __y) { return fmaxl(__x, __y); }
S    inline long double fmin(long double __x, long double __y) { return fminl(__x, __y); }
S    inline long double log2(long double __x) { return log2l(__x); }
S    inline _ARMABI long lrint(long double __x) { return lrintl(__x); }
S    inline _ARMABI __LONGLONG llrint(long double __x) { return llrintl(__x); }
S    inline _ARMABI long lround(long double __x) { return lroundl(__x); }
S    inline _ARMABI __LONGLONG llround(long double __x) { return llroundl(__x); }
S    inline _ARMABI_FPEXCEPT long double nearbyint(long double __x) { return nearbyintl(__x); }
S    inline long double remquo(long double __x, long double __y, int *__q) { return remquol(__x, __y, __q); }
S    inline _ARMABI_FPEXCEPT long double round(long double __x) { return roundl(__x); }
S    inline long double tgamma(long double __x) { return tgammal(__x); }
S    inline _ARMABI_FPEXCEPT long double trunc(long double __x) { return truncl(__x); }
S    inline int (fpclassify)(long double __x) { return fpclassify(__x); }
S    inline bool (isfinite)(long double __x) { return isfinite(__x); }
S    inline bool (isgreater)(long double __x, long double __y) { return isgreater(__x, __y); }
S    inline bool (isgreaterequal)(long double __x, long double __y) { return isgreaterequal(__x, __y); }
S    inline bool (isinf)(long double __x) { return isinf(__x); }
S    inline bool (isless)(long double __x, long double __y) { return isless(__x, __y); }
S    inline bool (islessequal)(long double __x, long double __y) { return islessequal(__x, __y); }
S    inline bool (islessgreater)(long double __x, long double __y) { return islessgreater(__x, __y); }
S    inline bool (isnan)(long double __x) { return isnan(__x); }
S    inline bool (isnormal)(long double __x) { return isnormal(__x); }
S    inline bool (isunordered)(long double __x, long double __y) { return isunordered(__x, __y); }
S#endif
S
S#undef fpclassify
S#undef isfinite
S#undef isgreater
S#undef isgreaterequal
S#undef isinf
S#undef isless
S#undef islessequal
S#undef islessgreater
S#undef isnan
S#undef isnormal
S#undef isunordered
S
S#endif
S
S  }
N#endif
N
N    #ifdef __cplusplus
S        }  /* extern "C" */
S      }  /* namespace std */
N    #endif
N  #endif /* __MATH_DECLS */
N
N  #if _AEABI_PORTABILITY_LEVEL != 0 && !defined _AEABI_PORTABLE
X  #if _AEABI_PORTABILITY_LEVEL != 0 && !0L
S    #define _AEABI_PORTABLE
N  #endif
N
N  #if defined(__cplusplus) && !defined(__MATH_NO_EXPORTS)
X  #if 0L && !0L
S    using ::std::__use_accurate_range_reduction;
S    #ifndef __ARMCOMPILER_LIBCXX
S      using ::std::abs;
S    #endif
S    using ::std::acos;
S    using ::std::asin;
S    using ::std::atan2;
S    using ::std::atan;
S    using ::std::ceil;
S    using ::std::cos;
S    using ::std::cosh;
S    using ::std::exp;
S    using ::std::fabs;
S    using ::std::floor;
S    using ::std::fmod;
S    using ::std::frexp;
S    using ::std::ldexp;
S    using ::std::log10;
S    using ::std::log;
S    using ::std::modf;
S    using ::std::pow;
S    using ::std::sin;
S    using ::std::sinh;
S    using ::std::sqrt;
S    using ::std::_sqrt;
S    using ::std::_sqrtf;
S    using ::std::tan;
S    using ::std::tanh;
S    using ::std::_fabsf;
S    /* C99 float and long double versions in already-C89-reserved namespace */
S    using ::std::acosf;
S    using ::std::acosl;
S    using ::std::asinf;
S    using ::std::asinl;
S    using ::std::atan2f;
S    using ::std::atan2l;
S    using ::std::atanf;
S    using ::std::atanl;
S    using ::std::ceilf;
S    using ::std::ceill;
S    using ::std::cosf;
S    using ::std::coshf;
S    using ::std::coshl;
S    using ::std::cosl;
S    using ::std::expf;
S    using ::std::expl;
S    using ::std::fabsf;
S    using ::std::fabsl;
S    using ::std::floorf;
S    using ::std::floorl;
S    using ::std::fmodf;
S    using ::std::fmodl;
S    using ::std::frexpf;
S    using ::std::frexpl;
S    using ::std::ldexpf;
S    using ::std::ldexpl;
S    using ::std::log10f;
S    using ::std::log10l;
S    using ::std::logf;
S    using ::std::logl;
S    using ::std::modff;
S    using ::std::modfl;
S    using ::std::powf;
S    using ::std::powl;
S    using ::std::sinf;
S    using ::std::sinhf;
S    using ::std::sinhl;
S    using ::std::sinl;
S    using ::std::sqrtf;
S    using ::std::sqrtl;
S    using ::std::tanf;
S    using ::std::tanhf;
S    using ::std::tanhl;
S    using ::std::tanl;
S    #if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)
S      /* C99 additions which for historical reasons appear in non-strict mode */
S      using ::std::acosh;
S      using ::std::asinh;
S      using ::std::atanh;
S      using ::std::cbrt;
S      using ::std::copysign;
S      using ::std::copysignf;
S      using ::std::erf;
S      using ::std::erfc;
S      using ::std::expm1;
S      using ::std::hypot;
S      using ::std::ilogb;
S      using ::std::ilogbf;
S      using ::std::ilogbl;
S      using ::std::lgamma;
S      using ::std::log1p;
S      using ::std::logb;
S      using ::std::logbf;
S      using ::std::logbl;
S      using ::std::nextafter;
S      using ::std::nextafterf;
S      using ::std::nextafterl;
S      using ::std::nexttoward;
S      using ::std::nexttowardf;
S      using ::std::nexttowardl;
S      using ::std::remainder;
S      using ::std::rint;
S      using ::std::scalbln;
S      using ::std::scalblnf;
S      using ::std::scalblnl;
S      using ::std::scalbn;
S      using ::std::scalbnf;
S      using ::std::scalbnl;
S      using ::std::math_errhandling;
S      using ::std::acoshf;
S      using ::std::acoshl;
S      using ::std::asinhf;
S      using ::std::asinhl;
S      using ::std::atanhf;
S      using ::std::atanhl;
S      using ::std::copysignl;
S      using ::std::cbrtf;
S      using ::std::cbrtl;
S      using ::std::erff;
S      using ::std::erfl;
S      using ::std::erfcf;
S      using ::std::erfcl;
S      using ::std::expm1f;
S      using ::std::expm1l;
S      using ::std::log1pf;
S      using ::std::log1pl;
S      using ::std::hypotf;
S      using ::std::hypotl;
S      using ::std::lgammaf;
S      using ::std::lgammal;
S      using ::std::remainderf;
S      using ::std::remainderl;
S      using ::std::rintf;
S      using ::std::rintl;
S      /* New in C99. */
S      using ::std::float_t;
S      using ::std::double_t;
S    #endif
S    #if (defined(__clang__) && !defined(__STRICT_ANSI)) || defined(__USE_C99_MATH)
S      /* Functions new in C99. */
S      using ::std::exp2;
S      using ::std::exp2f;
S      using ::std::exp2l;
S      using ::std::fdim;
S      using ::std::fdimf;
S      using ::std::fdiml;
S      using ::std::fma;
S      using ::std::fmaf;
S#ifdef __HAVE_LONGDOUBLE
S      using ::std::fmal;
S#endif
S      using ::std::fmax;
S      using ::std::fmaxf;
S      using ::std::fmaxl;
S      using ::std::fmin;
S      using ::std::fminf;
S      using ::std::fminl;
S      using ::std::log2;
S      using ::std::log2f;
S      using ::std::log2l;
S      using ::std::lrint;
S      using ::std::lrintf;
S#ifdef __HAVE_LONGDOUBLE
S      using ::std::lrintl;
S#endif
S      using ::std::llrint;
S      using ::std::llrintf;
S#ifdef __HAVE_LONGDOUBLE
S      using ::std::llrintl;
S#endif
S      using ::std::lround;
S      using ::std::lroundf;
S#ifdef __HAVE_LONGDOUBLE
S      using ::std::lroundl;
S#endif
S      using ::std::llround;
S      using ::std::llroundf;
S#ifdef __HAVE_LONGDOUBLE
S      using ::std::llroundl;
S#endif
S      using ::std::nan;
S      using ::std::nanf;
S#ifdef __HAVE_LONGDOUBLE
S      using ::std::nanl;
S#endif
S      using ::std::nearbyint;
S      using ::std::nearbyintf;
S      using ::std::nearbyintl;
S      using ::std::remquo;
S      using ::std::remquof;
S#ifdef __HAVE_LONGDOUBLE
S      using ::std::remquol;
S#endif
S      using ::std::round;
S      using ::std::roundf;
S      using ::std::roundl;
S      using ::std::tgamma;
S      using ::std::tgammaf;
S      using ::std::tgammal;
S      using ::std::trunc;
S      using ::std::truncf;
S      using ::std::truncl;
S    #endif
S
S    #if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)
S      using ::std::fpclassify;
S      using ::std::isfinite;
S      using ::std::isgreater;
S      using ::std::isgreaterequal;
S      using ::std::isinf;
S      using ::std::isless;
S      using ::std::islessequal;
S      using ::std::islessgreater;
S      using ::std::isnan;
S      using ::std::isnormal;
S      using ::std::isunordered;
S    #endif
N  #endif
N
N#undef __LONGLONG
N
N#endif /* __math_h */
N
N/* end of math.h */
L 63 "..\..\User\bsp\bsp.h" 2
N#include "RTL.h"
L 1 "..\..\User\RTL.h" 1
N/*----------------------------------------------------------------------------
N *      RL-ARM - A P I 
N *----------------------------------------------------------------------------
N *      Name:    RTL.H 
N *      Purpose: Application Programming Interface 
N *      Rev.:    V4.73
N *----------------------------------------------------------------------------
N *      This code is part of the RealView Run-Time Library.
N *      Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved.
N *---------------------------------------------------------------------------*/
N
N#ifndef __RTL_H__
N#define __RTL_H__
N//#include "port.h"
N
N
Ntypedef signed char     S8;
Ntypedef unsigned char   U8;
Ntypedef short           S16;
Ntypedef unsigned short  U16;
Ntypedef int             S32;
Ntypedef unsigned int    U32;
Ntypedef long long       S64;
Ntypedef unsigned long long U64;
Ntypedef unsigned char   BIT;
Ntypedef unsigned int    BOOL;
N
N
N
N#endif
N 
L 64 "..\..\User\bsp\bsp.h" 2
N#ifndef TRUE
N	#define TRUE  1
N#endif
N
N#ifndef FALSE
N	#define FALSE 0
N#endif
N
N/*
N	EXTI9_5_IRQHandler 的中断服务程序分散在几个独立的 bsp文件中。
N	需要整合到 stm32f4xx_it.c 中。
N
N	定义下面行表示EXTI9_5_IRQHandler入口函数集中放到 stm32f4xx_it.c。
N*/
N#define EXTI9_5_ISR_MOVE_OUT
N
N#define DEBUG_GPS_TO_COM1	/* 打印GPS数据到串口1 */
N
N/* 通过取消注释或者添加注释的方式控制是否包含底层驱动模块 */
N
N#include "bsp_usart.h"
L 1 "..\..\User\bsp\BSP\bsp_usart.h" 1
N/*
N*********************************************************************************************************
N*	                                  
N*	模块名称 : 串口驱动模块    
N*	文件名称 : bsp_usart.h
N*	版    本 : V2.0
N*	说    明 : 头文件
N*
N*	Copyright (C), 2010-2011, 安富莱电子 www.armfly.com
N*
N*********************************************************************************************************
N*/
N
N#ifndef __BSP_USART_H
N#define __BSP_USART_H
N
N#define COM1   1
N#define COM2   2
N#define COM3   3
N#define COM4   4
N#define COM5   5
N#define COM6   6
N#define CAN    7
N//队列数据缓存区大小
N#define UART_BUF_LEN	0x3ff
N
N#define BJF		1
N#define TEK 	0
Nextern short LandMarkID;
Ntypedef struct 
N{
N	unsigned char  RxBuf[UART_BUF_LEN+1];  //接收队列数据缓存区
X	unsigned char  RxBuf[0x3ff+1];  
N	unsigned char  TxBuf[UART_BUF_LEN+1];  //发送队列数据缓存区
X	unsigned char  TxBuf[0x3ff+1];  
N    volatile unsigned short RxBuf_In;	   //接收队列入列位置
N	volatile unsigned short RxBuf_Out;	   //接收队列出列位置
N	volatile unsigned short TxBuf_In;	   //发送队列入列位置
N	volatile unsigned short TxBuf_Out;	   //发送队列出列位置
N}UartStruct;
N
Ntypedef struct 
N{
N	float angular_velocity_x;
N	float angular_velocity_y;
N	float angular_velocity_z;
N	
N	float linear_acceleration_x;
N	float linear_acceleration_y;
N	float linear_acceleration_z;
N	
N	float angular_roll;
N	float angular_pitch;	 
N	float angular_yaw;//角度
N	
N	short angular_x;
N	short angular_y;
N	int	  angular_count;
N}Imu_msg;
N
Nextern Imu_msg imu_msg;
N
N
Nextern void Init_LightSensor(void);
Nextern void bsp_InitUart(void);
Nextern void Uart_Printf(unsigned char UartID, const char *fmt,...);
Nextern void SetZigbee_BaudRate_38400(void);
Nextern void ProcessDataFormUart1(void);
Nextern void ProcessDataFormUartCard(void);
Nextern void ProcessDataFormUartSlam(void);
Nextern void ProcessDataFormUartGoya(void);
Nextern void ProcessDataFormUartQR(void);
Nextern void RFID_Process_TEK(unsigned char *buff,unsigned short len,unsigned short userDataLen);
Nextern void RFID_Process_BJF(unsigned char *buff,unsigned short len,unsigned short userDataLen);
Nextern unsigned int ReadUart(unsigned char UartID,unsigned char *buff,unsigned int length);
Nextern void WriteUart(unsigned char UartID,unsigned char *buff,unsigned int length);
N#endif
N
N
L 85 "..\..\User\bsp\bsp.h" 2
N#include "bsp_can.h"
L 1 "..\..\User\bsp\BSP\bsp_can.h" 1
N/*
N*********************************************************************************************************
N*	                                  
N*	模块名称 : CAN网络演示程序。
N*	文件名称 : bsp_can.h
N*	版    本 : V1.0
N*	说    明 : 头文件
N*
N*********************************************************************************************************
N*/
N#ifndef _BSP_CAN_H
N#define _BSP_CAN_H
N
N#include "stm32f4xx_can.h"
N#include "bsp.h"
L 1 "..\..\User\bsp\bsp.h" 1
N/*
N*********************************************************************************************************
N*
N*	模块名称 : 底层驱动模块
N*	文件名称 : bsp.h
N*	版    本 : V1.0
N*	说    明 : 这是底层驱动模块所有的h文件的汇总文件。
N*	 	       应用程序只需 #include bsp.h 即可,不需要#include 每个模块的 h 文件
N*
N*	修改记录 :
N*		版本号  日期         作者    说明
N*		v1.0    2012-12-17  Eric2013  ST固件库V1.0.2版本。
N*	
N*********************************************************************************************************
N*/
N
N#ifndef _BSP_H_
S#define _BSP_H_
S
S#define STM32_V5
S//#define STM32_X3
S
S
S/* 检查是否定义了开发板型号 */
S#if !defined (STM32_V5) && !defined (STM32_X3)
S	#error "Please define the board model : STM32_X3 or STM32_V5"
S#endif
S
S/* 定义 BSP 版本号 */
S#define __STM32F1_BSP_VERSION		"1.1"
S
S/* CPU空闲时执行的函数 */
S//#define CPU_IDLE()		bsp_Idle()
S
S/* 使能在源文件中使用uCOS-III的函数, 这里的源文件主要是指BSP驱动文件 */
S#define uCOS_EN       1
S
S#if uCOS_EN == 1    
S	#include "os.h"   
S
S	#define  ENABLE_INT()      OS_CRITICAL_EXIT()     /* 使能全局中断 */
S	#define  DISABLE_INT()     OS_CRITICAL_ENTER()    /* 禁止全局中断 */
S#else
S	/* 开关全局中断的宏 */
S	#define ENABLE_INT()	__set_PRIMASK(0)	/* 使能全局中断 */
S	#define DISABLE_INT()	__set_PRIMASK(1)	/* 禁止全局中断 */
S#endif
S
S/* 这个宏仅用于调试阶段排错 */
S#define BSP_Printf		printf
S//#define BSP_Printf(...)
S
S#include "stm32f4xx.h"
S#include <stdio.h>
S#include <string.h>
S#include <stdlib.h>
S#include "stm32f4xx_can.h"
S#include "stm32f4xx_conf.h"
S
S#include "stdbool.h"
S#include <stdarg.h>
S#include  <math.h>
S#include "RTL.h"
S#ifndef TRUE
S	#define TRUE  1
S#endif
S
S#ifndef FALSE
S	#define FALSE 0
S#endif
S
S/*
S	EXTI9_5_IRQHandler 的中断服务程序分散在几个独立的 bsp文件中。
S	需要整合到 stm32f4xx_it.c 中。
S
S	定义下面行表示EXTI9_5_IRQHandler入口函数集中放到 stm32f4xx_it.c。
S*/
S#define EXTI9_5_ISR_MOVE_OUT
S
S#define DEBUG_GPS_TO_COM1	/* 打印GPS数据到串口1 */
S
S/* 通过取消注释或者添加注释的方式控制是否包含底层驱动模块 */
S
S#include "bsp_usart.h"
S#include "bsp_can.h"
S#include "bsp_usart.h"
S#include "bsp_cpu_flash.h"
S#include "bsp_exti.h"
S#include "bsp_wwdg.h"
S#include "bsp_iwdg.h"
S#include "bsp_spi.h"
S#include "bsp_gpio.h"
S#include "tcp_server.h"
S
S#include "ARC-GLC_IODefine.h"
S#include "Laser.h"
S#include "Calculation.h"
S#include "Paramater.h"
S#include "RunCore.h"
S#include "CommunicationForCenter.h"
S#include "SHOW.h"
S#include "ModbusHMI.h"
S#include "user_setup.h"
S#include "user_motor.h"
S#include "user.h"
S
S#include "CanSensor.h"
S#include "Vision.h"
S#include "Camera.h"
S
S#include "HardDifferential.h"
S
S#include "Trackless.h"
S#include "QRcode.h"
S
S#include "ForkLift.h"
S#include "MovableLifterArm.h"
S#include "DoubleSMT.h"
S#include "SMT.h"
S#include "ch_serial.h"
S
S
Svoid bsp_Init(void);
Svoid bsp_DelayMS(uint32_t _ulDelayTime);
Svoid bsp_DelayUS(uint32_t _ulDelayTime);
Svoid BSP_Tick_Init (void);
S
S/**信号量***/
Sextern OS_SEM RFIDSEM;
Sextern int InitFlag;
S
S#define PI		3.1415926f
S
N#endif
N
N/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/
L 16 "..\..\User\bsp\BSP\bsp_can.h" 2
N#define CAN_BUF_LEN	0xf
Ntypedef struct
N{
N	CanTxMsg g_tCanTxMsg;	/* 用于发送 */
N	CanRxMsg g_tCanRxMsg;	/* 用于接收 */	
N	unsigned char  RxBuf[CAN_BUF_LEN+1];
X	unsigned char  RxBuf[0xf+1];
N	unsigned char  TxBuf[CAN_BUF_LEN+1];
X	unsigned char  TxBuf[0xf+1];
N    volatile unsigned short RxBuf_In;
N	volatile unsigned short RxBuf_Out;
N	volatile unsigned short TxBuf_In;
N	volatile unsigned short TxBuf_Out;	
N}CANStruct;
N
N
Ntypedef struct
N{
N	//电池1
N	u16 msg1;
N	u16 msg2;
N	u16 msg3;
N	u16 msg4;
N	u16 msg5;
N	u16 msg6;
N	u16 msg7;
N	u16 msg8;
N	
N	u16 msg9;
N	u16 msg10;
N	u16 msg11;
N	u16 msg12;
N	u16 msg13;
N	u16 msg14;
N	u16 msg15;
N	u16 msg16;
N	
N	u16 msg17;
N	u16 msg18;
N	u16 msg19;
N	u16 msg20;
N	u16 msg21;
N	u16 msg22;
N	u16 msg23;
N	u16 msg24;
N
N	//绝缘检测1
N	u16 msg25;
N	u16 msg26;
N	u16 msg27;
N	u16 msg28;
N	u16 msg29;
N	u16 msg30;
N	u16 msg31;
N	u16 msg32;
N	
N	//电池2
N	u16 msg33;
N	u16 msg34;
N	u16 msg35;
N	u16 msg36;
N	u16 msg37;
N	u16 msg38;
N	u16 msg39;
N	u16 msg40;
N	
N	u16 msg41;
N	u16 msg42;
N	u16 msg43;
N	u16 msg44;
N	u16 msg45;
N	u16 msg46;
N	u16 msg47;
N	u16 msg48;
N	
N	u16 msg49;
N	u16 msg50;
N	u16 msg51;
N	u16 msg52;
N	u16 msg53;
N	u16 msg54;
N	u16 msg55;
N	u16 msg56;
N
N	//绝缘检测2
N	u16 msg57;
N	u16 msg58;
N	u16 msg59;
N	u16 msg60;
N	u16 msg61;
N	u16 msg62;
N	u16 msg63;
N	u16 msg64;	
N	
N}BMSMessage;
N
Nextern BMSMessage BMSmsg;
N
Nextern CanRxMsg g_tCanRxMsg;
N
N/* 供外部调用的函数声明 */
Nextern void CAN1_Init(u16 Fdiv);
Nextern void CAN2_Init(u16 Fdiv);
Nextern void SendCanMsg(void);
Nextern void ProcessDataFormCAN(void);
Nextern u8 CAN1_Send_Msg(unsigned short int StdID,unsigned char *msg, unsigned char len,u16 time);
Nextern u8 CAN2_Send_Msg(unsigned short int StdID,unsigned char *msg, unsigned char len,u16 time);
Nextern u8 CAN1_Send_Msg_Extend(unsigned int StdID,unsigned char *msg, unsigned char len,u16 time);
Nextern u8 CAN2_Send_Msg_Extend(unsigned int StdID,unsigned char *msg, unsigned char len,u16 time);
Nextern u8 CAN_Send_Msg(unsigned short int StdID,unsigned char *msg, unsigned char len,u16 time,u8 CanSelect);
N#endif
N
N
L 86 "..\..\User\bsp\bsp.h" 2
N#include "bsp_usart.h"
N#include "bsp_cpu_flash.h"
L 1 "..\..\User\bsp\BSP\bsp_cpu_flash.h" 1
N/*
N*********************************************************************************************************
N*
N*	模块名称 : cpu内部falsh操作模块
N*	文件名称 : bsp_cpu_flash.h
N*	版    本 : V1.0
N*
N*	Copyright (C), 2013-2014, 安富莱电子 www.armfly.com
N*
N*********************************************************************************************************
N*/
N#include "includes.h"
L 1 "..\..\User\includes.h" 1
N/*
N*********************************************************************************************************
N*
N*	模块名称 : 头文件汇总
N*	文件名称 : includes.h
N*	版    本 : V1.0
N*	说    明 : 当前使用头文件汇总
N*
N*	修改记录 :
N*		版本号    日期        作者     说明
N*		V1.0    2015-08-02  Eric2013   首次发布
N*
N*	Copyright (C), 2015-2020, 安富莱电子 www.armfly.com
N*
N*********************************************************************************************************
N*/
N#ifndef  __INCLUDES_H__
N#define  __INCLUDES_H__
N
N
N
N
N/*
N*********************************************************************************************************
N*                                         标准库
N*********************************************************************************************************
N*/
N#include  <stdarg.h>
N#include  <stdio.h>
N#include  <stdlib.h>
N#include  <math.h>
N
N
N/*
N*********************************************************************************************************
N*                                         其它库
N*********************************************************************************************************
N*/
N#include  <cpu.h>
N#include  <lib_def.h>
N#include  <lib_ascii.h>
N#include  <lib_math.h>
L 1 "..\..\uCOS-III\uC-LIB\lib_math.h" 1
N/*
N*********************************************************************************************************
N*                                                uC/LIB
N*                                        CUSTOM LIBRARY MODULES
N*
N*                          (c) Copyright 2004-2012; Micrium, Inc.; Weston, FL
N*
N*               All rights reserved.  Protected by international copyright laws.
N*
N*               uC/LIB is provided in source form to registered licensees ONLY.  It is 
N*               illegal to distribute this source code to any third party unless you receive 
N*               written permission by an authorized Micrium representative.  Knowledge of 
N*               the source code may NOT be used to develop a similar product.
N*
N*               Please help us continue to provide the Embedded community with the finest 
N*               software available.  Your honesty is greatly appreciated.
N*
N*               You can contact us at www.micrium.com.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*
N*                                        MATHEMATIC OPERATIONS
N*
N* Filename      : lib_math.h
N* Version       : V1.37.01
N* Programmer(s) : SR
N*                 ITJ
N*********************************************************************************************************
N* Note(s)       : (1) NO compiler-supplied standard library functions are used in library or product software.
N*
N*                     (a) ALL standard library functions are implemented in the custom library modules :
N*
N*                         (1) \<Custom Library Directory>\lib_*.*
N*
N*                         (2) \<Custom Library Directory>\Ports\<cpu>\<compiler>\lib*_a.*
N*
N*                               where
N*                                       <Custom Library Directory>      directory path for custom library software
N*                                       <cpu>                           directory name for specific processor (CPU)
N*                                       <compiler>                      directory name for specific compiler
N*
N*                     (b) Product-specific library functions are implemented in individual products.
N*
N*********************************************************************************************************
N* Notice(s)     : (1) The Institute of Electrical and Electronics Engineers and The Open Group, have given
N*                     us permission to reprint portions of their documentation.  Portions of this text are
N*                     reprinted and reproduced in electronic form from the IEEE Std 1003.1, 2004 Edition,
N*                     Standard for Information Technology -- Portable Operating System Interface (POSIX),
N*                     The Open Group Base Specifications Issue 6, Copyright (C) 2001-2004 by the Institute
N*                     of Electrical and Electronics Engineers, Inc and The Open Group.  In the event of any
N*                     discrepancy between these versions and the original IEEE and The Open Group Standard,
N*                     the original IEEE and The Open Group Standard is the referee document.  The original
N*                     Standard can be obtained online at http://www.opengroup.org/unix/online.html.
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                               MODULE
N*
N* Note(s) : (1) This mathematics library header file is protected from multiple pre-processor inclusion 
N*               through use of the mathematics library module present pre-processor macro definition.
N*********************************************************************************************************
N*/
N
N#ifndef  LIB_MATH_MODULE_PRESENT                                /* See Note #1.                                         */
N#define  LIB_MATH_MODULE_PRESENT
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                            INCLUDE FILES
N*
N* Note(s) : (1) The custom library software files are located in the following directories :
N*
N*               (a) \<Custom Library Directory>\lib_*.*
N*
N*                       where
N*                               <Custom Library Directory>      directory path for custom library software
N*
N*           (2) CPU-configuration  software files are located in the following directories :
N*
N*               (a) \<CPU-Compiler Directory>\cpu_*.*
N*               (b) \<CPU-Compiler Directory>\<cpu>\<compiler>\cpu*.*
N*
N*                       where
N*                               <CPU-Compiler Directory>        directory path for common CPU-compiler software
N*                               <cpu>                           directory name for specific processor (CPU)
N*                               <compiler>                      directory name for specific compiler
N*
N*           (3) Compiler MUST be configured to include as additional include path directories :
N*
N*               (a) '\<Custom Library Directory>\' directory                            See Note #1a
N*
N*               (b) (1) '\<CPU-Compiler Directory>\'                  directory         See Note #2a
N*                   (2) '\<CPU-Compiler Directory>\<cpu>\<compiler>\' directory         See Note #2b
N*
N*           (4) NO compiler-supplied standard library functions SHOULD be used.
N*********************************************************************************************************
N*/
N
N#include  <cpu.h>
N#include  <cpu_core.h>
N
N#include  <lib_def.h>
N
N
N/*
N*********************************************************************************************************
N*                                               EXTERNS
N*********************************************************************************************************
N*/
N
N#ifdef   LIB_MATH_MODULE
S#define  LIB_MATH_EXT
N#else
N#define  LIB_MATH_EXT  extern
N#endif
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                               DEFINES
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                        RANDOM NUMBER DEFINES
N*
N* Note(s) : (1) (a) IEEE Std 1003.1, 2004 Edition, Section 'rand() : DESCRIPTION' states that "if rand() 
N*                   is called before any calls to srand() are made, the same sequence shall be generated 
N*                   as when srand() is first called with a seed value of 1".
N*
N*               (b) (1) BSD/ANSI-C implements rand() as a Linear Congruential Generator (LCG) :
N*
N*                       (A) random_number       =  [(a * random_number ) + b]  modulo m
N*                                        n + 1                        n
N*
N*                               where
N*                                       (1) (a) random_number       Next     random number to generate
N*                                                            n+1
N*                                           (b) random_number       Previous random number    generated
N*                                                            n
N*                                           (c) random_number       Initial  random number seed
N*                                                            0                      See also Note #1a
N*
N*                                       (2) a =   1103515245        LCG multiplier
N*                                       (3) b =        12345        LCG incrementor
N*                                       (4) m = RAND_MAX + 1        LCG modulus     See also Note #1b2
N*
N*                   (2) (A) IEEE Std 1003.1, 2004 Edition, Section 'rand() : DESCRIPTION' states that 
N*                           "rand() ... shall compute a sequence of pseudo-random integers in the range 
N*                           [0, {RAND_MAX}] with a period of at least 2^32".
N*
N*                       (B) However, BSD/ANSI-C 'stdlib.h' defines "RAND_MAX" as "0x7fffffff", or 2^31; 
N*                           which therefore limits the range AND period to no more than 2^31.
N*********************************************************************************************************
N*/
N
N#define  RAND_SEED_INIT_VAL                                1u   /* See Note #1a.                                        */
N
N#define  RAND_LCG_PARAM_M                         0x7FFFFFFFu   /* See Note #1b2B.                                      */
N#define  RAND_LCG_PARAM_A                         1103515245u   /* See Note #1b1A2.                                     */
N#define  RAND_LCG_PARAM_B                              12345u   /* See Note #1b1A3.                                     */
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                             DATA TYPES
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*                                       RANDOM NUMBER DATA TYPE
N*********************************************************************************************************
N*/
N
Ntypedef  CPU_INT32U  RAND_NBR;
N
N
N/*
N*********************************************************************************************************
N*                                          GLOBAL VARIABLES
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                         FUNCTION PROTOTYPES
N*********************************************************************************************************
N*/
N
Nvoid      Math_Init       (void);
N
N                                                                /* ------------------ RAND NBR FNCTS ------------------ */
Nvoid      Math_RandSetSeed(RAND_NBR  seed);
N
NRAND_NBR  Math_Rand       (void);
N
NRAND_NBR  Math_RandSeed   (RAND_NBR  seed);
N
N
N/*$PAGE*/
N/*
N*********************************************************************************************************
N*                                        CONFIGURATION ERRORS
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                             MODULE END
N*
N* Note(s) : (1) See 'lib_math.h  MODULE'.
N*********************************************************************************************************
N*/
N
N#endif                                                          /* End of lib math module include.                      */
N
L 43 "..\..\User\includes.h" 2
N#include  <lib_mem.h>
N#include  <lib_str.h>
N#include  <app_cfg.h>
L 1 "..\..\User\app_cfg.h" 1
N/*
N*********************************************************************************************************
N*                                            EXAMPLE CODE
N*
N*               This file is provided as an example on how to use Micrium products.
N*
N*               Please feel free to use any application code labeled as 'EXAMPLE CODE' in
N*               your application products.  Example code may be used as is, in whole or in
N*               part, or may be used as a reference only. This file can be modified as
N*               required to meet the end-product requirements.
N*
N*               Please help us continue to provide the Embedded community with the finest
N*               software available.  Your honesty is greatly appreciated.
N*
N*               You can find our product's user manual, API reference, release notes and
N*               more information at https://doc.micrium.com.
N*               You can contact us at www.micrium.com.
N*********************************************************************************************************
N*/
N
N/*
N*********************************************************************************************************
N*
N*	模块名称 : uCOS-III的应用配置
N*	文件名称 : app_cfg.c
N*	版    本 : V1.0
N*	说    明 : ucos-ii的应用配置
N*
N*	修改记录 :
N*		版本号  日期        作者     说明
N*		V1.0    2015-08-10 Eric2013  正式发布
N*
N*	Copyright (C), 2015-2016, 安富莱电子 www.armfly.com
N*
N*********************************************************************************************************
N*/
N#ifndef  APP_CFG_MODULE_PRESENT
N#define  APP_CFG_MODULE_PRESENT
N
N
N/*
N*********************************************************************************************************
N*                                       MODULE ENABLE / DISABLE
N*********************************************************************************************************
N*/
N
N
N/*
N*********************************************************************************************************
N*                                            TASK PRIORITIES
N*********************************************************************************************************
N*/
N#define		APP_CFG_TASK_FeedDog_PRIO									2u
N#define		APP_CFG_TASK_EthernetSer_PRIO								4u
N#define		APP_CFG_TASK_EthernetCli_PRIO								5u
N#define		APP_CFG_TASK_MotionControl_PRIO								9u
N#define		APP_CFG_TASK_CAN_PRIO                                 		8u
N#define  	APP_CFG_TASK_SpeedCtr_PRIO								8u
N
N
N/*
N*********************************************************************************************************
N*                                            TASK STACK SIZES
N*                             Size of the task stacks (# of OS_STK entries)
N*********************************************************************************************************
N*/
N
N#define		APP_CFG_TASK_FEEDDOG_STK_SIZE                    		256u
N#define		APP_CFG_TASK_ETHERNETSERCOM_STK_SIZE					1024u
N#define		APP_CFG_TASK_ETHERNETCLICOM_STK_SIZE					1024u
N#define 	APP_CFG_TASK_MotionControl_STK_SIZE						2048u
N
N#define		APP_CFG_TASK_USER_CAN_STK_SIZE                    		1024u
N#define  APP_CFG_TASK_Speed_STK_SIZE						1024u
N
N
N/*
N*********************************************************************************************************
N*                                     TRACE / DEBUG CONFIGURATION
N*********************************************************************************************************
N*/
N
N#ifndef  TRACE_LEVEL_OFF
S#define  TRACE_LEVEL_OFF                        0u
N#endif
N
N#ifndef  TRACE_LEVEL_INFO
S#define  TRACE_LEVEL_INFO                       1u
N#endif
N
N#ifndef  TRACE_LEVEL_DBG
S#define  TRACE_LEVEL_DBG                        2u
N#endif
N
N#define  APP_TRACE_LEVEL                        TRACE_LEVEL_OFF
N#define  APP_TRACE                              printf
N
N#define  APP_TRACE_INFO(x)               ((APP_TRACE_LEVEL >= TRACE_LEVEL_INFO)  ? (void)(APP_TRACE x) : (void)0)
N#define  APP_TRACE_DBG(x)                ((APP_TRACE_LEVEL >= TRACE_LEVEL_DBG)   ? (void)(APP_TRACE x) : (void)0)
N
N#endif
N
N/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/
L 46 "..\..\User\includes.h" 2
N
N
N/*
N*********************************************************************************************************
N*                                          OS和系统库
N*********************************************************************************************************
N*/
N#include  <os.h>
N
N/*
N*********************************************************************************************************
N*                                        APP / BSP
N*********************************************************************************************************
N*/
N#include  <bsp.h>
N
N
N/*
N*********************************************************************************************************
N*                                          变量和函数
N*********************************************************************************************************
N*/
Nextern void TCPnetTest(void);
N
N
N#endif
N
N/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/
L 13 "..\..\User\bsp\BSP\bsp_cpu_flash.h" 2
N#ifndef _BSP_CPU_FLASH_H_
N#define _BSP_CPU_FLASH_H_
N
N#define FLASH_BASE_ADDR	0x08000000			/* Flash基地址 */
N#define	FLASH_SIZE		(1*1024*1024)		/* Flash 容量 */
N
N/* Base address of the Flash sectors */
N#define ADDR_FLASH_SECTOR_0     ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */
N#define ADDR_FLASH_SECTOR_1     ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */
N#define ADDR_FLASH_SECTOR_2     ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */
N#define ADDR_FLASH_SECTOR_3     ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */
N#define ADDR_FLASH_SECTOR_4     ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */
N#define ADDR_FLASH_SECTOR_5     ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */
N#define ADDR_FLASH_SECTOR_6     ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */
N#define ADDR_FLASH_SECTOR_7     ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */
N#define ADDR_FLASH_SECTOR_8     ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */
N#define ADDR_FLASH_SECTOR_9     ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */
N#define ADDR_FLASH_SECTOR_10    ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */
N#define ADDR_FLASH_SECTOR_11    ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */
N
N#define FLASH_IS_EQU		0   /* Flash内容和待写入的数据相等,不需要擦除和写操作 */
N#define FLASH_REQ_WRITE		1	/* Flash不需要擦除,直接写 */
N
N#define FLASH_REQ_ERASE		2	/* Flash需要先擦除,再写 */
N#define FLASH_PARAM_ERR		3	/* 函数参数错误 */
N
Nuint8_t bsp_ReadCpuFlash(uint32_t _ulFlashAddr, uint8_t *_ucpDst, uint32_t _ulSize);
Nuint8_t bsp_WriteCpuFlash(uint32_t _ulFlashAddr, uint8_t *_ucpSrc, uint32_t _ulSize);
Nuint8_t bsp_CmpCpuFlash(uint32_t _ulFlashAddr, uint8_t *_ucpBuf, uint32_t _ulSize);
Nuint32_t bsp_GetSector(uint32_t Address);
Nvoid bsp_FLASH_EraseSector(uint32_t _ulFlashAddr);
Nvoid bsp_FLASH_Write(uint32_t _ulFlashAddr, uint8_t *_ucpSrc, uint32_t _ulSize);
Nvoid PowerOn_WriteFlash_SystemInfoBackup(void);
N#endif
L 88 "..\..\User\bsp\bsp.h" 2
N#include "bsp_exti.h"
L 1 "..\..\User\bsp\BSP\bsp_exti.h" 1
N/*
N*********************************************************************************************************
N*
N*	模块名称 : 外部中断模块
N*	文件名称 : bsp_exit.h
N*	版    本 : V1.0
N*	说    明 : 将按键K1配置成外部中断触发方式头文件
N*	修改记录 :
N*		版本号   日期        作者     说明
N*		V1.0    2013-11-21  armfly   正式发布
N*
N*	Copyright (C), 2013-2014, 安富莱电子 www.armfly.com
N*
N*********************************************************************************************************
N*/
N
N#ifndef __BSP_EXIT_H
N#define __BSP_EXIT_H
N#include "bsp.h"
Nextern u8 PVDFlag;
Nextern void vBkpSramInit(void);     // 备份 RTC 4K SRAM初始化 
N
Nextern void EXTIX_Init(void);    // 信号处理单元板CPU掉电检测脚PB8 外部中断设置
Nextern u16 BackupSRAM_ReadData(u16 AddrOffset, u8 *pData, u16 DataLen);
Nextern void agvReadLastCoo(void);
N
Ntypedef struct
N{
N	float xPoint;
N	float yPoint;
N	float W;
N}agvPowOffCoordinatePoints;
N
Ntypedef union
N{
N	agvPowOffCoordinatePoints PowOffCoordinatePoints;
N	unsigned char buffer[sizeof(agvPowOffCoordinatePoints)];
N}agvPowOffList;
N
N
Nextern agvPowOffList PowOffList;
N
N#endif
N
N/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/
L 89 "..\..\User\bsp\bsp.h" 2
N#include "bsp_wwdg.h"
L 1 "..\..\User\bsp\BSP\bsp_wwdg.h" 1
N#include "sys.h"
L 1 "..\..\User\bsp\BSP\sys.h" 1
N#ifndef __SYS_H
N#define __SYS_H	 
N#include "stm32f4xx.h" 
N
N//0,不支持os
N//1,支持os
N#define SYSTEM_SUPPORT_OS		1		//定义系统文件夹是否支持OS
N																	    
N//位带操作,实现51类似的GPIO控制功能
N//具体实现思想,参考<<CM3权威指南>>第五章(87页~92页).M4同M3类似,只是寄存器地址变了.
N//IO口操作宏定义
N#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2)) 
N#define MEM_ADDR(addr)  *((volatile unsigned long  *)(addr)) 
N#define BIT_ADDR(addr, bitnum)   MEM_ADDR(BITBAND(addr, bitnum)) 
N//IO口地址映射
N#define GPIOA_ODR_Addr    (GPIOA_BASE+20) //0x40020014
N#define GPIOB_ODR_Addr    (GPIOB_BASE+20) //0x40020414 
N#define GPIOC_ODR_Addr    (GPIOC_BASE+20) //0x40020814 
N#define GPIOD_ODR_Addr    (GPIOD_BASE+20) //0x40020C14 
N#define GPIOE_ODR_Addr    (GPIOE_BASE+20) //0x40021014 
N#define GPIOF_ODR_Addr    (GPIOF_BASE+20) //0x40021414    
N#define GPIOG_ODR_Addr    (GPIOG_BASE+20) //0x40021814   
N#define GPIOH_ODR_Addr    (GPIOH_BASE+20) //0x40021C14    
N#define GPIOI_ODR_Addr    (GPIOI_BASE+20) //0x40022014     
N
N#define GPIOA_IDR_Addr    (GPIOA_BASE+16) //0x40020010 
N#define GPIOB_IDR_Addr    (GPIOB_BASE+16) //0x40020410 
N#define GPIOC_IDR_Addr    (GPIOC_BASE+16) //0x40020810 
N#define GPIOD_IDR_Addr    (GPIOD_BASE+16) //0x40020C10 
N#define GPIOE_IDR_Addr    (GPIOE_BASE+16) //0x40021010 
N#define GPIOF_IDR_Addr    (GPIOF_BASE+16) //0x40021410 
N#define GPIOG_IDR_Addr    (GPIOG_BASE+16) //0x40021810 
N#define GPIOH_IDR_Addr    (GPIOH_BASE+16) //0x40021C10 
N#define GPIOI_IDR_Addr    (GPIOI_BASE+16) //0x40022010 
N 
N//IO口操作,只对单一的IO口!
N//确保n的值小于16!
N#define PAout(n)   BIT_ADDR(GPIOA_ODR_Addr,n)  //输出 
N#define PAin(n)    BIT_ADDR(GPIOA_IDR_Addr,n)  //输入 
N
N#define PBout(n)   BIT_ADDR(GPIOB_ODR_Addr,n)  //输出 
N#define PBin(n)    BIT_ADDR(GPIOB_IDR_Addr,n)  //输入 
N
N#define PCout(n)   BIT_ADDR(GPIOC_ODR_Addr,n)  //输出 
N#define PCin(n)    BIT_ADDR(GPIOC_IDR_Addr,n)  //输入 
N
N#define PDout(n)   BIT_ADDR(GPIOD_ODR_Addr,n)  //输出 
N#define PDin(n)    BIT_ADDR(GPIOD_IDR_Addr,n)  //输入 
N
N#define PEout(n)   BIT_ADDR(GPIOE_ODR_Addr,n)  //输出 
N#define PEin(n)    BIT_ADDR(GPIOE_IDR_Addr,n)  //输入
N
N#define PFout(n)   BIT_ADDR(GPIOF_ODR_Addr,n)  //输出 
N#define PFin(n)    BIT_ADDR(GPIOF_IDR_Addr,n)  //输入
N
N#define PGout(n)   BIT_ADDR(GPIOG_ODR_Addr,n)  //输出 
N#define PGin(n)    BIT_ADDR(GPIOG_IDR_Addr,n)  //输入
N
N#define PHout(n)   BIT_ADDR(GPIOH_ODR_Addr,n)  //输出 
N#define PHin(n)    BIT_ADDR(GPIOH_IDR_Addr,n)  //输入
N
N#define PIout(n)   BIT_ADDR(GPIOI_ODR_Addr,n)  //输出 
N#define PIin(n)    BIT_ADDR(GPIOI_IDR_Addr,n)  //输入
N
N//以下为汇编函数
N//void WFI_SET(void);		//执行WFI指令
N//void INTX_DISABLE(void);//关闭所有中断
N//void INTX_ENABLE(void);	//开启所有中断
N//void MSR_MSP(u32 addr);	//设置堆栈地址 
N#endif
N
N
N
N
N
N
N
N
N
N
N
L 2 "..\..\User\bsp\BSP\bsp_wwdg.h" 2
Nvoid bsp_InitWWDG(void);
Nvoid FeedDog(void);
N
L 90 "..\..\User\bsp\bsp.h" 2
N#include "bsp_iwdg.h"
L 1 "..\..\User\bsp\BSP\bsp_iwdg.h" 1
N#ifndef _IWDG_H
N#define _IWDG_H
N#include "sys.h"
N//////////////////////////////////////////////////////////////////////////////////	 
N//本程序只供学习使用,未经作者许可,不得用于其它任何用途
N//ALIENTEK STM32F407开发板
N//独立看门狗 驱动代码	   
N//正点原子@ALIENTEK
N//技术论坛:www.openedv.com
N//创建日期:2014/6/11
N//版本:V1.0
N//版权所有,盗版必究。
N//Copyright(C) 广州市星翼电子科技有限公司 2014-2024
N//All rights reserved				
N//********************************************************************************
N//V1.1 20140504
N//增加了窗口看门狗相关函数。
N////////////////////////////////////////////////////////////////////////////////// 	
N
Nvoid IWDG_Init(u8 prer,u16 rlr);//IWDG初始化
Nvoid IWDG_Feed(void);  //喂狗函数
N#endif
L 91 "..\..\User\bsp\bsp.h" 2
N#include "bsp_spi.h"
L 1 "..\..\User\bsp\BSP\bsp_spi.h" 1
N#ifndef __BSP_SPI_H
N#define __BSP_SPI_H
N#include "bsp.h"
N
Nvoid spi_gpio_init(void);
Nvoid spiinitailize(void);
Nvoid cs_high(void);
Nvoid cs_low(void);
Nvoid spi_send_byte(u8 byte);
Nu8 spi_read_byte(void);
N
N
Nextern void SpiInit(void);
N#endif
N
N
L 92 "..\..\User\bsp\bsp.h" 2
N#include "bsp_gpio.h"
L 1 "..\..\User\bsp\BSP\bsp_gpio.h" 1
N#ifndef _GLC_IO_H_
N#define _GLC_IO_H_
N#include "bsp.h"
N/**********************************************************
N		IO Define   [Add: 2016-10-24  By: CZ]
N		宏定义:更加直观的编写程序
N		端口编号从1开始++
N***********************************************************/
N//GLC_IO_ReadInput_24V---------------------------
N//gpio引脚默认为低电平
N#define  X1            			GPIO_ReadInput_24V(0) //壁障减速1
N#define  X2   		     			GPIO_ReadInput_24V(1) //壁障减速2
N#define  X3		     		    	GPIO_ReadInput_24V(2) //壁障停车
N#define  X4         				GPIO_ReadInput_24V(3) // 后避障减速1
N#define  X5 			     			GPIO_ReadInput_24V(4) // 后避障减速2
N#define  X6 								GPIO_ReadInput_24V(5) // 后避障减速3
N#define  X7  								GPIO_ReadInput_24V(6) // 急停 常开
N#define  X8         		    GPIO_ReadInput_24V(7) //防撞条
N#define  X9									GPIO_ReadInput_24V(8) // 启动 
N#define  X10        	    	GPIO_ReadInput_24V(9) //暂停
N#define  X11	    	        GPIO_ReadInput_24V(10)//左停靠
N#define  X12	    					GPIO_ReadInput_24V(11)//右停靠
N#define  X13	    	        GPIO_ReadInput_24V(12)//升降平台上限位
N#define  X14	    					GPIO_ReadInput_24V(13)//升降平台下限位
N#define  X15  	    				GPIO_ReadInput_24V(14)//左极限
N#define  X16 	    	        GPIO_ReadInput_24V(15)//左到位对射
N#define  X17	    	        GPIO_ReadInput_24V(16)//右到位对射
N#define  X18	    					GPIO_ReadInput_24V(17)//右极限 
N#define  X19	    	        GPIO_ReadInput_24V(18)//
N#define  X20	    					GPIO_ReadInput_24V(19)//
N#define  X21  	    				GPIO_ReadInput_24V(20)	
N#define  X22 	    	        GPIO_ReadInput_24V(21)		
N#define  X23  	    				GPIO_ReadInput_24V(22)	
N#define  X24 	    	        GPIO_ReadInput_24V(23)	
N#define  X25	    	        GPIO_ReadInput_24V(24)
N#define  X26	    					GPIO_ReadInput_24V(25)
N#define  X27	    	        GPIO_ReadInput_24V(26)
N#define  X28	    			    GPIO_ReadInput_24V(27)
N#define  X29	    			  	GPIO_ReadInput_24V(28)
N#define  X30	    			  	GPIO_ReadInput_24V(29)
N#define  X31	    					GPIO_ReadInput_24V(30)
N#define  X32	    	        GPIO_ReadInput_24V(31)
N#define  X33	    			    GPIO_ReadInput_24V(32)
N#define  X34	    			  	GPIO_ReadInput_24V(33)
N#define  X35	    			  	GPIO_ReadInput_24V(34)
N#define  X36	    					GPIO_ReadInput_24V(35)
N#define  X37	    	        GPIO_ReadInput_24V(36)
N#define  X38	    			    GPIO_ReadInput_24V(37)
N#define  X39	    			  	GPIO_ReadInput_24V(38)
N#define  X40	    			  	GPIO_ReadInput_24V(39)
N
N//GLC_IO_SetOutput_24V-------------------------------------------------------
N#define  Y1(n)			 				GPIO_SetOutput_24V(0,n)//前壁障切换信号1
N#define  Y2(n)			 				GPIO_SetOutput_24V(1,n)//前壁障切换信号2
N#define  Y3(n)			 				GPIO_SetOutput_24V(2,n)//前壁障切换信号3
N#define  Y4(n)							GPIO_SetOutput_24V(3,n)//红灯
N#define  Y5(n)							GPIO_SetOutput_24V(4,n)//黄灯
N#define  Y6(n)							GPIO_SetOutput_24V(5,n)//绿灯
N#define  Y7(n)		 		  		GPIO_SetOutput_24V(6,n)//  启动灯
N#define  Y8(n)		 	    		GPIO_SetOutput_24V(7,n)//  暂停灯
N#define  Y9(n)		 	    		GPIO_SetOutput_24V(8,n)//  充电
N#define  Y10(n)		 	    		GPIO_SetOutput_24V(9,n)//  
N#define  Y11(n)	        	  GPIO_SetOutput_24V(10,n)// 
N#define  Y12(n)	        	  GPIO_SetOutput_24V(11,n)// 
N#define  Y13(n)	     				GPIO_SetOutput_24V(12,n)//
N#define  Y14(n)	     				GPIO_SetOutput_24V(13,n) //
N#define  Y15(n)      				GPIO_SetOutput_24V(14,n)//
N#define  Y16(n)	     				GPIO_SetOutput_24V(15,n) //
N#define  Y17(n)	         	  GPIO_SetOutput_24V(16,n)//
N#define  Y18(n)	  					GPIO_SetOutput_24V(17,n)//
N#define  Y19(n)     				GPIO_SetOutput_24V(18,n) //
N#define  Y20(n)	   					GPIO_SetOutput_24V(19,n)//
N#define  Y21(n)	   					GPIO_SetOutput_24V(20,n);//
N#define  Y22(n)	   					GPIO_SetOutput_24V(21,n);//
N#define  Y23(n)	   					GPIO_SetOutput_24V(22,n);//
N#define  Y24(n)	   					GPIO_SetOutput_24V(23,n);//
N#define  Y25(n)	            GPIO_SetOutput_24V(24,n);//
N#define  Y26(n)	   					GPIO_SetOutput_24V(25,n);//
N#define  Y27(n)	   					GPIO_SetOutput_24V(26,n);//
N#define  Y28(n)	            GPIO_SetOutput_24V(27,n);//
N
Ntypedef union{
N	short wValue[2];
N	float fValue;
N	int dwValue;
N}tu_convert32;
N
Nvoid initIN40X(void);
Nvoid initOUT28Y(void);
Nbool GPIO_ReadInput_24V(int index);
X_Bool GPIO_ReadInput_24V(int index);
Nvoid GPIO_SetOutput_24V(int index, bool iBool);
Xvoid GPIO_SetOutput_24V(int index, _Bool iBool);
Nbool GPIO_ReadOutput_24v(int index);
X_Bool GPIO_ReadOutput_24v(int index);
N		
Nextern tu_convert32 tuconvert32;
N#endif
L 93 "..\..\User\bsp\bsp.h" 2
N#include "tcp_server.h"
L 1 "..\..\User\W5100S\tcp_server.h" 1
N/**
N******************************************************************************
N* @file         tcp_server.h                                 
N* @version      V1.0										  		
N* @date         2018-06-18								 
N* @brief        tcp_server.c的头文件	
N*
N* @company      深圳炜世科技有限公司
N* @information  WIZnet W5100S官方代理商,全程技术支持,价格优势大!
N* @website      www.wisioe.com					
N* @forum        www.w5100s.com
N* @qqGroup      579842114																										 
N******************************************************************************
N*/
N#ifndef _TCP_ERVER_H_
N#define _TCP_ERVER_H_
N
N#include <stdint.h>
N
N/* DATA_BUF_SIZE define for Loopback example */
N#ifndef DATA_BUF_SIZE
N#define DATA_BUF_SIZE			2048
N#endif
N
N/* TCP server Loopback test example */
Nvoid do_tcp_server(void);
Nextern void do_tcp_serverQT(void);
Nextern void EthernetPrintf(const char *fmt,...);
N
N
N#endif
L 94 "..\..\User\bsp\bsp.h" 2
N
N#include "ARC-GLC_IODefine.h"
L 1 "..\..\User\bsp\ARC-GLC_IODefine.h" 1
N/*******************************************************************************
N* Function Name  : _ARC_GLC_IODEFINE_H_
N* Description    : Define ARC_GLC_IO initial
N* Input          : 双向潜伏式
N* Output         :
N* Return         : 
N*******************************************************************************/
N
N#ifndef _ARC_GLC_IODEFINE_H_
N#define _ARC_GLC_IODEFINE_H_
N
N#include <stm32f4xx.h>
N
N/***************************************
NINPUT24V_PIN:
N
N******************************************/
N
N//---------------------------------------------------
N#define INPUT24V1_PIN			GPIO_Pin_7  
N#define INPUT24V1_PORT			GPIOI
N
N#define INPUT24V2_PIN			GPIO_Pin_6 
N#define INPUT24V2_PORT			GPIOI
N
N#define INPUT24V3_PIN			GPIO_Pin_5 	
N#define INPUT24V3_PORT			GPIOI
N
N#define INPUT24V4_PIN			GPIO_Pin_4  
N#define INPUT24V4_PORT			GPIOI
N
N#define INPUT24V5_PIN			GPIO_Pin_1  
N#define INPUT24V5_PORT			GPIOE
N
N#define INPUT24V6_PIN			GPIO_Pin_0	
N#define INPUT24V6_PORT			GPIOE
N
N#define INPUT24V7_PIN			GPIO_Pin_9	
N#define INPUT24V7_PORT			GPIOB
N
N#define INPUT24V8_PIN			GPIO_Pin_8	
N#define INPUT24V8_PORT			GPIOB
N
N#define INPUT24V9_PIN			GPIO_Pin_7	
N#define INPUT24V9_PORT			GPIOB
N
N#define INPUT24V10_PIN		GPIO_Pin_4	
N#define INPUT24V10_PORT			GPIOB
N
N#define INPUT24V11_PIN		GPIO_Pin_15  
N#define INPUT24V11_PORT			GPIOG
N
N#define INPUT24V12_PIN		GPIO_Pin_13	
N#define INPUT24V12_PORT			GPIOG
N
N#define INPUT24V13_PIN		GPIO_Pin_12	
N#define INPUT24V13_PORT			GPIOG
N
N#define INPUT24V14_PIN		GPIO_Pin_11	
N#define INPUT24V14_PORT			GPIOG
N
N#define INPUT24V15_PIN		GPIO_Pin_10	
N#define INPUT24V15_PORT			GPIOG
N
N#define INPUT24V16_PIN		GPIO_Pin_7	
N#define INPUT24V16_PORT			GPIOD
N
N#define INPUT24V17_PIN		GPIO_Pin_4	
N#define INPUT24V17_PORT			GPIOD
N
N#define INPUT24V18_PIN		GPIO_Pin_3 
N#define INPUT24V18_PORT			GPIOD
N
N#define INPUT24V19_PIN		GPIO_Pin_1 	
N#define INPUT24V19_PORT			GPIOD
N
N#define INPUT24V20_PIN		GPIO_Pin_0	
N#define INPUT24V20_PORT			GPIOD
N
N#define INPUT24V21_PIN		GPIO_Pin_15	
N#define INPUT24V21_PORT			GPIOA
N
N#define INPUT24V22_PIN		GPIO_Pin_3	
N#define INPUT24V22_PORT			GPIOI
N
N#define INPUT24V23_PIN		GPIO_Pin_2	
N#define INPUT24V23_PORT			GPIOI
N
N#define INPUT24V24_PIN		GPIO_Pin_1	
N#define INPUT24V24_PORT			GPIOI
N
N#define INPUT24V25_PIN		GPIO_Pin_0  
N#define INPUT24V25_PORT			GPIOI
N
N#define INPUT24V26_PIN		GPIO_Pin_15
N#define INPUT24V26_PORT			GPIOH
N
N#define INPUT24V27_PIN		GPIO_Pin_14	
N#define INPUT24V27_PORT			GPIOH
N
N#define INPUT24V28_PIN		GPIO_Pin_13	
N#define INPUT24V28_PORT			GPIOH
N
N#define INPUT24V29_PIN		GPIO_Pin_9	
N#define INPUT24V29_PORT			GPIOC
N
N#define INPUT24V30_PIN		GPIO_Pin_8	
N#define INPUT24V30_PORT			GPIOG
N
N#define INPUT24V31_PIN		GPIO_Pin_7	
N#define INPUT24V31_PORT			GPIOG
N
N#define INPUT24V32_PIN		GPIO_Pin_6	
N#define INPUT24V32_PORT			GPIOG
N
N#define INPUT24V33_PIN		GPIO_Pin_5	
N#define INPUT24V33_PORT			GPIOG
N
N#define INPUT24V34_PIN		GPIO_Pin_4	
N#define INPUT24V34_PORT			GPIOG
N
N#define INPUT24V35_PIN		GPIO_Pin_3	
N#define INPUT24V35_PORT			GPIOG
N
N#define INPUT24V36_PIN		GPIO_Pin_2	
N#define INPUT24V36_PORT			GPIOG
N
N#define INPUT24V37_PIN		GPIO_Pin_15	
N#define INPUT24V37_PORT			GPIOD
N
N#define INPUT24V38_PIN		GPIO_Pin_14	
N#define INPUT24V38_PORT			GPIOD
N
N#define INPUT24V39_PIN		GPIO_Pin_11	
N#define INPUT24V39_PORT			GPIOD
N
N#define INPUT24V40_PIN		GPIO_Pin_10	
N#define INPUT24V40_PORT			GPIOD
N
N
N/*********************************************
NOUTPUT24V_PIN:
N
N**********************************************/
N//---------------------------------------------------
N#define OUTPUT24V1_PIN			GPIO_Pin_2		
N#define OUTPUT24V1_PORT			GPIOH
N
N#define OUTPUT24V2_PIN			GPIO_Pin_3		
N#define OUTPUT24V2_PORT			GPIOH
N
N#define OUTPUT24V3_PIN			GPIO_Pin_4		
N#define OUTPUT24V3_PORT			GPIOH
N
N#define OUTPUT24V4_PIN			GPIO_Pin_5		
N#define OUTPUT24V4_PORT			GPIOH
N
N#define OUTPUT24V5_PIN			GPIO_Pin_3		
N#define OUTPUT24V5_PORT			GPIOA
N
N#define OUTPUT24V6_PIN			GPIO_Pin_4		
N#define OUTPUT24V6_PORT			GPIOA
N
N#define OUTPUT24V7_PIN			GPIO_Pin_5		
N#define OUTPUT24V7_PORT			GPIOA
N
N#define OUTPUT24V8_PIN			GPIO_Pin_0      
N#define OUTPUT24V8_PORT			GPIOB
N
N#define OUTPUT24V9_PIN			GPIO_Pin_1     
N#define OUTPUT24V9_PORT			GPIOB
N
N#define OUTPUT24V10_PIN			GPIO_Pin_11     
N#define OUTPUT24V10_PORT		GPIOF
N
N#define OUTPUT24V11_PIN			GPIO_Pin_12     
N#define OUTPUT24V11_PORT		GPIOF
N
N#define OUTPUT24V12_PIN			GPIO_Pin_13     
N#define OUTPUT24V12_PORT		GPIOF
N
N#define OUTPUT24V13_PIN			GPIO_Pin_14     
N#define OUTPUT24V13_PORT		GPIOF
N
N#define OUTPUT24V14_PIN			GPIO_Pin_15    
N#define OUTPUT24V14_PORT		GPIOF
N
N#define OUTPUT24V15_PIN			GPIO_Pin_0     
N#define OUTPUT24V15_PORT		GPIOG
N
N#define OUTPUT24V16_PIN			GPIO_Pin_1     
N#define OUTPUT24V16_PORT		GPIOG
N
N#define OUTPUT24V17_PIN			GPIO_Pin_7   
N#define OUTPUT24V17_PORT		GPIOE
N
N#define OUTPUT24V18_PIN			GPIO_Pin_8    
N#define OUTPUT24V18_PORT		GPIOE
N
N#define OUTPUT24V19_PIN			GPIO_Pin_9   
N#define OUTPUT24V19_PORT		GPIOE
N
N#define OUTPUT24V20_PIN			GPIO_Pin_10   
N#define OUTPUT24V20_PORT		GPIOE
N
N#define OUTPUT24V21_PIN			GPIO_Pin_12     
N#define OUTPUT24V21_PORT		GPIOE
N
N#define OUTPUT24V22_PIN			GPIO_Pin_13    
N#define OUTPUT24V22_PORT		GPIOE
N
N#define OUTPUT24V23_PIN			GPIO_Pin_14     
N#define OUTPUT24V23_PORT		GPIOE
N
N#define OUTPUT24V24_PIN			GPIO_Pin_15     
N#define OUTPUT24V24_PORT		GPIOE
N
N#define OUTPUT24V25_PIN			GPIO_Pin_7   
N#define OUTPUT24V25_PORT		GPIOH
N
N#define OUTPUT24V26_PIN			GPIO_Pin_8    
N#define OUTPUT24V26_PORT		GPIOH
N
N#define OUTPUT24V27_PIN			GPIO_Pin_9  
N#define OUTPUT24V27_PORT		GPIOH
N
N#define OUTPUT24V28_PIN			GPIO_Pin_11   
N#define OUTPUT24V28_PORT		GPIOH
N/******************************************************/
N
N
Nstatic GPIO_TypeDef* INPUT24V_PORT_List[40] =
N{
N	INPUT24V1_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x2000)),
N	INPUT24V2_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x2000)),
N	INPUT24V3_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x2000)),
N	INPUT24V4_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x2000)),
N	INPUT24V5_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1000)),
N	INPUT24V6_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1000)),
N	INPUT24V7_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0400)),
N	INPUT24V8_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0400)),
N	INPUT24V9_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0400)),
N	INPUT24V10_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0400)),
N	INPUT24V11_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	INPUT24V12_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	INPUT24V13_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	INPUT24V14_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	INPUT24V15_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	INPUT24V16_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0C00)),
N	INPUT24V17_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0C00)),
N	INPUT24V18_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0C00)),
N	INPUT24V19_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0C00)),
N	INPUT24V20_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0C00)),
N	INPUT24V21_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0000)),
N	INPUT24V22_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x2000)),
N	INPUT24V23_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x2000)),
N	INPUT24V24_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x2000)),
N	INPUT24V25_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x2000)),
N	INPUT24V26_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1C00)),
N	INPUT24V27_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1C00)),
N	INPUT24V28_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1C00)),
N	INPUT24V29_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0800)),
N	INPUT24V30_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	INPUT24V31_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	INPUT24V32_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	INPUT24V33_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	INPUT24V34_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	INPUT24V35_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	INPUT24V36_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	INPUT24V37_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0C00)),
N	INPUT24V38_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0C00)),
N	INPUT24V39_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0C00)),
N	INPUT24V40_PORT
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0C00))
N};
N
Nstatic uint16_t INPUT24V_PIN_List[40] =
N{
N	INPUT24V1_PIN,
X	((uint16_t)0x0080),
N	INPUT24V2_PIN,
X	((uint16_t)0x0040),
N	INPUT24V3_PIN,
X	((uint16_t)0x0020),
N	INPUT24V4_PIN,
X	((uint16_t)0x0010),
N	INPUT24V5_PIN,
X	((uint16_t)0x0002),
N	INPUT24V6_PIN,
X	((uint16_t)0x0001),
N	INPUT24V7_PIN,
X	((uint16_t)0x0200),
N	INPUT24V8_PIN,
X	((uint16_t)0x0100),
N	INPUT24V9_PIN,
X	((uint16_t)0x0080),
N	INPUT24V10_PIN,
X	((uint16_t)0x0010),
N	INPUT24V11_PIN,
X	((uint16_t)0x8000),
N	INPUT24V12_PIN,
X	((uint16_t)0x2000),
N	INPUT24V13_PIN,
X	((uint16_t)0x1000),
N	INPUT24V14_PIN,
X	((uint16_t)0x0800),
N	INPUT24V15_PIN,
X	((uint16_t)0x0400),
N	INPUT24V16_PIN,
X	((uint16_t)0x0080),
N	INPUT24V17_PIN,
X	((uint16_t)0x0010),
N	INPUT24V18_PIN,
X	((uint16_t)0x0008),
N	INPUT24V19_PIN,
X	((uint16_t)0x0002),
N	INPUT24V20_PIN,
X	((uint16_t)0x0001),
N	INPUT24V21_PIN,
X	((uint16_t)0x8000),
N	INPUT24V22_PIN,
X	((uint16_t)0x0008),
N	INPUT24V23_PIN,
X	((uint16_t)0x0004),
N	INPUT24V24_PIN,
X	((uint16_t)0x0002),
N	INPUT24V25_PIN,
X	((uint16_t)0x0001),
N	INPUT24V26_PIN,
X	((uint16_t)0x8000),
N	INPUT24V27_PIN,
X	((uint16_t)0x4000),
N	INPUT24V28_PIN,
X	((uint16_t)0x2000),
N	INPUT24V29_PIN,
X	((uint16_t)0x0200),
N	INPUT24V30_PIN,
X	((uint16_t)0x0100),
N	INPUT24V31_PIN,
X	((uint16_t)0x0080),
N	INPUT24V32_PIN,
X	((uint16_t)0x0040),
N	INPUT24V33_PIN,
X	((uint16_t)0x0020),
N	INPUT24V34_PIN,
X	((uint16_t)0x0010),
N	INPUT24V35_PIN,
X	((uint16_t)0x0008),
N	INPUT24V36_PIN,
X	((uint16_t)0x0004),
N	INPUT24V37_PIN,
X	((uint16_t)0x8000),
N	INPUT24V38_PIN,
X	((uint16_t)0x4000),
N	INPUT24V39_PIN,
X	((uint16_t)0x0800),
N	INPUT24V40_PIN
X	((uint16_t)0x0400)
N};
N
Nstatic GPIO_TypeDef* OUTPUT24V_PORT_List[28] =
N{
N	OUTPUT24V1_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1C00)),
N	OUTPUT24V2_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1C00)),
N	OUTPUT24V3_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1C00)),
N	OUTPUT24V4_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1C00)),
N	OUTPUT24V5_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0000)),
N	OUTPUT24V6_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0000)),
N	OUTPUT24V7_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0000)),
N	OUTPUT24V8_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0400)),
N	OUTPUT24V9_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x0400)),
N	OUTPUT24V10_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1400)),
N	OUTPUT24V11_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1400)),
N	OUTPUT24V12_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1400)),
N	OUTPUT24V13_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1400)),
N	OUTPUT24V14_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1400)),
N	OUTPUT24V15_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	OUTPUT24V16_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1800)),
N	OUTPUT24V17_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1000)),
N	OUTPUT24V18_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1000)),
N	OUTPUT24V19_PORT,
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1000)),
N	OUTPUT24V20_PORT
X	((GPIO_TypeDef *) ((((uint32_t)0x40000000) + 0x00020000) + 0x1000))
N};
N
Nstatic uint16_t OUTPUT24V_PIN_List[28] =
N{
N	OUTPUT24V1_PIN,
X	((uint16_t)0x0004),
N	OUTPUT24V2_PIN,
X	((uint16_t)0x0008),
N	OUTPUT24V3_PIN,
X	((uint16_t)0x0010),
N	OUTPUT24V4_PIN,
X	((uint16_t)0x0020),
N	OUTPUT24V5_PIN,
X	((uint16_t)0x0008),
N	OUTPUT24V6_PIN,
X	((uint16_t)0x0010),
N	OUTPUT24V7_PIN,
X	((uint16_t)0x0020),
N	OUTPUT24V8_PIN,
X	((uint16_t)0x0001),
N	OUTPUT24V9_PIN,
X	((uint16_t)0x0002),
N	OUTPUT24V10_PIN,
X	((uint16_t)0x0800),
N	OUTPUT24V11_PIN,
X	((uint16_t)0x1000),
N	OUTPUT24V12_PIN,
X	((uint16_t)0x2000),
N	OUTPUT24V13_PIN,
X	((uint16_t)0x4000),
N	OUTPUT24V14_PIN,
X	((uint16_t)0x8000),
N	OUTPUT24V15_PIN,
X	((uint16_t)0x0001),
N	OUTPUT24V16_PIN,
X	((uint16_t)0x0002),
N	OUTPUT24V17_PIN,
X	((uint16_t)0x0080),
N	OUTPUT24V18_PIN,
X	((uint16_t)0x0100),
N	OUTPUT24V19_PIN,
X	((uint16_t)0x0200),
N	OUTPUT24V20_PIN
X	((uint16_t)0x0400)
N};
N
N
N
N#endif
L 96 "..\..\User\bsp\bsp.h" 2
N#include "Laser.h"
L 1 "..\..\User\SENSOR\Laser.h" 1
N#ifndef _LASER_H
N#define _LASER_H
N#include "bsp.h"
Nvoid ProccessAGVInfo(unsigned char *RecvBuffer,unsigned short BufferLength);
Nvoid ProccessAGVDATAInfo1(unsigned char Res);//将此函数放入串口中断即可
Nunsigned int Prepare_UartToROS_Send(unsigned char string_out[]);
N
W "..\..\User\SENSOR\Laser.h" 8 6 Deprecated declaration SlamDataProcess - give arg types
Nvoid SlamDataProcess();
Nuint16_t SlamAddCheckSumCRC(unsigned char* cBuffer, unsigned short iBufLen);
N
W "..\..\User\SENSOR\Laser.h" 11 8 last line of file ends without a newline
N#endif 
L 97 "..\..\User\bsp\bsp.h" 2
N#include "Calculation.h"
L 1 "..\..\User\CONTROLFUNCTION\Calculation.h" 1
N#ifndef __CALCULATION_H
N#define __CALCULATION_H
N#include "bsp.h"
N
Ntypedef struct
N{
N    float TarX;
N
N    float TarY;
N
N    float CurAngle;
N
N} CoordinatePoints; //模块局部结构体
N
N/*定义用于计算的点
NStartPoint TargetPoint直线运行当前点(起点)和下一个点(目标点)
NCurrentCenterPoint  agv运动中心实时坐标
NPointOne,PointTwo,PointThree,PointFour弧线转弯用的四个点,上一个点,当前点,下一个点,下两个点
NA,B为单机测试时,放置屏幕可以调整的坐标
N*/
Nextern CoordinatePoints StartPoint, TargetPoint, CurrentCenterPoint, PointOne, PointTwo, PointThree, PointFour, CircleCenterPoint,FrontViewPoint;
N
Ntypedef struct
N{
N	CoordinatePoints p1,p2;//两点构成一条直线
N	int VerticalWithX;//1垂直于X轴  2垂直于Y轴  3不与坐标轴垂直 
N	double k,b;//直线方程参数y = kx + b
N}Line;
N
Nextern float mapping(float val, float I_Min, float I_Max, float O_Min, float O_Max);
N
Nextern float TwoPointDistance(CoordinatePoints PointOne, CoordinatePoints PointTwo);
N
Nextern CoordinatePoints GetCircleCenterPoint(CoordinatePoints P,CoordinatePoints Point2,CoordinatePoints Point3);//计算圆心
N
Nextern double CalCoordinateDis(CoordinatePoints CurrentCenterPoint, CoordinatePoints StartPoint, CoordinatePoints TargetPoint);
N
Nextern float CalculatingDirectionAngle(CoordinatePoints PointOne, CoordinatePoints PointTwo);
N
Nextern float CalculatingCurrentAndTargetAngle(float agvActualAngle, float agvTargetAngle);
N
W "..\..\User\CONTROLFUNCTION\Calculation.h" 42 13 Deprecated declaration CalculateDistance - give arg types
Nextern void CalculateDistance();
N
Nextern int Point_Line_Pos(double x, double y, double startx, double starty, double endx, double endy);
N//void CalculateXBias(double Vx, double palstance, double timecount, float *YBias, float *Theta);
Nvoid CalculateXBias(float Vx, float Vy, float palstance, float timecount, float *XBias, float *YBias, float *Theta);
N
Nextern CoordinatePoints getControlTargetPoint(CoordinatePoints Point,Line Lpath,float dis);
N
Nextern Line getLine1(CoordinatePoints Point);
N
Nextern Line getLine2(CoordinatePoints Point1,CoordinatePoints Point2);
N
N#endif
L 98 "..\..\User\bsp\bsp.h" 2
N#include "Paramater.h"
L 1 "..\..\User\DATAUPDATE\Paramater.h" 1
N#ifndef __PARAMATER_H
N#define __PARAMATER_H
N#include "bsp.h"
N
N#define PATHFLAG  5  //
N
Ntypedef struct
N{
N	/***************IO输入信号***************/
N	bool 			i_QuickStopSig;						//急停
X	_Bool 			i_QuickStopSig;						
N	bool 			i_StartSig;								//启动
X	_Bool 			i_StartSig;								
N	bool			i_StopSig;								//暂停
X	_Bool			i_StopSig;								
N	bool			i_BumperSig;							//防撞条
X	_Bool			i_BumperSig;							
N	bool			i_RadarSigFront_1;				//前雷达最外层信号
X	_Bool			i_RadarSigFront_1;				
N	bool			i_RadarSigFront_2;				//前雷达中间层信号
X	_Bool			i_RadarSigFront_2;				
N	bool			i_RadarSigFront_3;				//前雷达最里层信号
X	_Bool			i_RadarSigFront_3;				
N	bool			i_RadarSigBack_1;					//后雷达最外层信号
X	_Bool			i_RadarSigBack_1;					
N	bool			i_RadarSigBack_2;					//后雷达中间层信号
X	_Bool			i_RadarSigBack_2;					
N	bool			i_RadarSigBack_3;					//后雷达最里层信号
X	_Bool			i_RadarSigBack_3;					
N	
N	bool 			i_Lift1UpLimit;						//下升降上限位
X	_Bool 			i_Lift1UpLimit;						
N	bool			i_Lift1DownLimit;					//下升降下限位
X	_Bool			i_Lift1DownLimit;					
N	
N	bool 			i_Lift2UpLimit;						//上升降上限位
X	_Bool 			i_Lift2UpLimit;						
N	bool			i_Lift2DownLimit;					//上升降下限位
X	_Bool			i_Lift2DownLimit;					
N
N	bool			i_Shift1_LimitLeft;				//下层平移左极限
X	_Bool			i_Shift1_LimitLeft;				
N	bool			i_Shift1_LimitRight;			//下层平移右极限
X	_Bool			i_Shift1_LimitRight;			
N	bool			i_Shift1_Origin;					//下层平移原点
X	_Bool			i_Shift1_Origin;					
N	bool			i_Shift1ArrivalLeft;			//下层料框左到位对射
X	_Bool			i_Shift1ArrivalLeft;			
N	bool			i_Shift1ArrivalRight;			//下层料框右到位对射
X	_Bool			i_Shift1ArrivalRight;			
N	
N	bool			i_Shift2_LimitLeft;				//上层平移左极限
X	_Bool			i_Shift2_LimitLeft;				
N	bool      i_Shift2_LimitRight;			//上层平移右极限
X	_Bool      i_Shift2_LimitRight;			
N	bool      i_Shift2_Origin;					//上层平移原点
X	_Bool      i_Shift2_Origin;					
N	bool			i_Shift2ArrivalLeft;			//上层料框左到位对射
X	_Bool			i_Shift2ArrivalLeft;			
N	bool			i_Shift2ArrivalRight;			//上层料框右到位对射
X	_Bool			i_Shift2ArrivalRight;			
N	
N	bool			i_Push1_Limit;						//下层推杆极限
X	_Bool			i_Push1_Limit;						
N	bool			i_Push1_Origain;					//下层推杆原点
X	_Bool			i_Push1_Origain;					
N	
N	bool			i_Push2_Limit;						//上层推杆极限
X	_Bool			i_Push2_Limit;						
N	bool			i_Push2_Origain;					//上层推杆原点
X	_Bool			i_Push2_Origain;					
N	
N	bool 			i_LightStopFlagL;					//左光电停车
X	_Bool 			i_LightStopFlagL;					
N	bool 			i_LightStopFlagR;					//右光电停车
X	_Bool 			i_LightStopFlagR;					
N	
N	/***************判断标志位****************/
N	bool      i_Reduction;							//雷达避障一级减速
X	_Bool      i_Reduction;							
N	bool      i_DoubleReduction;				//雷达避障二级减速
X	_Bool      i_DoubleReduction;				
N	u32 			Error_Flag;								//错误状态回报标志位	
N	
N	bool			i_StartFirst;							//第一次启动按钮触发
X	_Bool			i_StartFirst;							
N	bool      i_MaterialTesting;				//物料检测
X	_Bool      i_MaterialTesting;				
N	bool 			i_MaterialOKFlag;					//物料检测到位		
X	_Bool 			i_MaterialOKFlag;					
N	bool 			i_DamperFLAG;							//阻挡块状态  1弹起  0缩回
X	_Bool 			i_DamperFLAG;							
N	
N	/**************双层SMT**************/
N	
N
N	
N	
N	u8 				i_MaterialFlagSecond;			//上层物料状态  1有料0无料2中间状态(有料到无料,或者无料到有料)
N	u8 				i_MaterialFlagFirst;			//下层物料状态  1有料0无料2中间状态(有料到无料,或者无料到有料)
N	
N	
N	
N	short 		i_quadEncoder1;						//正交编码器1
N	short 		i_quadEncoder2;						//正交编码器2
N	short 		i_quadEncoder3;						//正交编码器3
N	short 		i_quadEncoder4;						//正交编码器4
N	
N	bool		  i_QRCodeOKFlag;						//二维码数据
X	_Bool		  i_QRCodeOKFlag;						
N	bool 			i_UpdatePathSig;					//系统更新路径标志,为1才可以接收系统下发路径
X	_Bool 			i_UpdatePathSig;					
N	int 			i_LiftHeightFirst;				//下举升实际高度
N	int 			i_LiftHeightSecond;				//上举升实际高度
N	//二维码数据
N	float 		QR_Compensation_X;				//二维码对接X补偿值
N	float 		QR_Compensation_Y;				//二维码对接Y补偿值
N	float 		QR_XbiasFromros;					//相机下发X偏移值
N	float 		QR_YbiasFromros;					//相机下发Y偏移值
N	//激光数据
N	bool 			SlamConnectError;					//SLAM与控制器通讯中断	
X	_Bool 			SlamConnectError;					
N	u8 				OnlinePointSig;						
N	float 		Coordinate_X;
N	float 		Coordinate_Y;
N	float 		Coordinate_W;
N			
N	u32 			SystemTime;								//系统时间,单位MS
N}AGVPublicInfo;
N 
Ntypedef struct
N{
N	u16 AGVID;									//agvID号
N	u16 AdvanceParkSpeed;				//预停车速度
N	u16 AdvanceParkPos;					//预停车距离
N	u16 OnlyAnglePos;						//只纠偏角度距离设置
N	u16 HandSpeed;							//点动速度
N	u16 HandSpeedSlope;					//点动速度斜坡
N	u16 AutoSpeedSlope;					//自动速度斜坡
N	u16 HandTurnSpeed;					//点动转弯速度
N	u16 LiftSpeed;							//举升速度
N	u16 ShiftSpeed;							//移轴速度
N	u16 PushSpeed;							//推杆速度
N	
N	int SetLift1Height;			//设置举升1高度
N	int SetLift2Height;			//设置举升2高度
N	int ChargingTime;						//充电时间
N	int LimitPusherPos;					//推杆极限位置
N	int TargerPusherPos;				//推杆目标位置
N	
N}AGVParameterInfo;
N
Ntypedef struct
N{
N	int SetBaseSpeed;						//实际给的行走速度
N	bool	Au_Hand;							//站点0手动/1自动	
X	_Bool	Au_Hand;							
N
N	//手动动作信号
N	u8 	HandMotorState;					//手动行走
N	u8 	HandLiftState;					//手动举升
N	u8 	HandShiftState;					//手动移轴或者皮带滚筒
N	u8 	HandPushState;					//手动推杆	
N	u8 	MusicFlag;  						//设置音乐
N	u8 	Barrier_ONOFF;					//红外开关
N	u8 	Music_ONOFF;						//音乐开关
N	u16 Vol;										//设置音量
N	u16 LaserState;							//设置激光避障状态
N	
N	//双层SMT自动对接信号
N	short Shift2State;		//上层滚筒指令
N	short Shift1State;			//下层滚筒指令
N	
N	//调度动作信号
N	u16		LaserArea;						//设置激光区域
N	u8 		standSiteID; 					//当前站点ID 自己虚拟的12345
N	u8		LightStopSig;					//对接信号
N	short DispatchSpeed;				//调度下发的路径速度
N	short NextDispatchSpeed;		//调度下发的下一个路径速度
N	u8 		CurDirection;					//当前运行方向
N	u8 		NextDirection;				//下一个运行方向
N	u8 		RunStraightState;			//0,沿X直行  1沿Y直行
N	u8    RunState;
N	float SetPlatformTurnAngle;					//设置原地旋转平台角度
N	float SetChassisTurnAngle;					//设置原地旋转底盘角度
N	
N	float X_compensation;				//单独工位特殊补偿 龙旗项目使用中
N	float Y_compensation;				//单独工位特殊补偿 龙旗项目使用中
N	float W_compensation;				//单独工位特殊补偿 龙旗项目使用中
N}AGVCommandInfo;
N
Ntypedef struct
N{
N	AGVCommandInfo Command;//屏幕或者调度指令
N	
N	AGVParameterInfo Parameter;//屏幕保存的参数
N	
N	AGVPublicInfo  Public;	//接的外设信号(相机 激光 IO 光电 报警)
N	
N}AGVStruct;//agv结构体
Nextern AGVStruct agv;
N
Ntypedef struct
N{		
N	//坐标之间的距离
N	float AngleDifference;//车身角度偏差 public
N	
N	float CenterOffset;//中心偏移量 public
N	
N	float TurnAngleDifference;
N	
N	float DistanceAgvToSTART;
N	
N	float DistanceAgvToTARGET;
N	
N	float DistanceSTARTtoTARGET;//起点和终点距离
N	
N	float VerticalDistanceAgvToTARGET;//距离终点垂直距离 public
N	
N	float VerticalDistanceAgvToSTART;//距离起点垂直距离 public
N	
N}navigationPublic;//底盘控制发布的值
N
Ntypedef struct
N{			
N	float SetCalculationRadius;//算出来的转弯半径
N		
N	float TarAngle;//直行是当前路径的方向角度 转弯是出弯线路的角度
N	
N	float OutputOffset;//最终pid算出来的补偿值
N
N	u8 FirstZeroPoint;//光电停靠第一次自然到达点位	
N	
N	float FrontViewDistance;//前视距离
N	
N	float FrontViewAngle;//当前位置与预瞄点连线形成的角度
N	
N}navigationPrivate;//底盘算法的变量
N
Ntypedef struct
N{		
N	float Kp;								//比例P
N		
N	float Ki;								//积分I
N	
N	float Kd;								//微分D
N	
N	float PosCofficient;		//位置权重系数
N	
N	float AngleCofficient;	//角度权重系数  前进正  后退负
N	
N	float MaxLimit;					//最大限制
N	
N}navigationPID;
Nextern navigationPID pid;
N
Ntypedef struct
N{		
N	navigationPublic Public;//导航模块发布的和路径的偏差
N	
N	navigationPrivate Private;//导航模块自己使用的变量
N
N	navigationPID PIDPara[4];//当前运行方向(直行 转弯 旋转)导航模块需要的pid参数
N	
N}navigationStruct;//导航控制结构体
N
Nextern navigationStruct navi;
N
W "..\..\User\DATAUPDATE\Paramater.h" 229 6 Deprecated declaration initPathInfo - give arg types
Nvoid initPathInfo();//初始化单机运行路径
N	
Nvoid reportRPTPose(u16 IntervalTime);
N
Nvoid reportRPTPose(u16 IntervalTime);
N
W "..\..\User\DATAUPDATE\Paramater.h" 235 13 Deprecated declaration ConnectOvertime - give arg types
Nextern void ConnectOvertime();
N
W "..\..\User\DATAUPDATE\Paramater.h" 237 13 Deprecated declaration clearPathInfomation - give arg types
Nextern void clearPathInfomation();
N
W "..\..\User\DATAUPDATE\Paramater.h" 239 13 Deprecated declaration InitParamater - give arg types
Nextern void InitParamater();
N
N#endif
N
N
L 99 "..\..\User\bsp\bsp.h" 2
N#include "RunCore.h"
L 1 "..\..\User\CONTROLFUNCTION\RunCore.h" 1
N#ifndef _CONTROL_H_ 
N#define _CONTROL_H_
N#include "bsp.h"
N//#define LaserSelect 1 
N//#define LED_yellow 1
N//#define LED_blue 2
N//#define LED_red 3
N//#define LED_all 4
N//#define LED_ry  5
N//#define LED_rg  6
N//#define LED_gy  7
N
N
W "..\..\User\CONTROLFUNCTION\RunCore.h" 14 13 Deprecated declaration AGVRunCore - give arg types
Nextern void AGVRunCore();
Nextern void returnZeroPoint(int TargetHight);
W "..\..\User\CONTROLFUNCTION\RunCore.h" 16 13 Deprecated declaration quickStop - give arg types
Nextern void quickStop();
Nextern void setMotorSpeedSlope(float speedSlope);
N
N#endif
N
L 100 "..\..\User\bsp\bsp.h" 2
N#include "CommunicationForCenter.h"
L 1 "..\..\User\DATAUPDATE\CommunicationForCenter.h" 1
N#ifndef _COMMUNICATIONFORCENTER_H_
N#define _COMMUNICATIONFORCENTER_H_
N#include "bsp.h"
N	
N//-----------------------
N#define STRING_SIZE 40   //瀛楃涓插ぇ灏
N#define LIST_SIZE   70
N#define WifiBUFF_SIZE   400 
N#define ParamSize       400
N#define NameSize        40
N#define UART8BUFFSTRING 400
Ntypedef enum
N{
N	teERR = 0,
N	teDecoding,
N	teDecodLost,
N	teDecodCRC,
N	teDecodSuccess
N}ctDecodestate;		//瑙g⒓鐙鎱
N//搴旂瓟鎴栧垯鎺ユ敹鐘舵
Ntypedef enum
N{
N	sort_Send = 0,  //鍙戦
N	sort_Receive = 1,//鎺ユ敹
N	sort_Default, 	//浣嶇疆鐘舵
N	sort_Size
N}teSendOrReplyType;//鍙戦佸拰鍥炲绫诲瀷
N
Ntypedef enum
N{
N	et_smtagv = 0,	//agv
N	et_B123,  //鏂欐灦
N	et_B124,	//鍏呯數鏈
N	et_Default,		//鏈煡璁惧
N	et_Size
N}teEquipmentType;//璁惧绫诲瀷
N
N
Ntypedef enum
N{
N	ct_rptac=0,
N	ct_getac ,
N	ct_getvol,
N	ct_geterr,
N	ct_getspd,
N	ct_getmt,
N	ct_rpterr,
N	ct_rptscan,
N	ct_rptmt,
N	ct_rptrtp,
N	ct_rptvol,
N	ct_rptvmot,
N	ct_rptin,
N	ct_rptlac,
N	ct_rptstart,
N	ct_rpttravel,
N	ct_rptmt_th,
N	ct_rptspd,
N	ct_rptmode,//鎵嬭嚜鍔ㄦā寮
N	ct_rptgo,
N	ct_rptpos,
N	ct_rptback,
N	ct_rtplayer,
N	ct_rptangle,
N	ct_releagv,
N	ct_callagv,
N	ct_settask,
N	ct_setrout,
N	ct_setstp,
N	ct_setspd,
N	ct_setrtp,
N	ct_settra,
N	ct_setmov,
N	ct_setvmot,
N	ct_setlock,
N	ct_setavoid,
N	ct_setmusic,
N	ct_setLaser,
N	ct_setout,
N	ct_setlrout,
N	ct_setlayer,
N	ct_setangle,
N	ct_delrtp,
N	ct_settcvoice,
N	ct_rptnode,
N	ct_rptline,//涓婃姤璺嚎
N	ct_settips,//绌洪棽鏀捐
N	ct_print,
N//	ct_setreach,
N	ct_Default,
N	ct_Size
N	
N
N}teContentType;//杩愬姩鐘舵
N
N//鏁版嵁閲嶅彂鏈哄埗缁撴瀯浣
Ntypedef struct
N{
N	//灏嗕互涓婄姸鎬佸瓧绗﹀鍒跺埌ReStructor.Matmes
N	char Matmes[ct_Size][STRING_SIZE];
X	char Matmes[ct_Size][40];
N
N	/****************鎶婃墍鏈夌殑鏁版嵁杩炴垚瀛楃绐***********************/
N	//瀛樺偍鍒癕atmesseg
N	char Matmesseg[ct_Size][WifiBUFF_SIZE];
X	char Matmesseg[ct_Size][400];
N	bool MatmesEnable[ct_Size];
X	_Bool MatmesEnable[ct_Size];
N	int  Matmestime[ct_Size];
N	uint8_t   Matmes_Num[ct_Size];
N}ResendStruct;
N
N//--------------鎻愬彇涔嬪墠鍛戒护-----------------
Ntypedef struct
N{
N	char ReceiveData[WifiBUFF_SIZE];
X	char ReceiveData[400];
N	char Cmd_List[LIST_SIZE][STRING_SIZE];//瀛樺偍鎷嗗垎鍚庣殑鍙傛暟
X	char Cmd_List[70][40];
N	char Cmd_Lt[WifiBUFF_SIZE];
X	char Cmd_Lt[400];
N	char Cmd_parameters[ParamSize][NameSize]; //鍒嗚В鍚庣殑鍙傛暟锛堝瓧绗︼級
X	char Cmd_parameters[400][40]; 
N	char Cmd_RoadParam[WifiBUFF_SIZE];
X	char Cmd_RoadParam[400];
N	int  Cmd_ListSize;
N	int Cmd_ParametersSize;
N	int RecesiveDate;//鎺ユ敹鍗曟鏁版嵁閲
N}tsCmdList;//鍛戒护鎻愬彇涔嬪墠鐨勬墍鏈夋帴鏀剁殑瀛楃
Ntypedef struct
N{
N	char Cmd_ListSize;//璁板綍澶氬皯涓В
N	char Cmd_List[7][30];//瀛樺偍鎷嗗垎鍚庣殑鍙傛暟
N	char Cmd_Dir[2];//瀛樺偍瀵瑰簲鐨勮繍鍔ㄦ柟鍚
N	char Cmd_RotateDir[2];//瀛樺偍瀵瑰簲鐨勬棆杞柟鍚
N	int Cmd_parameters[3]; //鍒嗚В鍚庣殑鍙傛暟锛堝瓧绗︼級
N	int land_mark_id;
N}tsCmdListParam;//鍛戒护鎻愬彇涔嬪墠鐨勬墍鏈夋帴鏀剁殑瀛楃
N
N
N//--------------鎻愬彇寰屾娊鍙栧嚭渚嗗垎椤炲緦鐨勫懡浠-----------------
N/******************************************
N鏈夋晥鏁告摎绲愭楂旀垚鍝 ~ 锛嬶級 锛
N
N鏂瑰悜锛坰endOrReply锛
N璁惧鍚嶇О(equipmentType)
N瀛愭ā鍧(SubEquipmentType)
N
N鎸囦护绫诲瀷(dictateType)
N鍔ㄤ綔(content)
N鍙傛暟(param)
N*******************************************/
Ntypedef struct
N{
N	tsCmdListParam CmdListParam[50];//鏈澶氳В鏋0鏉¤矾寰
N	tsCmdList CmdList;
N	teSendOrReplyType SendOrReply;			//鏂瑰悜锛坰endOrReply锛
N	teEquipmentType EquipmentType;		//璁惧鍚嶇О(equipmentType)
N	teContentType  Content;					//鍔ㄤ綔(content)
N    int Param[ParamSize];				//鍙傛暟(param)
X    int Param[400];				
N    unsigned int Paramcount;
N	 unsigned int RoadParamcount;		////閬撹矾鍙傛暟璁℃暟
N	unsigned char RFIDCtrB;
N	unsigned char RFIDDIR;
N	unsigned short ID_CountryB;
N	int RandomID;
N	bool NewReceive;
X	_Bool NewReceive;
N	unsigned int ReadyStopCtronl[2];
N}tsCommand;//鎻愬彇涔嬪緦鐨勬湁鏁堝懡浠
N
N//淇濆瓨绯荤粺涓嬪彂璺緞
Ntypedef struct
N{
N	float pose[3];//鍧愭爣
N	u8 LaserArea;//闆疯揪鍖哄煙
N	short Direction;//鏂瑰悜
N	int DispatchSpeed;//璋冨害閫熷害
N	u8 LightStopSig;//瀵规帴淇″彿
N	u8 RunState;//0娌害鏂瑰悜  1娌0搴︽柟鍚  2娌80搴︽柟鍚  3娌70搴︽柟鍚
N}LandMark;//搴曠洏鎺у埗淇″彿
N
Ntypedef struct
N{
N	char SendLineEndIDSig;
N	char ChargingState;
N	int size;
N	int curr_id;
N	LandMark land_marks[LIST_SIZE];
X	LandMark land_marks[70];
N}TrafficLandMarks;
N
Nextern TrafficLandMarks traffic_land_marks;
Nextern char Original_Command_String[WifiBUFF_SIZE];
Xextern char Original_Command_String[400];
Nextern char ParamBuff[40];
Nextern char GeCmddate[20];
Nextern ResendStruct ReStructor;
Nextern tsCommand CenterCommand;
N//extern bool bk;
N//瑙g⒓鎺ユ敹鍒扮殑涓帶
N//鎺ユ敹鍒扮殑瀛楃涓诧紝瑙g⒓涓︽媶濉厖鍒癷List
NctDecodestate CenterDecode(char Byte, tsCmdList* iList);
Nuint16_t AddCheckSum(char* cBuffer, short iBufLen);
Nint GetKeyWords(tsCmdList * iList);
Nint Getparameters(tsCmdList * iList);
Nchar CommandAnalysis(void);
Nvoid SendOrReplyTypeHandle(void);
N
Nvoid Bady_DictateTypeHandle(void);
N
N/***************************************************
N杞︿綋鍔ㄤ綔/鏌ヨ/鎻℃墜
N***************************************************/
Nvoid Create_BodyTreaty(bool AskAgainEnable,teEquipmentType EquipmentType ,teSendOrReplyType SendOrReplyType, teContentType ContentType, char *Parameter);
Xvoid Create_BodyTreaty(_Bool AskAgainEnable,teEquipmentType EquipmentType ,teSendOrReplyType SendOrReplyType, teContentType ContentType, char *Parameter);
N
Nchar* ParameterTransform(char *fmt, ...);
Nint vspf(char *fmt, ...);
Nvoid SysACKcheck(void);
Nvoid Recive_check(void);
Nuint16_t AddCheckSumCRC(char* cBuffer, short iBufLen);
Nint GetKeyWordschar(tsCmdListParam * iList,char *cmd,const char *str);
Nextern char Uart8SendBuff[UART8BUFFSTRING];
Xextern char Uart8SendBuff[400];
W "..\..\User\DATAUPDATE\CommunicationForCenter.h" 213 6 Deprecated declaration UartReceiveDataFromSystem - give arg types
Nvoid UartReceiveDataFromSystem();
N#endif
L 101 "..\..\User\bsp\bsp.h" 2
N#include "SHOW.h"
L 1 "..\..\User\HARAWARE\SHOW.h" 1
N#ifndef __SHOW_H
N#define __SHOW_H
N#include "bsp.h"
N#define LaserSelect 1 
N#define LED_blue 1
N#define LED_yellow 2
N#define LED_red 3
N#define LED_all 4
N#define LED_ry  5
N#define LED_rg  6
N#define LED_gy  7
N#define LED_ON  1 //led灯的开关亮
N
Nvoid SetAlarm(int Alarmdata);
Nvoid Reset_Alarm(int Alarmdata);
Nvoid LED_color(uint8_t color, u16 flicker);//LED颜色函数
Nvoid Laser_Run(u8 Data);//激光避障区域选择
N
N#endif
N
N
L 102 "..\..\User\bsp\bsp.h" 2
N#include "ModbusHMI.h"
L 1 "..\..\User\DATAUPDATE\ModbusHMI.h" 1
N#ifndef __MODBUSHMI_H_
N#define __MODBUSHMI_H_
N#include "bsp.h"
N
Ntypedef struct
N{
N	bool IN1;
X	_Bool IN1;
N	bool IN2;
X	_Bool IN2;
N	bool IN3;
X	_Bool IN3;
N	bool IN4;
X	_Bool IN4;
N	bool IN5;
X	_Bool IN5;
N	bool IN6;
X	_Bool IN6;
N	bool IN7;
X	_Bool IN7;
N	bool IN8;
X	_Bool IN8;
N	bool IN9;
X	_Bool IN9;
N	bool IN10;
X	_Bool IN10;
N	
N	bool IN11;
X	_Bool IN11;
N	bool IN12;
X	_Bool IN12;
N	bool IN13;
X	_Bool IN13;
N	bool IN14;
X	_Bool IN14;
N	bool IN15;
X	_Bool IN15;
N	bool IN16;
X	_Bool IN16;
N	bool IN17;
X	_Bool IN17;
N	bool IN18;
X	_Bool IN18;
N	bool IN19;
X	_Bool IN19;
N	bool IN20;
X	_Bool IN20;
N	
N	bool IN21;
X	_Bool IN21;
N	bool IN22;
X	_Bool IN22;
N	bool IN23;
X	_Bool IN23;
N	bool IN24;
X	_Bool IN24;
N	bool IN25;
X	_Bool IN25;
N	bool IN26;
X	_Bool IN26;
N	bool IN27;
X	_Bool IN27;
N	bool IN28;
X	_Bool IN28;
N	bool IN29;
X	_Bool IN29;
N	bool IN30;
X	_Bool IN30;
N	
N	bool IN31;
X	_Bool IN31;
N	bool IN32;
X	_Bool IN32;
N	bool IN33;
X	_Bool IN33;
N	bool IN34;
X	_Bool IN34;
N	bool IN35;
X	_Bool IN35;
N	bool IN36;
X	_Bool IN36;
N	bool IN37;
X	_Bool IN37;
N	bool IN38;
X	_Bool IN38;
N	bool IN39;
X	_Bool IN39;
N	bool IN40;
X	_Bool IN40;
N
N}MasterIOInput;
N
Nextern MasterIOInput MasterInput;
W "..\..\User\DATAUPDATE\ModbusHMI.h" 54 6 Deprecated declaration HMIDataUpdate - give arg types
Nvoid HMIDataUpdate();
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
W "..\..\User\DATAUPDATE\ModbusHMI.h" 72 7 last line of file ends without a newline
N#endif
L 103 "..\..\User\bsp\bsp.h" 2
N#include "user_setup.h"
L 1 "..\..\User\bsp\BSP\user_setup.h" 1
N#ifndef __USER_SETUP_H
N#define __USER_SETUP_H
N#include "bsp.h"
N
N#define DRIVER_HINS_BLD2L 0X0001//兴颂BLD2L
N#define DRIVER_HINS_BLD30 0X0002//兴颂BLD30或者STD2L
N#define DRIVER_SDO	 			0X0004//CANOPEN-SDO通讯 步科 风得控 AMC ELIFE DIS
N#define DRIVER_CURTIS			0X0008//柯蒂斯
N
N#define P_SETUP_SINGLE_PLAYER							0//单机版本:0.关闭单机测试,1:开启单机测试。
N#define P_SETUP_NAV_TYPE 									4//导航方式:0.磁条, 1.二维码, 2.SLAM, 3.Vslam,4.PPC
N#define P_SETUP_MUSIC_TYPE								1//音乐播报器类型  1新版DADONG  2旧版
N
N#define P_SETUP_PLATFORM_TYPE							5//平台类型:1悬臂轴,2双层SMT,3单层标准SMT,4叉车
N#define P_SETUP_CHASSIS_MODE							0//底盘类型:0.单差速,1.双转向架差速,2.单舵轮,3.双舵轮,4三舵轮,5.四舵轮,6.改造转向轮
N
N#define P_SETUP_LIDAR2BASE_X							0//雷达到运动中心X距离(mm)
N#define P_SETUP_LIDAR2BASE_Y							0//雷达到运动中心Y距离(mm)
N#define P_SETUP_LIDAR2BASE_THETA					0//雷达和车体前进方向夹角(0.1度)(-45.0°写成3150对应315.0°)
N
N#define P_SETUP_WHEEL_X_DIS								0//双驱动轮前进方向距离
N#define P_SETUP_WHEEL_Y_DIS								370//双驱动轮横移方向距离
N
N#define P_SETUP_ANGLE_ENCODER_NUM					0//角度编码器数量
N#define P_SETUP_ANGLE_ENCODER_DIR					0//角度编码器方向调整 
N#define P_SETUP_MAGNAV_DIR								0//导引传感器方向调整
N#define P_SETUP_DIS_ENCODER_DIR						0//拉线编码器方向调整
N
N#define P_SETUP_BATTERYTYPE								0//电池类型:1冠宇电池
N
N#define P_SETUP_MOTOR_DRIVER_BRAND				DRIVER_HINS_BLD30//行走驱动品牌
N#define P_SETUP_MOTOR_NUM									0//行走电机数量
N#define P_SETUP_MOTOR_SPEED_RATIO_NUM			6//行走速比分子
N#define P_SETUP_MOTOR_SPEED_RATIO_DEN			1//行走速比分母
N#define P_SETUP_MOTOR_DIS_RATIO_NUM				1//行走位置比分子
N#define P_SETUP_MOTOR_DIS_RATIO_DEN				1//行走位置比分母
N#define P_SETUP_MOTOR_CAN_CONNECTION			0//行走can线接法	
N#define P_SETUP_MOTOR_DIR									1000//行走轮方向调整
N
N#define P_SETUP_STEERING_DRIVER_BRAND			DRIVER_HINS_BLD2L//转向驱动品牌
N#define P_SETUP_STEERING_NUM							0//转向电机数量
N#define P_SETUP_STEERING_SPEED_RATIO_NUM	1//转向转速比分子
N#define P_SETUP_STEERING_SPEED_RATIO_DEN	1//转向转速比分母
N#define P_SETUP_STEERING_DIS_RATIO_NUM		1//转向位置比分子
N#define P_SETUP_STEERING_DIS_RATIO_DEN		1//转向位置比分母
N#define P_SETUP_STEERING_CAN_CONNECTION		0//转向can线接法
N#define P_SETUP_STEERING_DIR							0//转向轮方向调整	
N
N#define P_SETUP_LIFTER_DRIVER_BRAND				DRIVER_HINS_BLD2L//举升驱动品牌
N#define P_SETUP_LIFTER_NUM								0//举升电机数量
N#define P_SETUP_LIFTER_SPEED_RATIO_NUM		1//举升转速比分子
N#define P_SETUP_LIFTER_SPEED_RATIO_DEN		1//举升转速比分母  
N#define P_SETUP_LIFTER_DIS_RATIO_NUM			1//举升位置比分子
N#define P_SETUP_LIFTER_DIS_RATIO_DEN			1//举升位置比分母    	
N#define P_SETUP_LIFTER_CAN_CONNECTION			1000//举升can线接法
N#define P_SETUP_LIFTER_DIR								1000//举升轮方向调整
N
N#define P_SETUP_SHIFTER_DRIVER_BRAND			DRIVER_HINS_BLD2L//移轴驱动品牌
N#define P_SETUP_SHIFTER_NUM								0//移轴电机数量
N#define P_SETUP_SHIFTER_SPEED_RATIO_NUM		1//移轴转速比分子
N#define P_SETUP_SHIFTER_SPEED_RATIO_DEN		1//移轴转速比分母  
N#define P_SETUP_SHIFTER_DIS_RATIO_NUM			1//移轴位置比分子
N#define P_SETUP_SHIFTER_DIS_RATIO_DEN			1//移轴位置比分母    	
N#define P_SETUP_SHIFTER_CAN_CONNECTION		1000//移轴can线接法
N#define P_SETUP_SHIFTER_DIR								1000//移轴轮方向调整
N
N#define P_SETUP_PUSHER_DRIVER_BRAND				DRIVER_HINS_BLD2L//推杆驱动品牌
N#define P_SETUP_PUSHER_NUM								0//推杆电机数量
N#define P_SETUP_PUSHER_SPEED_RATIO_NUM		1//推杆转速比分子
N#define P_SETUP_PUSHER_SPEED_RATIO_DEN		1//推杆转速比分母  
N#define P_SETUP_PUSHER_DIS_RATIO_NUM			1//推杆位置比分子
N#define P_SETUP_PUSHER_DIS_RATIO_DEN			1//推杆位置比分母
N#define P_SETUP_PUSHER_CAN_CONNECTION			0//推杆can线接法
N#define P_SETUP_PUSHER_DIR								0//推杆轮方向调整			
N
N#define P_SETUP_CONTROLLER1_IP1						192//服务器IP192
N#define P_SETUP_CONTROLLER1_IP2						168//服务器IP168						
N#define P_SETUP_CONTROLLER1_IP3						0  //服务器IP0
N#define P_SETUP_CONTROLLER1_IP4						30 //服务器IP30
N
N#define P_SETUP_CONTROLLER2_IP1				  	192//服务器IP192
N#define P_SETUP_CONTROLLER2_IP2						168//服务器IP168
N#define P_SETUP_CONTROLLER2_IP3						0  //服务器IP0							
N#define P_SETUP_CONTROLLER2_IP4						31 //服务器IP30			
N
N#define P_SETUP_CONTROLLER3_IP1						192//服务器IP192
N#define P_SETUP_CONTROLLER3_IP2						168//服务器IP168
N#define P_SETUP_CONTROLLER3_IP3						0  //服务器IP0
N#define P_SETUP_CONTROLLER3_IP4						32 //服务器IP30	
N
N#define P_SETUP_CONTROLLER4_IP1						192//服务器IP192
N#define P_SETUP_CONTROLLER4_IP2						168//服务器IP168
N#define P_SETUP_CONTROLLER4_IP3						0  //服务器IP0							
N#define P_SETUP_CONTROLLER4_IP4						33 //服务器IP30
N
N/*四个行走轮设置ID编号*/
N#define MOTOR1_ID								0x01
N#define MOTOR2_ID      					0x01
N#define MOTOR3_ID       				0x0603
N#define MOTOR4_ID      					0x0604
N/*四个行走轮返回ID编号*/
N#define MOTOR1_BACK_ID  				0x01
N#define MOTOR2_BACK_ID 					0x01
N#define MOTOR3_BACK_ID  				0x0583
N#define MOTOR4_BACK_ID 					0x0584
N/*四个舵轮设置ID编号*/
N#define STEERING1_ID    				0x0605
N#define STEERING2_ID   					0x0606
N#define STEERING3_ID    				0x0607
N#define STEERING4_ID   					0x0608
N/*四个舵轮返回ID编号*/
N#define STEERING1_BACK_ID  			0x0585
N#define STEERING2_BACK_ID 			0x0586
N#define STEERING3_BACK_ID  			0x0587
N#define STEERING4_BACK_ID 			0x0588
N/*举升电机ID*/
N#define  LIFTER1_ID							0x9
N#define  LIFTER2_ID	    				0x9
N#define  LIFTER3_ID							0x060B
N#define  LIFTER4_ID	    				0x060C
N/*举升电机返回ID*/
N#define  LIFTER1_BACK_ID   			0x9
N#define  LIFTER2_BACK_ID				0x9
N#define  LIFTER3_BACK_ID   			0x058B
N#define  LIFTER4_BACK_ID				0x058C
N/*移轴电机ID*/
N#define  SHIFTER1_ID       			0x09
N#define  SHIFTER2_ID	    			0x05
N#define  SHIFTER3_ID       			0x060F
N/*移轴电机返回ID*/
N#define  SHIFTER1_BACK_ID  			0x09
N#define  SHIFTER2_BACK_ID				0x05
N#define  SHIFTER3_BACK_ID  			0x058F
N/*推杆电机ID*/
N#define  PUSHER1_ID       			0x0605
N#define  PUSHER2_ID	    				0x0000
N#define  PUSHER3_ID       			0x0000
N/*推杆电机返回ID*/
N#define  PUSHER1_BACK_ID				0x0585
N#define  PUSHER2_BACK_ID				0x0000
N#define  PUSHER3_BACK_ID				0x0000
N
N#define LIGHT_STOP_SIGNAL_DIS  30  //开启光电停车范围
N#define REFLECTIVE_RANGE				50	//寻找反光贴范围
N#define TURNINGOFF_ANGLE				0.03f//出弯角度判断
N#define	POSARRIVE_RANGE					5 //位置到达判断范围
N#define PRINT_TYPE_SELECT				1//打印类型1
N#define PRINT_FREQUENCY					10//多少周期打印一次
N#define START_SPEEDUP_RANGE			300//起步平稳加速范围
N#define START_SPEEDDIFF_LIMIT		20 //起步速度差限制
N#define ADVANCE_STOPSLOPE_ANGLE		0.3//弧线或者原地转弯 减速角度
N#define TURNSPEED_MIN						30//最小转弯速度
N#define TURNSPEED_MAX						100//最大转弯速度
N#define ARC_TURNSPEED_MIN				100//最小圆弧转弯速度
N
N#define  DONTSETVALUE		2147483647	  //不需要设置值
Ntypedef enum
N{
N	SETUP_NAV_TYPE,										//导航方式
N	
N	SETUP_TURN_MODE,                  //转向方式
N	SETUP_ANGLE_ENCODER_NUM,		  		//角度编码器数量
N	SETUP_ANGLE_ENCODER_DIR,		 	 		//角度编码器方向调整*********111*555**********   
N	SETUP_MAGNAV_DIR,				  				//导引传感器方向调整
N	SETUP_DIS_ENCODER_NUM,			  		//拉线编码器个数
N
N	SETUP_MOTOR_NUM,                  //行走电机数量
N	SETUP_MOTOR_SPEED_RATIO_NUM,			//行走速比分子 	 
N	SETUP_MOTOR_SPEED_RATIO_DEN,			//行走速比分母*********222*555********** 				
N	SETUP_MOTOR_DIS_RATIO_NUM,        //行走位置比分子
N	SETUP_MOTOR_DIS_RATIO_DEN,        //行走位置比分母
N	
N	SETUP_MOTOR_CAN_CONNECTION,		 	  //行走can线接法		
N	SETUP_MOTOR_DIR,							  	//行走轮方向调整
N	SETUP_STEERING_NUM,               //转向电机数量*********333*555**********
N	SETUP_STEERING_SPEED_RATIO_NUM,		//转向转速比分子
N	SETUP_STEERING_SPEED_RATIO_DEN,		//转向转速比分母
N	
N	SETUP_STEERING_DIS_RATIO_NUM,     //转向位置比分子
N	SETUP_STEERING_DIS_RATIO_DEN,     //转向位置比分母
N	SETUP_STEERING_CAN_CONNECTION,	  //转向can线接法*********444*555**********
N	SETUP_STEERING_DIR,								//转向轮方向调整				
N	SETUP_LIFTER_NUM,                 //举升电机数量
N	
N	SETUP_LIFTER_SPEED_RATIO_NUM,     //举升转速比分子
N	SETUP_LIFTER_SPEED_RATIO_DEN,     //举升转速比分母  
N	SETUP_LIFTER_DIS_RATIO_NUM,     	//举升位置比分子*********555*555**********
N	SETUP_LIFTER_DIS_RATIO_DEN,     	//举升位置比分母    	
N	SETUP_LIFTER_CAN_CONNECTION,	  	//举升can线接法
N	
N	SETUP_LIFTER_DIR,				  				//举升轮方向调整
N	SETUP_SHIFTER_NUM,                //移轴电机数量
N	SETUP_SHIFTER_SPEED_RATIO_NUM,    //移轴转速比分子*********666*555**********
N	SETUP_SHIFTER_SPEED_RATIO_DEN,    //移轴转速比分母  
N	SETUP_SHIFTER_DIS_RATIO_NUM,     	//移轴位置比分子
N	
N	SETUP_SHIFTER_DIS_RATIO_DEN,     	//移轴位置比分母    	
N	SETUP_SHIFTER_CAN_CONNECTION,	  	//移轴can线接法
N	SETUP_SHIFTER_DIR,				  			//移轴轮方向调整*********777*555**********
N	SETUP_PUSHER_NUM,                 //推杆电机数量
N	SETUP_PUSHER_SPEED_RATIO_NUM,     //推杆转速比分子
N	
N	SETUP_PUSHER_SPEED_RATIO_DEN,     //推杆转速比分母  
N	SETUP_PUSHER_DIS_RATIO_NUM,     	//推杆位置比分子
N	SETUP_PUSHER_DIS_RATIO_DEN,     	//推杆位置比分母*********888*555**********   
N	SETUP_PUSHER_CAN_CONNECTION,	    //推杆can线接法
N	SETUP_PUSHER_DIR,									//推杆轮方向调整			
N	
N	SETUP_MOTOR_DRIVER_BRAND,		  		//行走驱动器品牌 0.兴颂 ,1.步科 ,2.风得控 ,255.非can通讯
N	SETUP_STEERING_DRIVER_BRAND,	  	//转向驱动器品牌 0.兴颂 ,1.步科 ,2.风得控 ,255.非can通讯
N	SETUP_LIFTER_DRIVER_BRAND,		  	//举升驱动器品牌 0.兴颂 ,1.步科 ,2.风得控 ,255.非can通讯*********999*555**********
N	SETUP_SHIFTER_DRIVER_BRAND,		  	//移轴驱动器品牌 0.兴颂 ,1.步科 ,2.风得控 ,255.非can通讯
N	SETUP_PUSHER_DRIVER_BRAND,		  	//推杆驱动器品牌 0.兴颂 ,1.步科 ,2.风得控 ,255.非can通讯	
N	
N	SETUP_CONTROLLER1_IP1,			  		//服务器IP192
N	SETUP_CONTROLLER1_IP2,			  		//服务器IP168						
N	SETUP_CONTROLLER1_IP3,			  		//服务器IP0*********10*555**********
N	SETUP_CONTROLLER1_IP4,	 		  		//服务器IP30
N	SETUP_CONTROLLER2_IP1,			  		//服务器IP192
N	
N	SETUP_CONTROLLER2_IP2,			  		//服务器IP168
N	SETUP_CONTROLLER2_IP3,			  		//服务器IP0							
N	SETUP_CONTROLLER2_IP4,	 		  		//服务器IP30*********11*555**********											  									  
N	SETUP_CONTROLLER3_IP1,			  		//服务器IP192
N	SETUP_CONTROLLER3_IP2,			  		//服务器IP168
N	
N	SETUP_CONTROLLER3_IP3,			  		//服务器IP0
N	SETUP_CONTROLLER3_IP4,	 		  		//服务器IP30							  										  
N	SETUP_CONTROLLER4_IP1,			  		//服务器IP192
N	SETUP_CONTROLLER4_IP2,			  		//服务器IP168
N	SETUP_CONTROLLER4_IP3,			  		//服务器IP0							
N	
N	SETUP_CONTROLLER4_IP4,	 		  		//服务器IP30
N	SETUP_LIDAR2BASE_X,								//雷达到运动中心X距离(mm)
N	SETUP_LIDAR2BASE_Y,								//雷达到运动中心Y距离(mm)
N	SETUP_LIDAR2BASE_THETA,						//雷达和车体前进方向夹角(0.1度)(-45.0°写成3150对应315.0°)
N	SETUP_WHEEL_X_DIS,								//双驱动轮前进方向距离
N	SETUP_WHEEL_Y_DIS,								//双驱动轮横移方向距离
N	
N	SETUP_BATTERYTYPE = 98,						//电池类型1冠宇电池
N	SETUP_PLATFORM_TYPE = 99,					//agv平台类型:1悬臂轴,2双层SMT
N
N}ENUM_SETUP_DATA;//控制器保存的固定参数数据
N
Nextern unsigned long *pSetup;
Nextern void initSetup(unsigned long *pStart,unsigned long len);
Nextern void Setup_Process(void);
Nextern void Setup_Process_Map(void);
Nunsigned char PowerOn_ReadFlash_ConstData(void);
Nvoid PowerOn_WriteFlash_ConstData(void);
Nvoid PowerOff_ClearConstFlash(void);
N#endif
N
N
L 104 "..\..\User\bsp\bsp.h" 2
N#include "user_motor.h"
L 1 "..\..\User\MOTORDRIVER\user_motor.h" 1
N#ifndef __USER_MOTOR_H
N#define __USER_MOTOR_H
N#include "bsp.h"
N/*四个驱动轮设置和返回ID编号*/
N
Ntypedef struct
N{
N	int *setFlagOffset;//需要置位的标志位的地址
N	u8 *compareBuffer; //需要比较的buffer
N	u8 compareNum;	   //需要比较的长度
N	u8 noResponseNum;  //没有响应次数
N	int enable;        //已经使能则为 1 没有使能则为0
N	int enableDelay;	 //开使能后延迟启动,以防止抱闸未来得及开启。
N	int realEnable;	   //在有返回速度的时候才会置位1 代表真正使能上了
N	int motorState;	   //错误状态
N	int currentMode;   //当前模式
N	int tarFlag;	   	 //需要将enable或者currentMode标志位置为1则填写1
N	u16 driverID;	   	 //驱动器ID
N	int driverDir;	   //驱动器反向
N	int canSelect;	   //can口选择
N	u8 driverBrand;    //驱动器品牌
N	int setSpeed;	   	 //驱动器已经更新的速度
N	int responseValue; //应答标志位
N	float lastSpeed;	 //上次发送的速度
N	u8 initStep;  	   //是否初始化完成
N	u8 initSubStep;  	 //初始化延迟
N	u8 sendStep;				
N	u8 readAmpereCount;//读电流计数
N	u8 sendHeartBeatCount;//发送频率记录
N	u8 readStateCount;
N	
N	u8 dir;						 //兴颂驱动器 	运行方向
N	u8 sendBuffer[8];  //兴颂驱动器 发送
N	u8 slaveID;				 //兴颂驱动器 从站地址
N	
N	float sendSpeedCoefficient;	//发送速度系数
N	float getSpeedCoefficient;	//获取速度系数
N	float sendPosCoefficient;		//发送位置系数
N	double getPoseCoefficient;	//获取位置系数
N}DriverPrivateInfo;
N
Ntypedef struct
N{
N	int encoderValue;		//编码值
N	float encoderSpeed;	//当前速度
N	int   encoderPose;  //当前编码器位置
N	short torque;	   		//当前扭矩
N	float ampere;	   		//当前驱动器真实电流
N	float voltage; 			//电压
N	u8	  errorState;  	//错误状态
N}DriverPublicInfo;
N
Ntypedef struct
N{
N	float pose;		//目标位置或角度
N	float speed;	//目标速度
N	
N	float speedSlope;//设置加速度	
N	u8  mode;			//速度模式/位置模式
N	int clrPos;		//清位置
N}DriverCommandInfo;
N
Ntypedef struct
N{
N	u32 *driverShareErrorInfo;//由于结构体不能定义static 变量 此变量为所有驱动器可读写的变量 代表有驱动出现错误
N	DriverCommandInfo Command;//给电机发指令
N	DriverPrivateInfo Private;//电机模块内部数据,用户不需要读写
N	DriverPublicInfo  Public;//电机反馈的数据
N}DriverStruct;
N
Nextern DriverStruct DriverMotor1;//行走电机1
Nextern DriverStruct DriverMotor2;//行走电机2
Nextern DriverStruct DriverMotor3;//行走电机3
Nextern DriverStruct DriverMotor4;//行走电机4
N
Nextern DriverStruct DriverSteering1;//舵机 单转向或行走加转向
Nextern DriverStruct DriverSteering2;
Nextern DriverStruct DriverSteering3;
Nextern DriverStruct DriverSteering4;
N
Nextern DriverStruct DriverLifter1;//举升电机
Nextern DriverStruct DriverLifter2;
Nextern DriverStruct DriverLifter3;
Nextern DriverStruct DriverLifter4;
N
Nextern DriverStruct DriverShifter1;//移轴电机
Nextern DriverStruct DriverShifter2;
Nextern DriverStruct DriverShifter3;
N
Nextern DriverStruct DriverPusher1;//推杆电机
Nextern DriverStruct DriverPusher2;
Nextern DriverStruct DriverPusher3;
Nextern bool allDriverEnable;//所有驱动在速度为0时候不关使能
Xextern _Bool allDriverEnable;
N
Nextern void initDriverParam(void);
Nextern void init_driver(DriverStruct *Motor);
N
Nextern void set_speed_model(DriverStruct *Motor);
Nextern void set_pos_model(DriverStruct *Motor);
Nextern u8   set_speed(DriverStruct *Motor);
Nextern u8 	set_steering_speed(DriverStruct *Motor,DriverStruct *refMotor);
N
Nextern void get_actual_speed(DriverStruct *Motor);
Nextern void get_actual_pos(DriverStruct *Motor);
Nextern void get_driver_state(DriverStruct *Motor);
Nextern void get_driver_ampere(DriverStruct *Motor);
N
Nextern void clr_actual_pos(DriverStruct *Motor);
Nextern void send_heartbeat(DriverStruct *Motor);
Nextern void DriverDataProcess(DriverStruct *Motor,CanRxMsg *CanRxMsg);
Nextern void hins_driver_proc(DriverStruct *Motor);
Nextern void curtis_driver_proc(DriverStruct *Motor);
Nextern void get_driver_state(DriverStruct *Motor);
Nextern void DriverState(DriverStruct *Motor,float speedThreshold);
N#endif
L 105 "..\..\User\bsp\bsp.h" 2
N#include "user.h"
L 1 "..\..\User\bsp\BSP\user.h" 1
N#ifndef __USER_H
N#define __USER_H
N#include "bsp.h"
N#define FACTORYPARAMNUM 300
Ntypedef struct
N{
N    unsigned long  SystemParameter[FACTORYPARAMNUM]; //200个系统参数
X    unsigned long  SystemParameter[300]; 
N}SystemInfoStruct;
N
Ntypedef union
N{
N    SystemInfoStruct systemInfo;  
N    long buf[(sizeof(SystemInfoStruct)/4 + 1)];
N}SystemInfoUnion;
N
Nextern SystemInfoUnion        sysInfoUnion;
Nextern void ModeSwitch(void);
Nextern void _ModeSwitch(void);
Nextern void SoftTimerProcess(void);
N
Nextern unsigned char PowerOn_ReadFlash(void);
Nextern void PowerOn_WriteFlash_SystemInfoBackup(void);
Nextern unsigned char PowerOn_ReadFlash_SystemInfoBackup(void);
Nextern void PowerOn_ClearFlash_SystemInfoBackup(void);
Nextern void initFactoryParam(void);
N
Nunsigned char PowerOn_ReadFlash(void);
N
N#endif
N
N
L 106 "..\..\User\bsp\bsp.h" 2
N
N#include "CanSensor.h"
L 1 "..\..\User\HARAWARE\CanSensor.h" 1
N#ifndef _CANSENSOR_H
N#define _CANSENSOR_H
N#include "bsp.h"
N
N#define Music_Run 		1 //小车启动时语音
N#define Music_Pause 	2 //小车暂停时提示音  
N#define Music_Emg 		3 //小车急停时提示音
N#define Music_Derail	4 //小车脱轨时提示音
N#define Music_Laser  	5 //小车避障时提示音
N#define Music_Power  	6 //小车低电压时提示音
N#define Music_Driver  7 //小车驱动器报警时提示音
N#define Music         8 //正常放歌
N#define Music_Et      10//碰撞语音提示
N#define Music_Avoid    9 //agv交通管制
N#define Music_Arrivel 	11 //物料交接
N#define Music_close 	0 //不处理
N#define Music_Start 	14 //感谢使用创智科技智能系统产品
N#define CyMs 	15        //料框旋转失败
N#define UpDwMoterMs 	16 //升降马达过流报警
N#define Music_Warn 	    18 //料盒没放到位
N#define Music_SkipFull 			24 //满料车位置已满请移走相关的料车
N#define Music_EmpSkipFull 	    25 //空料车位置已满请移走相关的料车
N#define Music_EmpSkiEmp 	    26 //空料车位置没有料车请填补相关料车
N#define Music_WaitSkiEmp    	27 //待料位置没有料车请填补相关料车
N#define Music_UpSkiFull    	    28 //上料车位置有料请人工移走谢谢
N#define Music_DwSkiFull    	    29 //下料车位置有料请人工移走谢谢
N
N#define BattaryID 			 0x03C
N#define BattaryBackID_1  0x53C
N#define BattaryBackID_2  0x53D
N
N//电池通讯
Ntypedef struct
N{
N u8  BatterySet[8];//电池指令
N u8  BatterySend;  //开始发送
N u8  BatteryStop;  //暂停发送
N u32  BatteryReport;//上报周期
N u8  BatterySend_Stop;  //暂停与发送一体
N u8  BatteryOpen_StopCharging; //打开充电与关闭充电一体
N u8  BatteryPowerFailure; //断电指令
N u8  BatteryOpenCharging; //打开充电
N u8  BatteryStopCharging; //关闭充电
N u32 BatteryRepeatTime;   //重复上报时间
N u32 BatteryRepeatTimeADD;//重复上报时间累加
N 
N//接受电池数据参数
N//-------系统信息帧------
Nu32 TotalCurrent;  //总电流
Nbool Current_out_int; //0=放电   1充电
X_Bool Current_out_int; 
Nu32 SOC;
Nu32 TotalVoltage;  //总电压
Nu32 StateTable;    //总系统信息状态
N
Nbool StateTable0;   //充电故障        1表示充电故障  0正常
X_Bool StateTable0;   
Nbool StateTable1;   //放电过流        1表示放电过流  0正常
X_Bool StateTable1;   
Nbool StateTable2;   //接触器状态      1表示充电接触器闭合 0断开
X_Bool StateTable2;   
Nbool StateTable3;   //电池容量标志位2 
X_Bool StateTable3;   
Nbool StateTable4;   //电池容量标志位1	
X_Bool StateTable4;   
Nu8 quantity_electricity ; //电池电量显示
N//-------系统信息扩展帧-----
Nu32 DC_busVoltage; //直流母电压
Nu8 PowerOutage;  //已断电
Nu32 SOH; 
N//-------电池系统上报id信息帧------	
Nu32 ItemNumber;     //项目编号
Nu32 BatteryNumber;  //电池编号
N}CanBattery_Struct;
Nextern CanBattery_Struct CanBatteryStruct; //电池数据结构体
N
Nu8 Music_Select(u8 MusicS,u8 Vol);
Nu8 SendBatteryData(void);
Nvoid ReceiveBatteryData(CanRxMsg *CanRxMsg);
N#endif
L 108 "..\..\User\bsp\bsp.h" 2
N#include "Vision.h"
L 1 "..\..\User\SENSOR\Vision.h" 1
N#ifndef __VISION_H
N#define __VISION_H
N#include "bsp.h"
N#if P_SETUP_NAV_TYPE == 3
X#if 4 == 3
Svoid SlamDataProcess();
N#endif
W "..\..\User\SENSOR\Vision.h" 7 7 last line of file ends without a newline
N#endif
L 109 "..\..\User\bsp\bsp.h" 2
N#include "Camera.h"
L 1 "..\..\User\SENSOR\Camera.h" 1
N#ifndef __CAMERA_H
N#define __CAMERA_H
N#include "bsp.h"
N
Ntypedef struct
N{
N	int XCoordingData;
N	int YCoordingData;
N	float X_pixel;
N	float Y_pixel;
N	float angle;
N	float	CenterOffset;
N	unsigned char LocationSig;
N	unsigned char UpdataFlag;
N	int Number;
N	
N}CameraParameter;
Nextern CameraParameter Camera,CameraTwo;
W "..\..\User\SENSOR\Camera.h" 19 13 Deprecated declaration UpdateCameraData - give arg types
Nextern void UpdateCameraData();
W "..\..\User\SENSOR\Camera.h" 20 13 Deprecated declaration UpdateCameraData2 - give arg types
Nextern void UpdateCameraData2();
W "..\..\User\SENSOR\Camera.h" 21 7 last line of file ends without a newline
N#endif
L 110 "..\..\User\bsp\bsp.h" 2
N
N#include "HardDifferential.h"
L 1 "..\..\User\CHASSIS\HardDifferential.h" 1
N#if P_SETUP_CHASSIS_MODE == 0
X#if 0 == 0
N#include "user_motor.h"
Nextern void chassisGetAutoSpeed(u8 *CurrentDir);
Nextern void chassisControlAuto(void);
Nextern void chassisControlManual(void);
N#endif
L 112 "..\..\User\bsp\bsp.h" 2
N
N#include "Trackless.h"
L 1 "..\..\User\NAVAGATION\Trackless.h" 1
N#ifndef _TRACKLESS_H
N#define _TRACKLESS_H
N#include "bsp.h"
N
W "..\..\User\NAVAGATION\Trackless.h" 5 13 Deprecated declaration slamNavigation - give arg types
Nextern void slamNavigation();
W "..\..\User\NAVAGATION\Trackless.h" 6 7 last line of file ends without a newline
N#endif
L 114 "..\..\User\bsp\bsp.h" 2
N#include "QRcode.h"
L 1 "..\..\User\NAVAGATION\QRcode.h" 1
N#ifndef __QRCODE_H
S#define __QRCODE_H
S#include "bsp.h"
S
Stypedef struct
S{
S	float setSpeed;
S	float encodeSpeed;
S	int voltage;
S	short enable;
S	float speedSlope;
S}KincoStructInfo;
Stypedef struct
S{
S	float palstance;
S	float angle;
S	float angleCompensation;
S}IMUdata;
Stypedef struct
S{
S	u8 initState;//速度模式初始化步骤
S	float setSpeed;//目标速度
S	float setPos;//设置目标位置
S	float encodePos;//反馈实际位置
S	u8 		runState;//举升运动状态
S	int 	liftState;//-1原点  1最高点 0过程中
S	
S}LifterStructInfo;
S
Sextern LifterStructInfo Lifter1;
S
Stypedef struct
S{
S	u8 initState;
S	float setSpeed;
S	float encodeSpeed;
S	float encodeAngle;//旋转角度
S	int 	voltage;
S	short enable;
S	u8 		runState;//旋转运动状态
S	int 	rotateState;
S	int 	turnAngle;
S}RotateStructInfo;
S
Sextern RotateStructInfo Rotate1;
S
S
Sextern IMUdata IMU;
S
Sextern void getPosAngleOffset(float *PosOffset,float *Theta);
Sextern KincoStructInfo KincoStruct1,KincoStruct2;
Sextern void QRcodeNavigation();
W "..\..\User\NAVAGATION\QRcode.h" 53 7 last line of file ends without a newline
N#endif
L 115 "..\..\User\bsp\bsp.h" 2
N
N#include "ForkLift.h"
L 1 "..\..\User\PLATFORM\ForkLift.h" 1
N#ifndef __FORKLIFT_H
N#define __FORKLIFT_H
N#include "bsp.h"
N
W "..\..\User\PLATFORM\ForkLift.h" 5 7 last line of file ends without a newline
N#endif
L 117 "..\..\User\bsp\bsp.h" 2
N#include "MovableLifterArm.h"
L 1 "..\..\User\PLATFORM\MovableLifterArm.h" 1
N#ifndef _MOVABLELIFTERARM_H
N#define _MOVABLELIFTERARM_H
N#include "bsp.h"
N
N#define LIFTMAX   -50
N#define LIFTMIN   -350
N
N#define SHIFTMAX   71
N#define SHIFTMIN   -28
N
N#define PUSHMAX   300
N#define PUSHMIN   300
N
N#define QR_BIAS_MIN  0.004  //二维码允许误差
N
W "..\..\User\PLATFORM\MovableLifterArm.h" 16 13 Deprecated declaration platformDataProcess - give arg types
Nextern void platformDataProcess();//悬臂轴输入信号
N
W "..\..\User\PLATFORM\MovableLifterArm.h" 18 13 Deprecated declaration platformControlManual - give arg types
Nextern void platformControlManual();//悬臂轴点动控制
N
W "..\..\User\PLATFORM\MovableLifterArm.h" 20 13 Deprecated declaration platformControlAuto - give arg types
Nextern void platformControlAuto();//悬臂轴自动对接
N
Nextern void initPlaformParam(void);//参数更新
N
Nextern void commandActionAnalysis(int dataOne,int dataTwo);//SETVMOT动作指令解析
W "..\..\User\PLATFORM\MovableLifterArm.h" 25 8 last line of file ends without a newline
N#endif 
L 118 "..\..\User\bsp\bsp.h" 2
N#include "DoubleSMT.h"
L 1 "..\..\User\PLATFORM\DoubleSMT.h" 1
N#ifndef _DOUBLESMT_H
N#define _DOUBLESMT_H
N#include "bsp.h"
N
N#define LIFTARRIVEVALUE		0		//举升到达目标位置阈值
N
W "..\..\User\PLATFORM\DoubleSMT.h" 7 13 Deprecated declaration platformDataProcess - give arg types
Nextern void platformDataProcess();
N
W "..\..\User\PLATFORM\DoubleSMT.h" 9 13 Deprecated declaration platformControlManual - give arg types
Nextern void platformControlManual();
N
W "..\..\User\PLATFORM\DoubleSMT.h" 11 13 Deprecated declaration platformControlAuto - give arg types
Nextern void platformControlAuto();
N
Nextern void initPlaformParam(void);
N
N /*SETVMOT动作指令解析*/
Nextern void commandActionAnalysis(int dataOne,int dataTwo);
N
W "..\..\User\PLATFORM\DoubleSMT.h" 18 8 last line of file ends without a newline
N#endif 
L 119 "..\..\User\bsp\bsp.h" 2
N#include "SMT.h"
L 1 "..\..\User\PLATFORM\SMT.h" 1
N#ifndef _SMT_H_
N#define _SMT_H_
N#include "bsp.h"
N
W "..\..\User\PLATFORM\SMT.h" 5 13 Deprecated declaration platformDataProcess - give arg types
Nextern void platformDataProcess();
N
W "..\..\User\PLATFORM\SMT.h" 7 13 Deprecated declaration platformControlManual - give arg types
Nextern void platformControlManual();
N
W "..\..\User\PLATFORM\SMT.h" 9 13 Deprecated declaration platformControlAuto - give arg types
Nextern void platformControlAuto();
N
Nextern void initPlaformParam(void);
N
N /*SETVMOT动作指令解析*/
Nextern void commandActionAnalysis(int dataOne,int dataTwo);
W "..\..\User\PLATFORM\SMT.h" 15 7 last line of file ends without a newline
N#endif
L 120 "..\..\User\bsp\bsp.h" 2
N#include "ch_serial.h"
L 1 "..\..\User\HARAWARE\ch_serial.h" 1
N#ifndef __CH_SERIAL_H_
N#define	__CH_SERIAL_H_
N
N#include <stdint.h>
N#include <string.h>
N#include <stdio.h>
N#include "bsp.h"
N
N/* dump logs */
N//#define  CH_DEBUG
N
N#define MAXRAWLEN       (512)       /* max raw frame long */
N#define MAX_NODE_SIZE   (16)        /* max support node count */
N
N/* data items */
N#define kItemID                    (0x90)
N#define kItemAccRaw                (0xA0)
N#define kItemGyrRaw                (0xB0)
N#define kItemMagRaw                (0xC0)
N#define kItemRotationEul           (0xD0)
N#define kItemRotationQuat          (0xD1)
N#define kItemPressure              (0xF0)
N#define KItemIMUSOL                (0x91)
N#define KItemGWSOL                 (0x62)
N
Ntypedef struct
N{
N    uint32_t id;            /* user defined ID       */
N    float acc[3];           /* acceleration          */
N    float gyr[3];           /* angular velocity      */  
N    float mag[3];           /* magnetic field        */
N    float eul[3];           /* attitude: eular angle */
N    float quat[4];          /* attitude: quaternion  */
N    float pressure;         /* air pressure          */
N    uint32_t timestamp;
N}ch_imu_data_t;
N
Ntypedef struct
N{
N    int nbyte;                          /* number of bytes in message buffer */ 
N    int len;                            /* message length (bytes) */
N    uint8_t buf[MAXRAWLEN];             /* message raw buffer */
X    uint8_t buf[(512)];              
N    uint8_t gwid;                       /* network ID(HI222) */
N    uint8_t nimu;                       /* # of imu (HI222) */
N    
N    ch_imu_data_t imu[MAX_NODE_SIZE];   /* imu data list, if (HI226/HI229/CH100/CH110, use imu[0]) */
X    ch_imu_data_t imu[(16)];    
N    uint8_t item_code[8];               /* item code recv in one frame */
N    uint8_t nitem_code;                 /* # of item code */
N}raw_t;
N
N
N
N/* input CHAOHE raw message from stream -----------------------------------------
N* fetch next raw data and input a message from stream
N* args   : raw_t *raw   IO     receiver raw data control struct
N*          uint8_t data I   stream data (1 byte)
N* return : status (-1: error message, 0: no message, 1: input data successfully)
N*/
Nint ch_serial_input(raw_t *raw, uint8_t data);
N
N/* debug function -----------------------------------------
N*  dump decode information, need open  CH_DEBUG
N* args   : raw_t *raw   IO     receiver raw data control struct
N*/
Nvoid ch_dump_imu_data(raw_t *raw);
N
W "..\..\User\HARAWARE\ch_serial.h" 67 6 Deprecated declaration DecodeIMUdata - give arg types
Nvoid DecodeIMUdata();
N#endif
N
L 121 "..\..\User\bsp\bsp.h" 2
N
N
Nvoid bsp_Init(void);
Nvoid bsp_DelayMS(uint32_t _ulDelayTime);
Nvoid bsp_DelayUS(uint32_t _ulDelayTime);
Nvoid BSP_Tick_Init (void);
N
N/**信号量***/
Nextern OS_SEM RFIDSEM;
Nextern int InitFlag;
N
N#define PI		3.1415926f
N
N#endif
N
N/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/
L 4 "..\..\User\NAVAGATION\QRcode.h" 2
N
Ntypedef struct
N{
N	float setSpeed;
N	float encodeSpeed;
N	int voltage;
N	short enable;
N	float speedSlope;
N}KincoStructInfo;
Ntypedef struct
N{
N	float palstance;
N	float angle;
N	float angleCompensation;
N}IMUdata;
Ntypedef struct
N{
N	u8 initState;//速度模式初始化步骤
N	float setSpeed;//目标速度
N	float setPos;//设置目标位置
N	float encodePos;//反馈实际位置
N	u8 		runState;//举升运动状态
N	int 	liftState;//-1原点  1最高点 0过程中
N	
N}LifterStructInfo;
N
Nextern LifterStructInfo Lifter1;
N
Ntypedef struct
N{
N	u8 initState;
N	float setSpeed;
N	float encodeSpeed;
N	float encodeAngle;//旋转角度
N	int 	voltage;
N	short enable;
N	u8 		runState;//旋转运动状态
N	int 	rotateState;
N	int 	turnAngle;
N}RotateStructInfo;
N
Nextern RotateStructInfo Rotate1;
N
N
Nextern IMUdata IMU;
N
Nextern void getPosAngleOffset(float *PosOffset,float *Theta);
Nextern KincoStructInfo KincoStruct1,KincoStruct2;
W "..\..\User\NAVAGATION\QRcode.h" 52 13 Deprecated declaration QRcodeNavigation - give arg types
Nextern void QRcodeNavigation();
W "..\..\User\NAVAGATION\QRcode.h" 53 7 last line of file ends without a newline
N#endif
L 2 "..\..\User\NAVAGATION\QRcode.c" 2
N
NKincoStructInfo KincoStruct1,KincoStruct2;
NIMUdata IMU;
NLifterStructInfo Lifter1;
NRotateStructInfo Rotate1;
N#if P_SETUP_NAV_TYPE==1
X#if 4==1
S/******二维码坐标更新*******/
Svoid CameraDataUpdate()
S{
S	CurrentCenterPoint.TarX = Camera.XCoordingData + navi.Public.DistanceAgvToSTART; //X补偿
S
S	CurrentCenterPoint.TarY = Camera.YCoordingData + navi.Public.CenterOffset; //Y补偿
S
S	CurrentCenterPoint.CurAngle = Camera.angle + agv.Command.W_compensation; //W补偿
S}
S
Sunsigned char ArriveJugement()//到达判断
S{
S	static u8 lastStopFlagL = 0,lastStopFlagR = 0;
S	if(Camera.XCoordingData == TargetPoint.TarX&&Camera.YCoordingData == TargetPoint.TarY)//识别到二维码停车
S	{
S
S//		if(agv.Command.RunState == 0 || agv.Command.RunState == 2)//沿X轴前进
S		{
S			if (fabs(Camera.X_pixel) < POSARRIVE_RANGE)
S			{
S				return 1;
S			}
S			else
S			{
S				return 0;
S			}
S		}
S//		else//沿Y轴前进
S//		{
S//			if (fabs(Camera.Y_pixel) < POSARRIVE_RANGE)
S//			{
S//				return 1;
S//			}
S//			else
S//				return 0;
S//		}
S	}
S	return 0;
S}
S
S//更新执行站点
Svoid pathUpdate(u8 *CurrentID)
S{
S	static int count = 0;
S    static int lastTime = 0;
S		static float lastAnglediff = 0;
S    /*****************到达站点判断以及切换站点**********************/
S    if (agv.Command.CurDirection == 1 || agv.Command.CurDirection == 2) //直行判断
S    {
S        //到达站点判断
S        if (ArriveJugement()==1)
S        {
S            *CurrentID += 1;
S						count = 0;
S					navi.Public.DistanceAgvToSTART = 0;
S/****单机测试***/
S#if P_SETUP_SINGLE_PLAYER == 1
S
S//					}
S#elif P_SETUP_SINGLE_PLAYER == 0
S            if (*CurrentID >= traffic_land_marks.size)
S            {
S								 SetAlarm(0x200); 
S						
S							 agv.Public.i_UpdatePathSig = 1;
S            }
S#endif
S            Uart_Printf(COM1, "站点更新,当前站点 = %d 当前方向 = %d Error_Flag = %x\r\n", agv.Command.standSiteID, agv.Command.CurDirection, agv.Public.Error_Flag);
S        }
S				lastAnglediff = 0;
S    }
S    else if (agv.Command.CurDirection == 7 || agv.Command.CurDirection == 8 || agv.Command.CurDirection == 9 || agv.Command.CurDirection == 10) //弧线转弯
S    {
S        //站点更新
S        if ((fabs(navi.Public.AngleDifference) <= TURNINGOFF_ANGLE)||(navi.Public.AngleDifference*lastAnglediff<0))
S        {
S            *CurrentID += 1;
S        }
S				lastAnglediff = navi.Public.AngleDifference;
S    }
S//		if(*CurrentID == 1 || *CurrentID == 3)
S//		{
S//			if(count ++ <5000)
S//			{
S//				agv.Command.DispatchSpeed = 0;
S//			}
S//			else
S//				agv.Command.DispatchSpeed = traffic_land_marks.land_marks[*CurrentID - 1].DispatchSpeed; //系统下发速度
S//		}	
S//		else
S			agv.Command.DispatchSpeed = traffic_land_marks.land_marks[*CurrentID - 1].DispatchSpeed; //系统下发速度
S
S    agv.Command.CurDirection = traffic_land_marks.land_marks[*CurrentID - 1].Direction; //当前站点运行方向
S		
S		agv.Command.LaserArea = traffic_land_marks.land_marks[*CurrentID - 1].LaserArea;
S
S    if (*CurrentID < traffic_land_marks.size) //当前站点不是最后站点,保存下一个站点方向和光电停车信号
S    {
S        agv.Command.LightStopSig = traffic_land_marks.land_marks[*CurrentID].LightStopSig; //目标站点广电信号
S
S        agv.Command.NextDirection = traffic_land_marks.land_marks[*CurrentID].Direction; //下个站点运行方向
S
S        agv.Command.NextDispatchSpeed = traffic_land_marks.land_marks[*CurrentID].DispatchSpeed;
S    }
S    else //已经是最后一个站点,没有下一个站点清零
S    {
S        agv.Command.LightStopSig = 0;
S
S        agv.Command.NextDirection = 0;
S
S        agv.Command.NextDispatchSpeed = 0;
S    }
S
S    StartPoint.TarX = traffic_land_marks.land_marks[*CurrentID - 1].pose[0]; //当前点(起点)
S
S    StartPoint.TarY = traffic_land_marks.land_marks[*CurrentID - 1].pose[1];
S
S    TargetPoint.TarX = traffic_land_marks.land_marks[*CurrentID].pose[0]; //目标点(终点)
S
S    TargetPoint.TarY = traffic_land_marks.land_marks[*CurrentID].pose[1];
S		if(StartPoint.TarX == TargetPoint.TarX)
S		{
S			if(TargetPoint.TarY > StartPoint.TarY)
S			{
S				agv.Command.RunState = 3;
S			}
S			else
S				agv.Command.RunState = 1;
S		}
S		else if(StartPoint.TarY == TargetPoint.TarY)
S		{
S			if(TargetPoint.TarX > StartPoint.TarX)
S			{
S				agv.Command.RunState = 0;
S			}
S			else
S				agv.Command.RunState = 2;
S		}
S		
S//		agv.Command.RunState = traffic_land_marks.land_marks[*CurrentID - 1].RunState;//0沿0度方向  1沿90度方向  2沿180度方向  3沿270度方向
S//		if(StartPoint.TarX == TargetPoint.TarX && StartPoint.TarY != TargetPoint.TarY)
S//		{
S//			agv.Command.RunStraightState = 1;//沿Y轴直行
S//		}
S//		else if(StartPoint.TarY == TargetPoint.TarY && StartPoint.TarX != TargetPoint.TarX)
S//		{
S//			agv.Command.RunStraightState = 0;//沿X轴直行
S//		}
S
S    if (*CurrentID >= 2 && *CurrentID < traffic_land_marks.size - 1) //实现弧线转弯需要有四个点位计算
S    {
S        PointOne.TarX = traffic_land_marks.land_marks[*CurrentID - 2].pose[0];
S
S        PointOne.TarY = traffic_land_marks.land_marks[*CurrentID - 2].pose[1];
S
S        PointTwo.TarX = traffic_land_marks.land_marks[*CurrentID - 1].pose[0];
S
S        PointTwo.TarY = traffic_land_marks.land_marks[*CurrentID - 1].pose[1];
S
S        PointThree.TarX = traffic_land_marks.land_marks[*CurrentID].pose[0];
S
S        PointThree.TarY = traffic_land_marks.land_marks[*CurrentID].pose[1];
S
S        PointFour.TarX = traffic_land_marks.land_marks[*CurrentID + 1].pose[0];
S
S        PointFour.TarY = traffic_land_marks.land_marks[*CurrentID + 1].pose[1];
S    }
S}
S
Svoid getPosAngleOffset(float *PosOffset,float *Theta)
S{
S	double Vx = (KincoStruct1.encodeSpeed+KincoStruct2.encodeSpeed)/2*0.966;//实际线速度
S	double palstance = -(KincoStruct1.encodeSpeed - KincoStruct2.encodeSpeed)/450*0.965;//角速度
S	static int lastTime = 0,lastTime2 = 0;
S	float Time = 0;
S	static int i = 0;
S	
S		*Theta = IMU.angle + IMU.angleCompensation;
S		if(*Theta > 2*PI)
S		{
S			*Theta -= 2*PI;
S		}
S		else if(*Theta < -2*PI)
S		{
S			*Theta += 2*PI;
S		}
S
S	if(Camera.UpdataFlag == 1)//有码
S	{		
S			IMU.angleCompensation = Camera.angle - IMU.angle;
S//		if(agv.Command.RunState == 2 || agv.Command.RunState == 0)
S//		{
S//			if(agv.Command.SetBaseSpeed > 500)
S//			{
S				if(agv.Command.RunState == 2)
S				{
S					*PosOffset = Camera.Y_pixel*1;
S				}
S				else if(agv.Command.RunState == 0)
S				{
S					*PosOffset = Camera.Y_pixel*1 + 5;
S				}
S				else if(agv.Command.RunState == 3)
S				{
S					*PosOffset = Camera.Y_pixel*1 + 5;
S				}
S				else
S				{
S					*PosOffset = Camera.Y_pixel*1 + 5;
S				}
S//			}
S//			else
S//				*PosOffset = Camera.Y_pixel*1;
S//		}
S//		else
S//		{
S//			*PosOffset = Camera.Y_pixel*1+13;
S//		}
S		 
S		if(i++ >20)
S		{
S			i = 0;
S//			Uart_Printf(COM1,"速度 = %.2f  %.2f  Vx = %.2f  角速度 = %.5f  行走距离 = %.2f 位置偏移 = %.2f  角度 = %.2f 惯导角度 = %.2f  距离目标 = %.2f\r\n",
S//			KincoStruct1.encodeSpeed,KincoStruct2.encodeSpeed,Vx,IMU.palstance,navi.Public.DistanceAgvToSTART,*PosOffset,*Theta*57.3,IMU.angle*57.3,navi.Public.DistanceAgvToTARGET);
S		}
S	
S	}
S	else//无码
S	{
S		if(agv.Public.SystemTime - lastTime >= 20)//20Ms积分一次
S		{
S			lastTime = agv.Public.SystemTime;
S			Time = ((double)TIM_GetCounter(TIM7)) / 10.0f;
S			TIM_SetCounter(TIM7, 0);
S			CalculateXBias(Vx,0,IMU.palstance,Time*0.001,0,PosOffset,Theta);
S//			Uart_Printf(COM1,"速度 = %.2f  %.2f  Vx = %.2f  角速度 = %.5f  行走距离 = %.2f 位置偏移 = %.2f  角度 = %.2f 惯导角度 = %.2f  距离目标 = %.2f\r\n",
S//			KincoStruct1.encodeSpeed,KincoStruct2.encodeSpeed,Vx,IMU.palstance,navi.Public.DistanceAgvToSTART,*PosOffset,*Theta*57.3,IMU.angle*57.3,navi.Public.DistanceAgvToTARGET);
S		}
S	}
S	if((agv.Public.SystemTime - lastTime2 >= 24))
S	{
S		lastTime2 = agv.Public.SystemTime;
S		CalculateXBias(Vx,0,IMU.palstance,0.024,&navi.Public.DistanceAgvToSTART,0,Theta);
S	}
S}
S
S//计算偏移量 设置不同运动方式的pid值
Svoid calculateOffsetValue(unsigned char Direction)
S{
S    if (Direction == 7 || Direction == 8 || Direction == 9 || Direction == 10) //转弯需要计算圆心坐标
S    {
S        CircleCenterPoint = GetCircleCenterPoint(CurrentCenterPoint,PointThree,PointFour);                      //计算圆心坐标
S        navi.Private.SetCalculationRadius = TwoPointDistance(PointTwo, CircleCenterPoint); //入弯点到圆心的距离
S    }
S		
S    switch (Direction)
S    {
S    case 0:
S        break;
S		
S    case 1:                                                                            //前进
S        getPosAngleOffset(&navi.Public.CenterOffset,&CurrentCenterPoint.CurAngle);//获取当前角度和位置偏移量
S				
S				navi.Private.TarAngle = CalculatingDirectionAngle(StartPoint, TargetPoint); //求出目标方向角度
S
S        navi.Public.AngleDifference = CalculatingCurrentAndTargetAngle(CurrentCenterPoint.CurAngle, navi.Private.TarAngle); //角度偏移
S
S//        navi.Public.CenterOffset = -getPosAngleOffset(); //车中心横向偏移量
S        //根据不同车型和不同方向设置pid参数
S		if(agv.Command.SetBaseSpeed >= 500)
S		{
S			pid = navi.PIDPara[0];
S		}
S		else if(agv.Command.SetBaseSpeed <500 && agv.Command.SetBaseSpeed >= 500 >200)
S        pid = navi.PIDPara[1];
S		else
S			pid = navi.PIDPara[2];
S		
S        if (navi.Public.DistanceAgvToTARGET < agv.Parameter.OnlyAnglePos) //小于500MM只纠角度
S            pid = navi.PIDPara[3];
S        break;
S				
S    case 2: 			//后退
S				getPosAngleOffset(&navi.Public.CenterOffset,&CurrentCenterPoint.CurAngle);//获取当前角度和位置偏移量
S		
S				navi.Private.TarAngle = CalculatingDirectionAngle(StartPoint, TargetPoint); //求出目标方向角度
S
S        navi.Public.AngleDifference = CalculatingCurrentAndTargetAngle(CurrentCenterPoint.CurAngle, navi.Private.TarAngle); //角度偏移
S
S//        navi.Public.CenterOffset = getPosAngleOffset(); //车中心横向偏移量
S
S        pid = navi.PIDPara[1];
S//        if (navi.Public.VerticalDistanceAgvToTARGET < agv.Parameter.OnlyAnglePos) //小于500MM只纠角度
S//        {
S//            pid = navi.PIDPara[3];
S//            pid.AngleCofficient *= -1;
S//        }
S        break;
S				
S    case 3:
S				getPosAngleOffset(&navi.Public.CenterOffset,&CurrentCenterPoint.CurAngle);//获取当前角度和位置偏移量
S        break;
S		
S    case 4:
S				getPosAngleOffset(&navi.Public.CenterOffset,&CurrentCenterPoint.CurAngle);//获取当前角度和位置偏移量
S        break;
S		
S    default:
S        break;
S    }
S}
S
S//根据P值,I值,D值,位置偏差权重,角度偏差权重,输出偏移值
Svoid offsetCompensationOutput(navigationPID *Pid)
S{
S    static int i = 0;
S    static float LastCenterOffset = 0, LastAngleOffset = 0;
S    static float Error = 0, DcalError = 0, LastError = 0, SumError = 0;
S    //当位置和角度偏差变化重新计算
S    if (LastCenterOffset != navi.Public.CenterOffset || LastAngleOffset != navi.Public.AngleDifference)
S    {
S        LastCenterOffset = navi.Public.CenterOffset;
S
S        LastAngleOffset = navi.Public.AngleDifference;
S        //取角度和位置偏差做为偏差补偿量
S        Error = navi.Public.CenterOffset * Pid->PosCofficient + navi.Public.AngleDifference * 180 / PI * Pid->AngleCofficient;
S
S        DcalError = Error - LastError; //误差变化量
S
S        LastError = Error; //记录上次偏差
S    }
S		
S    navi.Private.OutputOffset = Error * Pid->Kp + SumError * Pid->Ki + DcalError * Pid->Kd;
S
S    if (navi.Private.OutputOffset >= Pid->MaxLimit)
S        navi.Private.OutputOffset = Pid->MaxLimit;
S    else if (navi.Private.OutputOffset <= -Pid->MaxLimit)
S        navi.Private.OutputOffset = -Pid->MaxLimit;
S		
S		#if PRINT_TYPE_SELECT == 1
S    if (i++ > PRINT_FREQUENCY)
S    {
S        i = 0;
S        //		Uart_Printf(COM1,"当前方向 = %d,角度偏差 = %.2f,位置偏差 = %.2f,输出补偿值 = %.2f\r\n",
S        //		agv.Command.CurDirection,navi.Public.AngleDifference*57.3,navi.Public.CenterOffset,navi.Private.OutputOffset);
S//        Uart_Printf(COM1, "X = %d Y = %d, 当前角度 = %.2f 目标角度 = %.2f 角度偏差 = %.2f,位置偏差 = %.2f,输出补偿值 = %.2f\r\n", 
S//						XCoordingData, YCoordingData, 
S//						CurrentCenterPoint.CurAngle,navi.Private.TarAngle,
S//						navi.Public.AngleDifference * 57.3, navi.Public.CenterOffset, navi.Private.OutputOffset);
S    }
S		#endif
S}
S
Svoid QRcodeNavigation()
S{
S		CameraDataUpdate();
S	
S    pathUpdate(&agv.Command.standSiteID); //执行路径更新 和站点++判断。
S
S    calculateOffsetValue(agv.Command.CurDirection); //计算偏移量和设置不同运动方式的pid值
S
S    offsetCompensationOutput(&pid); 			//计算处理得到补偿值***********
S	
S//		CalculateDistance();
S}
S
N#endif
N
N
N
N
N